Revision f1b0aa5d target-mips/op.c
| b/target-mips/op.c | ||
|---|---|---|
| 1260 | 1260 |
{
|
| 1261 | 1261 |
/* Large physaddr not implemented */ |
| 1262 | 1262 |
/* 1k pages not implemented */ |
| 1263 |
env->CP0_EntryLo0 = (int32_t)T0 & 0x3FFFFFFF;
|
|
| 1263 |
env->CP0_EntryLo0 = T0 & 0x3FFFFFFF; |
|
| 1264 | 1264 |
RETURN(); |
| 1265 | 1265 |
} |
| 1266 | 1266 |
|
| ... | ... | |
| 1268 | 1268 |
{
|
| 1269 | 1269 |
/* Large physaddr not implemented */ |
| 1270 | 1270 |
/* 1k pages not implemented */ |
| 1271 |
env->CP0_EntryLo1 = (int32_t)T0 & 0x3FFFFFFF;
|
|
| 1271 |
env->CP0_EntryLo1 = T0 & 0x3FFFFFFF; |
|
| 1272 | 1272 |
RETURN(); |
| 1273 | 1273 |
} |
| 1274 | 1274 |
|
| ... | ... | |
| 1338 | 1338 |
uint32_t val, old; |
| 1339 | 1339 |
uint32_t mask = env->Status_rw_bitmask; |
| 1340 | 1340 |
|
| 1341 |
/* No reverse endianness, no MDMX/DSP, no 64bit ops,
|
|
| 1342 |
no 64bit addressing implemented. */
|
|
| 1343 |
val = (int32_t)T0 & mask;
|
|
| 1341 |
/* No reverse endianness, no MDMX/DSP, no 64bit ops |
|
| 1342 |
implemented. */ |
|
| 1343 |
val = T0 & mask; |
|
| 1344 | 1344 |
old = env->CP0_Status; |
| 1345 | 1345 |
if (!(val & (1 << CP0St_EXL)) && |
| 1346 | 1346 |
!(val & (1 << CP0St_ERL)) && |
| ... | ... | |
| 1395 | 1395 |
|
| 1396 | 1396 |
void op_mtc0_epc (void) |
| 1397 | 1397 |
{
|
| 1398 |
env->CP0_EPC = (int32_t)T0;
|
|
| 1398 |
env->CP0_EPC = T0; |
|
| 1399 | 1399 |
RETURN(); |
| 1400 | 1400 |
} |
| 1401 | 1401 |
|
| ... | ... | |
| 1424 | 1424 |
{
|
| 1425 | 1425 |
/* Watch exceptions for instructions, data loads, data stores |
| 1426 | 1426 |
not implemented. */ |
| 1427 |
env->CP0_WatchLo = (int32_t)(T0 & ~0x7);
|
|
| 1427 |
env->CP0_WatchLo = (T0 & ~0x7); |
|
| 1428 | 1428 |
RETURN(); |
| 1429 | 1429 |
} |
| 1430 | 1430 |
|
| ... | ... | |
| 1453 | 1453 |
|
| 1454 | 1454 |
void op_mtc0_depc (void) |
| 1455 | 1455 |
{
|
| 1456 |
env->CP0_DEPC = (int32_t)T0;
|
|
| 1456 |
env->CP0_DEPC = T0; |
|
| 1457 | 1457 |
RETURN(); |
| 1458 | 1458 |
} |
| 1459 | 1459 |
|
| ... | ... | |
| 1489 | 1489 |
|
| 1490 | 1490 |
void op_mtc0_errorepc (void) |
| 1491 | 1491 |
{
|
| 1492 |
env->CP0_ErrorEPC = (int32_t)T0;
|
|
| 1492 |
env->CP0_ErrorEPC = T0; |
|
| 1493 | 1493 |
RETURN(); |
| 1494 | 1494 |
} |
| 1495 | 1495 |
|
| ... | ... | |
| 1500 | 1500 |
} |
| 1501 | 1501 |
|
| 1502 | 1502 |
#ifdef TARGET_MIPS64 |
| 1503 |
void op_mtc0_xcontext (void) |
|
| 1504 |
{
|
|
| 1505 |
env->CP0_XContext = (env->CP0_XContext & 0x1ffffffffULL) | (T0 & ~0x1ffffffffULL); |
|
| 1506 |
RETURN(); |
|
| 1507 |
} |
|
| 1508 |
|
|
| 1503 | 1509 |
void op_dmfc0_entrylo0 (void) |
| 1504 | 1510 |
{
|
| 1505 | 1511 |
T0 = env->CP0_EntryLo0; |
| ... | ... | |
| 1565 | 1571 |
T0 = env->CP0_ErrorEPC; |
| 1566 | 1572 |
RETURN(); |
| 1567 | 1573 |
} |
| 1568 |
|
|
| 1569 |
void op_dmtc0_entrylo0 (void) |
|
| 1570 |
{
|
|
| 1571 |
/* Large physaddr not implemented */ |
|
| 1572 |
/* 1k pages not implemented */ |
|
| 1573 |
env->CP0_EntryLo0 = T0 & 0x3FFFFFFF; |
|
| 1574 |
RETURN(); |
|
| 1575 |
} |
|
| 1576 |
|
|
| 1577 |
void op_dmtc0_entrylo1 (void) |
|
| 1578 |
{
|
|
| 1579 |
/* Large physaddr not implemented */ |
|
| 1580 |
/* 1k pages not implemented */ |
|
| 1581 |
env->CP0_EntryLo1 = T0 & 0x3FFFFFFF; |
|
| 1582 |
RETURN(); |
|
| 1583 |
} |
|
| 1584 |
|
|
| 1585 |
void op_dmtc0_context (void) |
|
| 1586 |
{
|
|
| 1587 |
env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF); |
|
| 1588 |
RETURN(); |
|
| 1589 |
} |
|
| 1590 |
|
|
| 1591 |
void op_dmtc0_epc (void) |
|
| 1592 |
{
|
|
| 1593 |
env->CP0_EPC = T0; |
|
| 1594 |
RETURN(); |
|
| 1595 |
} |
|
| 1596 |
|
|
| 1597 |
void op_dmtc0_watchlo0 (void) |
|
| 1598 |
{
|
|
| 1599 |
/* Watch exceptions for instructions, data loads, data stores |
|
| 1600 |
not implemented. */ |
|
| 1601 |
env->CP0_WatchLo = T0 & ~0x7; |
|
| 1602 |
RETURN(); |
|
| 1603 |
} |
|
| 1604 |
|
|
| 1605 |
void op_dmtc0_xcontext (void) |
|
| 1606 |
{
|
|
| 1607 |
env->CP0_XContext = (env->CP0_XContext & 0xffffffff) | (T0 & ~0xffffffff); |
|
| 1608 |
RETURN(); |
|
| 1609 |
} |
|
| 1610 |
|
|
| 1611 |
void op_dmtc0_depc (void) |
|
| 1612 |
{
|
|
| 1613 |
env->CP0_DEPC = T0; |
|
| 1614 |
RETURN(); |
|
| 1615 |
} |
|
| 1616 |
|
|
| 1617 |
void op_dmtc0_errorepc (void) |
|
| 1618 |
{
|
|
| 1619 |
env->CP0_ErrorEPC = T0; |
|
| 1620 |
RETURN(); |
|
| 1621 |
} |
|
| 1622 | 1574 |
#endif /* TARGET_MIPS64 */ |
| 1623 | 1575 |
|
| 1624 | 1576 |
/* CP1 functions */ |
Also available in: Unified diff