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Revision f1cb0951

IDf1cb0951c5298753652a73cfd8efc0b1a82f37de

Added by Nathan Froyd over 11 years ago

MIPS: Correct FCR0 initialization

This change addresses a problem where QEMU incorrectly traps on
floating-point MADD group instructions with SIGILL, at least while
emulating MIPS32r2 processors.  These instructions use the COP1X major
opcode and include ones like:
madd.d    $f2,$f4,$f2,$f6
Here's Nathan's original analysis of the problem:

"QEMU essentially does:

d = find_cpu (cpu_string)    // get CPU definition
  fpu_init (env, d)        // initialize fpu state (init FCR0, basically)
  cpu_reset (env)

...and the cpu_reset call clears all interesting state that fpu_init
setup, then proceeds to reinitialize all the CP0 registers...but not
FCR0." 

I have verified this change with system emulation running the GDB test
suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated),
there were 55 progressions and no regressions.

Signed-off-by: Maciej W. Rozycki <>
Reviewed-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

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