Revision f1de1334

b/hw/mainstone.c
76 76 
    }
77 77 

  		





  78
  78
  
    
    mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0);


  		





  
  79
  
    

  		





  
  80
  
    
    /* MMC/SD host */


  		





  
  81
  
    
    pxa2xx_mmci_handlers(cpu->mmc, mst_irq[MMC_IRQ], mst_irq[MMC_IRQ]);


  		





  
  82
  
    

  		





  79
  83
  
    
    smc91c111_init(&nd_table[0], MST_ETH_PHYS, mst_irq[ETHERNET_IRQ]);


  		





  80
  84
  
    

  		





  81
  85
  
    
    arm_load_kernel(cpu->env, mainstone_ram, kernel_filename, kernel_cmdline,


  		












  

    
      b/hw/mainstone.h
    
  






  17
  17
  
    
#define MST_FLASH_1		0x04000000


  		





  18
  18
  
    

  		





  19
  19
  
    
/* IRQ definitions */


  		





  20
  
  
    
#define ETHERNET_IRQ	3


  		





  
  20
  
    
#define MMC_IRQ       0


  		





  
  21
  
    
#define USIM_IRQ      1


  		





  
  22
  
    
#define USBC_IRQ      2


  		





  
  23
  
    
#define ETHERNET_IRQ  3


  		





  
  24
  
    
#define AC97_IRQ      4


  		





  
  25
  
    
#define PEN_IRQ       5


  		





  
  26
  
    
#define MSINS_IRQ     6


  		





  
  27
  
    
#define EXBRD_IRQ     7


  		





  
  28
  
    
#define S0_CD_IRQ     9


  		





  
  29
  
    
#define S0_STSCHG_IRQ 10


  		





  
  30
  
    
#define S0_IRQ        11


  		





  
  31
  
    
#define S1_CD_IRQ     13


  		





  
  32
  
    
#define S1_STSCHG_IRQ 14


  		





  
  33
  
    
#define S1_IRQ        15


  		





  21
  34
  
    

  		





  22
  35
  
    
extern qemu_irq


  		





  23
  36
  
    
*mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq);


  		












Also available in:
  Unified diff