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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "tcg.h"
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#ifdef CONFIG_DYNGEN_OP
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/* legacy dyngen operations */
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#include "gen-op.h"
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#endif
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int gen_new_label(void);
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static inline void tcg_gen_op1(int opc, TCGv arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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}
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static inline void tcg_gen_op1i(int opc, TCGArg arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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}
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static inline void tcg_gen_op2(int opc, TCGv arg1, TCGv arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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}
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static inline void tcg_gen_op2i(int opc, TCGv arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op3(int opc, TCGv arg1, TCGv arg2, TCGv arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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}
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static inline void tcg_gen_op3i(int opc, TCGv arg1, TCGv arg2, TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_op4(int opc, TCGv arg1, TCGv arg2, TCGv arg3, 
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                               TCGv arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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}
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static inline void tcg_gen_op4i(int opc, TCGv arg1, TCGv arg2, TCGv arg3, 
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                                TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii(int opc, TCGv arg1, TCGv arg2, TCGArg arg3, 
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                                 TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op5(int opc, TCGv arg1, TCGv arg2, 
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                               TCGv arg3, TCGv arg4,
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                               TCGv arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = GET_TCGV(arg5);
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}
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static inline void tcg_gen_op5i(int opc, TCGv arg1, TCGv arg2, 
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                                TCGv arg3, TCGv arg4,
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                                TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op6(int opc, TCGv arg1, TCGv arg2, 
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                               TCGv arg3, TCGv arg4,
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                               TCGv arg5, TCGv arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = GET_TCGV(arg5);
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    *gen_opparam_ptr++ = GET_TCGV(arg6);
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}
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static inline void tcg_gen_op6ii(int opc, TCGv arg1, TCGv arg2, 
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                                 TCGv arg3, TCGv arg4,
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                                 TCGArg arg5, TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = arg5;
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    *gen_opparam_ptr++ = arg6;
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}
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static inline void gen_set_label(int n)
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{
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    tcg_gen_op1i(INDEX_op_set_label, n);
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}
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static inline void tcg_gen_br(int label)
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{
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    tcg_gen_op1i(INDEX_op_br, label);
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}
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static inline void tcg_gen_mov_i32(TCGv ret, TCGv arg)
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{
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    if (GET_TCGV(ret) != GET_TCGV(arg))
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        tcg_gen_op2(INDEX_op_mov_i32, ret, arg);
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}
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static inline void tcg_gen_movi_i32(TCGv ret, int32_t arg)
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{
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    tcg_gen_op2i(INDEX_op_movi_i32, ret, arg);
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}
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/* helper calls */
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#define TCG_HELPER_CALL_FLAGS 0
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static inline void tcg_gen_helper_0_0(void *func)
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{
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    TCGv t0;
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    t0 = tcg_const_ptr((tcg_target_long)func);
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    tcg_gen_call(&tcg_ctx, 
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                 t0, TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 0, NULL);
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    tcg_temp_free(t0);
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}
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static inline void tcg_gen_helper_0_1(void *func, TCGv arg)
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{
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    TCGv t0;
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    t0 = tcg_const_ptr((tcg_target_long)func);
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    tcg_gen_call(&tcg_ctx,
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                 t0, TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 1, &arg);
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    tcg_temp_free(t0);
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}
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static inline void tcg_gen_helper_0_2(void *func, TCGv arg1, TCGv arg2)
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{
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    TCGv args[2];
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    TCGv t0;
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    args[0] = arg1;
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    args[1] = arg2;
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    t0 = tcg_const_ptr((tcg_target_long)func);
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    tcg_gen_call(&tcg_ctx, 
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                 t0, TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 2, args);
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    tcg_temp_free(t0);
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}
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static inline void tcg_gen_helper_0_3(void *func,
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                                      TCGv arg1, TCGv arg2, TCGv arg3)
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{
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    TCGv args[3];
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    TCGv t0;
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    args[0] = arg1;
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    args[1] = arg2;
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    args[2] = arg3;
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    t0 = tcg_const_ptr((tcg_target_long)func);
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    tcg_gen_call(&tcg_ctx,
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                 t0, TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 3, args);
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    tcg_temp_free(t0);
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}
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static inline void tcg_gen_helper_0_4(void *func, TCGv arg1, TCGv arg2,
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                                      TCGv arg3, TCGv arg4)
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{
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    TCGv args[4];
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    TCGv t0;
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    args[0] = arg1;
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    args[1] = arg2;
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    args[2] = arg3;
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    args[3] = arg4;
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    t0 = tcg_const_ptr((tcg_target_long)func);
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    tcg_gen_call(&tcg_ctx,
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                 t0, TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 4, args);
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    tcg_temp_free(t0);
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}
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static inline void tcg_gen_helper_1_0(void *func, TCGv ret)
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{
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    TCGv t0;
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    t0 = tcg_const_ptr((tcg_target_long)func);
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    tcg_gen_call(&tcg_ctx,
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                 t0, TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 0, NULL);
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    tcg_temp_free(t0);
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}
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static inline void tcg_gen_helper_1_1(void *func, TCGv ret, TCGv arg1)
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{
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    TCGv t0;
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    t0 = tcg_const_ptr((tcg_target_long)func);
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    tcg_gen_call(&tcg_ctx,
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                 t0, TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 1, &arg1);
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    tcg_temp_free(t0);
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}
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static inline void tcg_gen_helper_1_2(void *func, TCGv ret, 
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                                      TCGv arg1, TCGv arg2)
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{
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    TCGv args[2];
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    TCGv t0;
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    args[0] = arg1;
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    args[1] = arg2;
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    t0 = tcg_const_ptr((tcg_target_long)func);
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    tcg_gen_call(&tcg_ctx, 
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                 t0, TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 2, args);
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    tcg_temp_free(t0);
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}
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static inline void tcg_gen_helper_1_3(void *func, TCGv ret,
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                                      TCGv arg1, TCGv arg2, TCGv arg3)
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{
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    TCGv args[3];
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    TCGv t0;
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    args[0] = arg1;
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    args[1] = arg2;
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    args[2] = arg3;
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    t0 = tcg_const_ptr((tcg_target_long)func);
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    tcg_gen_call(&tcg_ctx,
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                 t0, TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 3, args);
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    tcg_temp_free(t0);
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}
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static inline void tcg_gen_helper_1_4(void *func, TCGv ret,
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                                      TCGv arg1, TCGv arg2, TCGv arg3,
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                                      TCGv arg4)
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{
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    TCGv args[4];
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    TCGv t0;
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    args[0] = arg1;
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    args[1] = arg2;
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    args[2] = arg3;
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    args[3] = arg4;
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    t0 = tcg_const_ptr((tcg_target_long)func);
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    tcg_gen_call(&tcg_ctx,
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                 t0, TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 4, args);
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    tcg_temp_free(t0);
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}
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/* 32 bit ops */
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static inline void tcg_gen_ld8u_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld8u_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld8s_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld8s_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld16u_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld16u_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld16s_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld16s_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_st8_i32(TCGv arg1, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_st8_i32, arg1, arg2, offset);
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}
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static inline void tcg_gen_st16_i32(TCGv arg1, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_st16_i32, arg1, arg2, offset);
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}
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static inline void tcg_gen_st_i32(TCGv arg1, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_st_i32, arg1, arg2, offset);
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}
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static inline void tcg_gen_add_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_add_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_addi_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    /* some cases can be optimized here */
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    if (arg2 == 0) {
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        tcg_gen_mov_i32(ret, arg1);
368 7089442c blueswir1
    } else {
369 e8996ee0 bellard
        TCGv t0 = tcg_const_i32(arg2);
370 e8996ee0 bellard
        tcg_gen_add_i32(ret, arg1, t0);
371 e8996ee0 bellard
        tcg_temp_free(t0);
372 7089442c blueswir1
    }
373 c896fe29 bellard
}
374 c896fe29 bellard
375 ac56dd48 pbrook
static inline void tcg_gen_sub_i32(TCGv ret, TCGv arg1, TCGv arg2)
376 c896fe29 bellard
{
377 c896fe29 bellard
    tcg_gen_op3(INDEX_op_sub_i32, ret, arg1, arg2);
378 c896fe29 bellard
}
379 c896fe29 bellard
380 ac56dd48 pbrook
static inline void tcg_gen_subi_i32(TCGv ret, TCGv arg1, int32_t arg2)
381 c896fe29 bellard
{
382 7089442c blueswir1
    /* some cases can be optimized here */
383 7089442c blueswir1
    if (arg2 == 0) {
384 7089442c blueswir1
        tcg_gen_mov_i32(ret, arg1);
385 7089442c blueswir1
    } else {
386 e8996ee0 bellard
        TCGv t0 = tcg_const_i32(arg2);
387 e8996ee0 bellard
        tcg_gen_sub_i32(ret, arg1, t0);
388 e8996ee0 bellard
        tcg_temp_free(t0);
389 7089442c blueswir1
    }
390 c896fe29 bellard
}
391 c896fe29 bellard
392 ac56dd48 pbrook
static inline void tcg_gen_and_i32(TCGv ret, TCGv arg1, TCGv arg2)
393 c896fe29 bellard
{
394 c896fe29 bellard
    tcg_gen_op3(INDEX_op_and_i32, ret, arg1, arg2);
395 c896fe29 bellard
}
396 c896fe29 bellard
397 ac56dd48 pbrook
static inline void tcg_gen_andi_i32(TCGv ret, TCGv arg1, int32_t arg2)
398 c896fe29 bellard
{
399 c896fe29 bellard
    /* some cases can be optimized here */
400 c896fe29 bellard
    if (arg2 == 0) {
401 c896fe29 bellard
        tcg_gen_movi_i32(ret, 0);
402 c896fe29 bellard
    } else if (arg2 == 0xffffffff) {
403 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
404 c896fe29 bellard
    } else {
405 e8996ee0 bellard
        TCGv t0 = tcg_const_i32(arg2);
406 e8996ee0 bellard
        tcg_gen_and_i32(ret, arg1, t0);
407 e8996ee0 bellard
        tcg_temp_free(t0);
408 c896fe29 bellard
    }
409 c896fe29 bellard
}
410 c896fe29 bellard
411 ac56dd48 pbrook
static inline void tcg_gen_or_i32(TCGv ret, TCGv arg1, TCGv arg2)
412 c896fe29 bellard
{
413 c896fe29 bellard
    tcg_gen_op3(INDEX_op_or_i32, ret, arg1, arg2);
414 c896fe29 bellard
}
415 c896fe29 bellard
416 ac56dd48 pbrook
static inline void tcg_gen_ori_i32(TCGv ret, TCGv arg1, int32_t arg2)
417 c896fe29 bellard
{
418 c896fe29 bellard
    /* some cases can be optimized here */
419 c896fe29 bellard
    if (arg2 == 0xffffffff) {
420 7089442c blueswir1
        tcg_gen_movi_i32(ret, 0xffffffff);
421 c896fe29 bellard
    } else if (arg2 == 0) {
422 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
423 c896fe29 bellard
    } else {
424 e8996ee0 bellard
        TCGv t0 = tcg_const_i32(arg2);
425 e8996ee0 bellard
        tcg_gen_or_i32(ret, arg1, t0);
426 e8996ee0 bellard
        tcg_temp_free(t0);
427 c896fe29 bellard
    }
428 c896fe29 bellard
}
429 c896fe29 bellard
430 ac56dd48 pbrook
static inline void tcg_gen_xor_i32(TCGv ret, TCGv arg1, TCGv arg2)
431 c896fe29 bellard
{
432 c896fe29 bellard
    tcg_gen_op3(INDEX_op_xor_i32, ret, arg1, arg2);
433 c896fe29 bellard
}
434 c896fe29 bellard
435 ac56dd48 pbrook
static inline void tcg_gen_xori_i32(TCGv ret, TCGv arg1, int32_t arg2)
436 c896fe29 bellard
{
437 c896fe29 bellard
    /* some cases can be optimized here */
438 c896fe29 bellard
    if (arg2 == 0) {
439 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
440 c896fe29 bellard
    } else {
441 e8996ee0 bellard
        TCGv t0 = tcg_const_i32(arg2);
442 e8996ee0 bellard
        tcg_gen_xor_i32(ret, arg1, t0);
443 e8996ee0 bellard
        tcg_temp_free(t0);
444 c896fe29 bellard
    }
445 c896fe29 bellard
}
446 c896fe29 bellard
447 ac56dd48 pbrook
static inline void tcg_gen_shl_i32(TCGv ret, TCGv arg1, TCGv arg2)
448 c896fe29 bellard
{
449 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shl_i32, ret, arg1, arg2);
450 c896fe29 bellard
}
451 c896fe29 bellard
452 ac56dd48 pbrook
static inline void tcg_gen_shli_i32(TCGv ret, TCGv arg1, int32_t arg2)
453 c896fe29 bellard
{
454 34151a20 bellard
    if (arg2 == 0) {
455 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
456 34151a20 bellard
    } else {
457 e8996ee0 bellard
        TCGv t0 = tcg_const_i32(arg2);
458 e8996ee0 bellard
        tcg_gen_shl_i32(ret, arg1, t0);
459 e8996ee0 bellard
        tcg_temp_free(t0);
460 34151a20 bellard
    }
461 c896fe29 bellard
}
462 c896fe29 bellard
463 ac56dd48 pbrook
static inline void tcg_gen_shr_i32(TCGv ret, TCGv arg1, TCGv arg2)
464 c896fe29 bellard
{
465 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shr_i32, ret, arg1, arg2);
466 c896fe29 bellard
}
467 c896fe29 bellard
468 ac56dd48 pbrook
static inline void tcg_gen_shri_i32(TCGv ret, TCGv arg1, int32_t arg2)
469 c896fe29 bellard
{
470 34151a20 bellard
    if (arg2 == 0) {
471 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
472 34151a20 bellard
    } else {
473 e8996ee0 bellard
        TCGv t0 = tcg_const_i32(arg2);
474 e8996ee0 bellard
        tcg_gen_shr_i32(ret, arg1, t0);
475 e8996ee0 bellard
        tcg_temp_free(t0);
476 34151a20 bellard
    }
477 c896fe29 bellard
}
478 c896fe29 bellard
479 ac56dd48 pbrook
static inline void tcg_gen_sar_i32(TCGv ret, TCGv arg1, TCGv arg2)
480 c896fe29 bellard
{
481 c896fe29 bellard
    tcg_gen_op3(INDEX_op_sar_i32, ret, arg1, arg2);
482 c896fe29 bellard
}
483 c896fe29 bellard
484 ac56dd48 pbrook
static inline void tcg_gen_sari_i32(TCGv ret, TCGv arg1, int32_t arg2)
485 c896fe29 bellard
{
486 34151a20 bellard
    if (arg2 == 0) {
487 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
488 34151a20 bellard
    } else {
489 e8996ee0 bellard
        TCGv t0 = tcg_const_i32(arg2);
490 e8996ee0 bellard
        tcg_gen_sar_i32(ret, arg1, t0);
491 e8996ee0 bellard
        tcg_temp_free(t0);
492 34151a20 bellard
    }
493 c896fe29 bellard
}
494 c896fe29 bellard
495 ac56dd48 pbrook
static inline void tcg_gen_brcond_i32(int cond, TCGv arg1, TCGv arg2, 
496 c896fe29 bellard
                                      int label_index)
497 c896fe29 bellard
{
498 ac56dd48 pbrook
    tcg_gen_op4ii(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
499 c896fe29 bellard
}
500 c896fe29 bellard
501 cb63669a pbrook
static inline void tcg_gen_brcondi_i32(int cond, TCGv arg1, int32_t arg2, 
502 cb63669a pbrook
                                       int label_index)
503 cb63669a pbrook
{
504 cb63669a pbrook
    TCGv t0 = tcg_const_i32(arg2);
505 cb63669a pbrook
    tcg_gen_brcond_i32(cond, arg1, t0, label_index);
506 cb63669a pbrook
    tcg_temp_free(t0);
507 cb63669a pbrook
}
508 cb63669a pbrook
509 ac56dd48 pbrook
static inline void tcg_gen_mul_i32(TCGv ret, TCGv arg1, TCGv arg2)
510 c896fe29 bellard
{
511 c896fe29 bellard
    tcg_gen_op3(INDEX_op_mul_i32, ret, arg1, arg2);
512 c896fe29 bellard
}
513 c896fe29 bellard
514 f730fd27 ths
static inline void tcg_gen_muli_i32(TCGv ret, TCGv arg1, int32_t arg2)
515 f730fd27 ths
{
516 e8996ee0 bellard
    TCGv t0 = tcg_const_i32(arg2);
517 e8996ee0 bellard
    tcg_gen_mul_i32(ret, arg1, t0);
518 e8996ee0 bellard
    tcg_temp_free(t0);
519 f730fd27 ths
}
520 f730fd27 ths
521 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i32
522 ac56dd48 pbrook
static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2)
523 c896fe29 bellard
{
524 c896fe29 bellard
    tcg_gen_op3(INDEX_op_div_i32, ret, arg1, arg2);
525 c896fe29 bellard
}
526 c896fe29 bellard
527 ac56dd48 pbrook
static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2)
528 c896fe29 bellard
{
529 c896fe29 bellard
    tcg_gen_op3(INDEX_op_rem_i32, ret, arg1, arg2);
530 c896fe29 bellard
}
531 c896fe29 bellard
532 ac56dd48 pbrook
static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2)
533 c896fe29 bellard
{
534 c896fe29 bellard
    tcg_gen_op3(INDEX_op_divu_i32, ret, arg1, arg2);
535 c896fe29 bellard
}
536 c896fe29 bellard
537 ac56dd48 pbrook
static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2)
538 c896fe29 bellard
{
539 c896fe29 bellard
    tcg_gen_op3(INDEX_op_remu_i32, ret, arg1, arg2);
540 c896fe29 bellard
}
541 c896fe29 bellard
#else
542 ac56dd48 pbrook
static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2)
543 c896fe29 bellard
{
544 ac56dd48 pbrook
    TCGv t0;
545 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
546 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
547 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
548 e8996ee0 bellard
    tcg_temp_free(t0);
549 c896fe29 bellard
}
550 c896fe29 bellard
551 ac56dd48 pbrook
static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2)
552 c896fe29 bellard
{
553 ac56dd48 pbrook
    TCGv t0;
554 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
555 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
556 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
557 e8996ee0 bellard
    tcg_temp_free(t0);
558 c896fe29 bellard
}
559 c896fe29 bellard
560 ac56dd48 pbrook
static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2)
561 c896fe29 bellard
{
562 ac56dd48 pbrook
    TCGv t0;
563 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
564 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
565 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
566 e8996ee0 bellard
    tcg_temp_free(t0);
567 c896fe29 bellard
}
568 c896fe29 bellard
569 ac56dd48 pbrook
static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2)
570 c896fe29 bellard
{
571 ac56dd48 pbrook
    TCGv t0;
572 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
573 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
574 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
575 e8996ee0 bellard
    tcg_temp_free(t0);
576 c896fe29 bellard
}
577 c896fe29 bellard
#endif
578 c896fe29 bellard
579 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
580 c896fe29 bellard
581 ac56dd48 pbrook
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg)
582 c896fe29 bellard
{
583 98156423 pbrook
    if (GET_TCGV(ret) != GET_TCGV(arg)) {
584 4d07272d blueswir1
        tcg_gen_mov_i32(ret, arg);
585 4d07272d blueswir1
        tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
586 4d07272d blueswir1
    }
587 c896fe29 bellard
}
588 c896fe29 bellard
589 ac56dd48 pbrook
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg)
590 c896fe29 bellard
{
591 c896fe29 bellard
    tcg_gen_movi_i32(ret, arg);
592 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
593 c896fe29 bellard
}
594 c896fe29 bellard
595 ac56dd48 pbrook
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
596 c896fe29 bellard
{
597 c896fe29 bellard
    tcg_gen_ld8u_i32(ret, arg2, offset);
598 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
599 c896fe29 bellard
}
600 c896fe29 bellard
601 ac56dd48 pbrook
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
602 c896fe29 bellard
{
603 c896fe29 bellard
    tcg_gen_ld8s_i32(ret, arg2, offset);
604 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
605 c896fe29 bellard
}
606 c896fe29 bellard
607 ac56dd48 pbrook
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
608 c896fe29 bellard
{
609 c896fe29 bellard
    tcg_gen_ld16u_i32(ret, arg2, offset);
610 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
611 c896fe29 bellard
}
612 c896fe29 bellard
613 ac56dd48 pbrook
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
614 c896fe29 bellard
{
615 c896fe29 bellard
    tcg_gen_ld16s_i32(ret, arg2, offset);
616 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
617 c896fe29 bellard
}
618 c896fe29 bellard
619 ac56dd48 pbrook
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
620 c896fe29 bellard
{
621 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset);
622 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
623 c896fe29 bellard
}
624 c896fe29 bellard
625 ac56dd48 pbrook
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
626 c896fe29 bellard
{
627 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset);
628 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
629 c896fe29 bellard
}
630 c896fe29 bellard
631 ac56dd48 pbrook
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
632 c896fe29 bellard
{
633 c896fe29 bellard
    /* since arg2 and ret have different types, they cannot be the
634 c896fe29 bellard
       same temporary */
635 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
636 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
637 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset + 4);
638 c896fe29 bellard
#else
639 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset);
640 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
641 c896fe29 bellard
#endif
642 c896fe29 bellard
}
643 c896fe29 bellard
644 ac56dd48 pbrook
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
645 c896fe29 bellard
{
646 c896fe29 bellard
    tcg_gen_st8_i32(arg1, arg2, offset);
647 c896fe29 bellard
}
648 c896fe29 bellard
649 ac56dd48 pbrook
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
650 c896fe29 bellard
{
651 c896fe29 bellard
    tcg_gen_st16_i32(arg1, arg2, offset);
652 c896fe29 bellard
}
653 c896fe29 bellard
654 ac56dd48 pbrook
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
655 c896fe29 bellard
{
656 c896fe29 bellard
    tcg_gen_st_i32(arg1, arg2, offset);
657 c896fe29 bellard
}
658 c896fe29 bellard
659 ac56dd48 pbrook
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
660 c896fe29 bellard
{
661 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
662 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
663 c896fe29 bellard
    tcg_gen_st_i32(arg1, arg2, offset + 4);
664 c896fe29 bellard
#else
665 c896fe29 bellard
    tcg_gen_st_i32(arg1, arg2, offset);
666 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
667 c896fe29 bellard
#endif
668 c896fe29 bellard
}
669 c896fe29 bellard
670 ac56dd48 pbrook
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2)
671 c896fe29 bellard
{
672 ac56dd48 pbrook
    tcg_gen_op6(INDEX_op_add2_i32, ret, TCGV_HIGH(ret), 
673 ac56dd48 pbrook
                arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2));
674 c896fe29 bellard
}
675 c896fe29 bellard
676 ac56dd48 pbrook
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2)
677 c896fe29 bellard
{
678 e8996ee0 bellard
    TCGv t0 = tcg_const_i64(arg2);
679 e8996ee0 bellard
    tcg_gen_add_i64(ret, arg1, t0);
680 e8996ee0 bellard
    tcg_temp_free(t0);
681 c896fe29 bellard
}
682 c896fe29 bellard
683 ac56dd48 pbrook
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2)
684 c896fe29 bellard
{
685 ac56dd48 pbrook
    tcg_gen_op6(INDEX_op_sub2_i32, ret, TCGV_HIGH(ret), 
686 ac56dd48 pbrook
                arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2));
687 c896fe29 bellard
}
688 c896fe29 bellard
689 ac56dd48 pbrook
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2)
690 c896fe29 bellard
{
691 e8996ee0 bellard
    TCGv t0 = tcg_const_i64(arg2);
692 e8996ee0 bellard
    tcg_gen_sub_i64(ret, arg1, t0);
693 e8996ee0 bellard
    tcg_temp_free(t0);
694 c896fe29 bellard
}
695 c896fe29 bellard
696 ac56dd48 pbrook
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2)
697 c896fe29 bellard
{
698 c896fe29 bellard
    tcg_gen_and_i32(ret, arg1, arg2);
699 ac56dd48 pbrook
    tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
700 c896fe29 bellard
}
701 c896fe29 bellard
702 ac56dd48 pbrook
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2)
703 c896fe29 bellard
{
704 c896fe29 bellard
    tcg_gen_andi_i32(ret, arg1, arg2);
705 ac56dd48 pbrook
    tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
706 c896fe29 bellard
}
707 c896fe29 bellard
708 ac56dd48 pbrook
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2)
709 c896fe29 bellard
{
710 c896fe29 bellard
    tcg_gen_or_i32(ret, arg1, arg2);
711 ac56dd48 pbrook
    tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
712 c896fe29 bellard
}
713 c896fe29 bellard
714 ac56dd48 pbrook
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2)
715 c896fe29 bellard
{
716 c896fe29 bellard
    tcg_gen_ori_i32(ret, arg1, arg2);
717 ac56dd48 pbrook
    tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
718 c896fe29 bellard
}
719 c896fe29 bellard
720 ac56dd48 pbrook
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2)
721 c896fe29 bellard
{
722 c896fe29 bellard
    tcg_gen_xor_i32(ret, arg1, arg2);
723 ac56dd48 pbrook
    tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
724 c896fe29 bellard
}
725 c896fe29 bellard
726 ac56dd48 pbrook
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2)
727 c896fe29 bellard
{
728 c896fe29 bellard
    tcg_gen_xori_i32(ret, arg1, arg2);
729 ac56dd48 pbrook
    tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
730 c896fe29 bellard
}
731 c896fe29 bellard
732 c896fe29 bellard
/* XXX: use generic code when basic block handling is OK or CPU
733 c896fe29 bellard
   specific code (x86) */
734 ac56dd48 pbrook
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2)
735 c896fe29 bellard
{
736 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_shl_i64, ret, arg1, arg2);
737 c896fe29 bellard
}
738 c896fe29 bellard
739 ac56dd48 pbrook
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2)
740 c896fe29 bellard
{
741 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
742 c896fe29 bellard
}
743 c896fe29 bellard
744 ac56dd48 pbrook
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2)
745 c896fe29 bellard
{
746 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_shr_i64, ret, arg1, arg2);
747 c896fe29 bellard
}
748 c896fe29 bellard
749 ac56dd48 pbrook
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2)
750 c896fe29 bellard
{
751 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
752 c896fe29 bellard
}
753 c896fe29 bellard
754 ac56dd48 pbrook
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2)
755 c896fe29 bellard
{
756 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_sar_i64, ret, arg1, arg2);
757 c896fe29 bellard
}
758 c896fe29 bellard
759 ac56dd48 pbrook
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2)
760 c896fe29 bellard
{
761 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
762 c896fe29 bellard
}
763 c896fe29 bellard
764 ac56dd48 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, 
765 c896fe29 bellard
                                      int label_index)
766 c896fe29 bellard
{
767 ac56dd48 pbrook
    tcg_gen_op6ii(INDEX_op_brcond2_i32, 
768 ac56dd48 pbrook
                  arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2),
769 ac56dd48 pbrook
                  cond, label_index);
770 c896fe29 bellard
}
771 c896fe29 bellard
772 ac56dd48 pbrook
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2)
773 c896fe29 bellard
{
774 ac56dd48 pbrook
    TCGv t0, t1;
775 c896fe29 bellard
    
776 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
777 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
778 c896fe29 bellard
779 ac56dd48 pbrook
    tcg_gen_op4(INDEX_op_mulu2_i32, t0, TCGV_HIGH(t0), arg1, arg2);
780 c896fe29 bellard
    
781 ac56dd48 pbrook
    tcg_gen_mul_i32(t1, arg1, TCGV_HIGH(arg2));
782 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
783 ac56dd48 pbrook
    tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), arg2);
784 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
785 c896fe29 bellard
    
786 c896fe29 bellard
    tcg_gen_mov_i64(ret, t0);
787 e8996ee0 bellard
    tcg_temp_free(t0);
788 e8996ee0 bellard
    tcg_temp_free(t1);
789 c896fe29 bellard
}
790 c896fe29 bellard
791 f730fd27 ths
static inline void tcg_gen_muli_i64(TCGv ret, TCGv arg1, int64_t arg2)
792 f730fd27 ths
{
793 e8996ee0 bellard
    TCGv t0 = tcg_const_i64(arg2);
794 e8996ee0 bellard
    tcg_gen_mul_i64(ret, arg1, t0);
795 e8996ee0 bellard
    tcg_temp_free(t0);
796 f730fd27 ths
}
797 f730fd27 ths
798 ac56dd48 pbrook
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2)
799 c896fe29 bellard
{
800 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_div_i64, ret, arg1, arg2);
801 c896fe29 bellard
}
802 c896fe29 bellard
803 ac56dd48 pbrook
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2)
804 c896fe29 bellard
{
805 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_rem_i64, ret, arg1, arg2);
806 c896fe29 bellard
}
807 c896fe29 bellard
808 ac56dd48 pbrook
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2)
809 c896fe29 bellard
{
810 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_divu_i64, ret, arg1, arg2);
811 c896fe29 bellard
}
812 c896fe29 bellard
813 ac56dd48 pbrook
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2)
814 c896fe29 bellard
{
815 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_remu_i64, ret, arg1, arg2);
816 c896fe29 bellard
}
817 c896fe29 bellard
818 c896fe29 bellard
#else
819 c896fe29 bellard
820 ac56dd48 pbrook
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg)
821 c896fe29 bellard
{
822 98156423 pbrook
    if (GET_TCGV(ret) != GET_TCGV(arg))
823 4d07272d blueswir1
        tcg_gen_op2(INDEX_op_mov_i64, ret, arg);
824 c896fe29 bellard
}
825 c896fe29 bellard
826 ac56dd48 pbrook
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg)
827 c896fe29 bellard
{
828 ac56dd48 pbrook
    tcg_gen_op2i(INDEX_op_movi_i64, ret, arg);
829 c896fe29 bellard
}
830 c896fe29 bellard
831 ac56dd48 pbrook
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2,
832 ac56dd48 pbrook
                                    tcg_target_long offset)
833 c896fe29 bellard
{
834 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld8u_i64, ret, arg2, offset);
835 c896fe29 bellard
}
836 c896fe29 bellard
837 ac56dd48 pbrook
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2,
838 ac56dd48 pbrook
                                    tcg_target_long offset)
839 c896fe29 bellard
{
840 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld8s_i64, ret, arg2, offset);
841 c896fe29 bellard
}
842 c896fe29 bellard
843 ac56dd48 pbrook
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2,
844 ac56dd48 pbrook
                                     tcg_target_long offset)
845 c896fe29 bellard
{
846 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld16u_i64, ret, arg2, offset);
847 c896fe29 bellard
}
848 c896fe29 bellard
849 ac56dd48 pbrook
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2,
850 ac56dd48 pbrook
                                     tcg_target_long offset)
851 c896fe29 bellard
{
852 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld16s_i64, ret, arg2, offset);
853 c896fe29 bellard
}
854 c896fe29 bellard
855 ac56dd48 pbrook
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2,
856 ac56dd48 pbrook
                                     tcg_target_long offset)
857 c896fe29 bellard
{
858 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld32u_i64, ret, arg2, offset);
859 c896fe29 bellard
}
860 c896fe29 bellard
861 ac56dd48 pbrook
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2,
862 ac56dd48 pbrook
                                     tcg_target_long offset)
863 c896fe29 bellard
{
864 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld32s_i64, ret, arg2, offset);
865 c896fe29 bellard
}
866 c896fe29 bellard
867 ac56dd48 pbrook
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
868 c896fe29 bellard
{
869 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld_i64, ret, arg2, offset);
870 c896fe29 bellard
}
871 c896fe29 bellard
872 ac56dd48 pbrook
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2,
873 ac56dd48 pbrook
                                   tcg_target_long offset)
874 c896fe29 bellard
{
875 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st8_i64, arg1, arg2, offset);
876 c896fe29 bellard
}
877 c896fe29 bellard
878 ac56dd48 pbrook
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2,
879 ac56dd48 pbrook
                                    tcg_target_long offset)
880 c896fe29 bellard
{
881 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st16_i64, arg1, arg2, offset);
882 c896fe29 bellard
}
883 c896fe29 bellard
884 ac56dd48 pbrook
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2,
885 ac56dd48 pbrook
                                    tcg_target_long offset)
886 c896fe29 bellard
{
887 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st32_i64, arg1, arg2, offset);
888 c896fe29 bellard
}
889 c896fe29 bellard
890 ac56dd48 pbrook
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
891 c896fe29 bellard
{
892 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st_i64, arg1, arg2, offset);
893 c896fe29 bellard
}
894 c896fe29 bellard
895 ac56dd48 pbrook
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2)
896 c896fe29 bellard
{
897 c896fe29 bellard
    tcg_gen_op3(INDEX_op_add_i64, ret, arg1, arg2);
898 c896fe29 bellard
}
899 c896fe29 bellard
900 ac56dd48 pbrook
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2)
901 c896fe29 bellard
{
902 e8996ee0 bellard
    TCGv t0 = tcg_const_i64(arg2);
903 e8996ee0 bellard
    tcg_gen_add_i64(ret, arg1, t0);
904 e8996ee0 bellard
    tcg_temp_free(t0);
905 c896fe29 bellard
}
906 c896fe29 bellard
907 ac56dd48 pbrook
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2)
908 c896fe29 bellard
{
909 c896fe29 bellard
    tcg_gen_op3(INDEX_op_sub_i64, ret, arg1, arg2);
910 c896fe29 bellard
}
911 c896fe29 bellard
912 ac56dd48 pbrook
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2)
913 c896fe29 bellard
{
914 e8996ee0 bellard
    TCGv t0 = tcg_const_i64(arg2);
915 e8996ee0 bellard
    tcg_gen_sub_i64(ret, arg1, t0);
916 e8996ee0 bellard
    tcg_temp_free(t0);
917 c896fe29 bellard
}
918 c896fe29 bellard
919 ac56dd48 pbrook
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2)
920 c896fe29 bellard
{
921 c896fe29 bellard
    tcg_gen_op3(INDEX_op_and_i64, ret, arg1, arg2);
922 c896fe29 bellard
}
923 c896fe29 bellard
924 ac56dd48 pbrook
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2)
925 c896fe29 bellard
{
926 e8996ee0 bellard
    TCGv t0 = tcg_const_i64(arg2);
927 e8996ee0 bellard
    tcg_gen_and_i64(ret, arg1, t0);
928 e8996ee0 bellard
    tcg_temp_free(t0);
929 c896fe29 bellard
}
930 c896fe29 bellard
931 ac56dd48 pbrook
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2)
932 c896fe29 bellard
{
933 c896fe29 bellard
    tcg_gen_op3(INDEX_op_or_i64, ret, arg1, arg2);
934 c896fe29 bellard
}
935 c896fe29 bellard
936 ac56dd48 pbrook
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2)
937 c896fe29 bellard
{
938 e8996ee0 bellard
    TCGv t0 = tcg_const_i64(arg2);
939 e8996ee0 bellard
    tcg_gen_or_i64(ret, arg1, t0);
940 e8996ee0 bellard
    tcg_temp_free(t0);
941 c896fe29 bellard
}
942 c896fe29 bellard
943 ac56dd48 pbrook
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2)
944 c896fe29 bellard
{
945 c896fe29 bellard
    tcg_gen_op3(INDEX_op_xor_i64, ret, arg1, arg2);
946 c896fe29 bellard
}
947 c896fe29 bellard
948 ac56dd48 pbrook
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2)
949 c896fe29 bellard
{
950 e8996ee0 bellard
    TCGv t0 = tcg_const_i64(arg2);
951 e8996ee0 bellard
    tcg_gen_xor_i64(ret, arg1, t0);
952 e8996ee0 bellard
    tcg_temp_free(t0);
953 c896fe29 bellard
}
954 c896fe29 bellard
955 ac56dd48 pbrook
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2)
956 c896fe29 bellard
{
957 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shl_i64, ret, arg1, arg2);
958 c896fe29 bellard
}
959 c896fe29 bellard
960 ac56dd48 pbrook
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2)
961 c896fe29 bellard
{
962 34151a20 bellard
    if (arg2 == 0) {
963 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
964 34151a20 bellard
    } else {
965 e8996ee0 bellard
        TCGv t0 = tcg_const_i64(arg2);
966 e8996ee0 bellard
        tcg_gen_shl_i64(ret, arg1, t0);
967 e8996ee0 bellard
        tcg_temp_free(t0);
968 34151a20 bellard
    }
969 c896fe29 bellard
}
970 c896fe29 bellard
971 ac56dd48 pbrook
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2)
972 c896fe29 bellard
{
973 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shr_i64, ret, arg1, arg2);
974 c896fe29 bellard
}
975 c896fe29 bellard
976 ac56dd48 pbrook
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2)
977 c896fe29 bellard
{
978 34151a20 bellard
    if (arg2 == 0) {
979 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
980 34151a20 bellard
    } else {
981 e8996ee0 bellard
        TCGv t0 = tcg_const_i64(arg2);
982 e8996ee0 bellard
        tcg_gen_shr_i64(ret, arg1, t0);
983 e8996ee0 bellard
        tcg_temp_free(t0);
984 34151a20 bellard
    }
985 c896fe29 bellard
}
986 c896fe29 bellard
987 ac56dd48 pbrook
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2)
988 c896fe29 bellard
{
989 c896fe29 bellard
    tcg_gen_op3(INDEX_op_sar_i64, ret, arg1, arg2);
990 c896fe29 bellard
}
991 c896fe29 bellard
992 ac56dd48 pbrook
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2)
993 c896fe29 bellard
{
994 34151a20 bellard
    if (arg2 == 0) {
995 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
996 34151a20 bellard
    } else {
997 e8996ee0 bellard
        TCGv t0 = tcg_const_i64(arg2);
998 e8996ee0 bellard
        tcg_gen_sar_i64(ret, arg1, t0);
999 e8996ee0 bellard
        tcg_temp_free(t0);
1000 34151a20 bellard
    }
1001 c896fe29 bellard
}
1002 c896fe29 bellard
1003 ac56dd48 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, 
1004 c896fe29 bellard
                                      int label_index)
1005 c896fe29 bellard
{
1006 ac56dd48 pbrook
    tcg_gen_op4ii(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1007 c896fe29 bellard
}
1008 c896fe29 bellard
1009 ac56dd48 pbrook
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2)
1010 c896fe29 bellard
{
1011 c896fe29 bellard
    tcg_gen_op3(INDEX_op_mul_i64, ret, arg1, arg2);
1012 c896fe29 bellard
}
1013 c896fe29 bellard
1014 f730fd27 ths
static inline void tcg_gen_muli_i64(TCGv ret, TCGv arg1, int64_t arg2)
1015 f730fd27 ths
{
1016 e8996ee0 bellard
    TCGv t0 = tcg_const_i64(arg2);
1017 e8996ee0 bellard
    tcg_gen_mul_i64(ret, arg1, t0);
1018 e8996ee0 bellard
    tcg_temp_free(t0);
1019 f730fd27 ths
}
1020 f730fd27 ths
1021 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i64
1022 ac56dd48 pbrook
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2)
1023 c896fe29 bellard
{
1024 c896fe29 bellard
    tcg_gen_op3(INDEX_op_div_i64, ret, arg1, arg2);
1025 c896fe29 bellard
}
1026 c896fe29 bellard
1027 ac56dd48 pbrook
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2)
1028 c896fe29 bellard
{
1029 c896fe29 bellard
    tcg_gen_op3(INDEX_op_rem_i64, ret, arg1, arg2);
1030 c896fe29 bellard
}
1031 c896fe29 bellard
1032 ac56dd48 pbrook
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2)
1033 c896fe29 bellard
{
1034 c896fe29 bellard
    tcg_gen_op3(INDEX_op_divu_i64, ret, arg1, arg2);
1035 c896fe29 bellard
}
1036 c896fe29 bellard
1037 ac56dd48 pbrook
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2)
1038 c896fe29 bellard
{
1039 c896fe29 bellard
    tcg_gen_op3(INDEX_op_remu_i64, ret, arg1, arg2);
1040 c896fe29 bellard
}
1041 c896fe29 bellard
#else
1042 ac56dd48 pbrook
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2)
1043 c896fe29 bellard
{
1044 ac56dd48 pbrook
    TCGv t0;
1045 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
1046 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
1047 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1048 e8996ee0 bellard
    tcg_temp_free(t0);
1049 c896fe29 bellard
}
1050 c896fe29 bellard
1051 ac56dd48 pbrook
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2)
1052 c896fe29 bellard
{
1053 ac56dd48 pbrook
    TCGv t0;
1054 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
1055 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
1056 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1057 e8996ee0 bellard
    tcg_temp_free(t0);
1058 c896fe29 bellard
}
1059 c896fe29 bellard
1060 ac56dd48 pbrook
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2)
1061 c896fe29 bellard
{
1062 ac56dd48 pbrook
    TCGv t0;
1063 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
1064 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
1065 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1066 e8996ee0 bellard
    tcg_temp_free(t0);
1067 c896fe29 bellard
}
1068 c896fe29 bellard
1069 ac56dd48 pbrook
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2)
1070 c896fe29 bellard
{
1071 ac56dd48 pbrook
    TCGv t0;
1072 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
1073 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
1074 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1075 e8996ee0 bellard
    tcg_temp_free(t0);
1076 c896fe29 bellard
}
1077 c896fe29 bellard
#endif
1078 c896fe29 bellard
1079 c896fe29 bellard
#endif
1080 c896fe29 bellard
1081 cb63669a pbrook
static inline void tcg_gen_brcondi_i64(int cond, TCGv arg1, int64_t arg2, 
1082 cb63669a pbrook
                                       int label_index)
1083 cb63669a pbrook
{
1084 cb63669a pbrook
    TCGv t0 = tcg_const_i64(arg2);
1085 cb63669a pbrook
    tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1086 cb63669a pbrook
    tcg_temp_free(t0);
1087 cb63669a pbrook
}
1088 cb63669a pbrook
1089 c896fe29 bellard
/***************************************/
1090 c896fe29 bellard
/* optional operations */
1091 c896fe29 bellard
1092 ac56dd48 pbrook
static inline void tcg_gen_ext8s_i32(TCGv ret, TCGv arg)
1093 c896fe29 bellard
{
1094 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i32
1095 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext8s_i32, ret, arg);
1096 c896fe29 bellard
#else
1097 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 24);
1098 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 24);
1099 c896fe29 bellard
#endif
1100 c896fe29 bellard
}
1101 c896fe29 bellard
1102 ac56dd48 pbrook
static inline void tcg_gen_ext16s_i32(TCGv ret, TCGv arg)
1103 c896fe29 bellard
{
1104 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i32
1105 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext16s_i32, ret, arg);
1106 c896fe29 bellard
#else
1107 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 16);
1108 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 16);
1109 c896fe29 bellard
#endif
1110 c896fe29 bellard
}
1111 c896fe29 bellard
1112 86831435 pbrook
/* These are currently just for convenience.
1113 86831435 pbrook
   We assume a target will recognise these automatically .  */
1114 86831435 pbrook
static inline void tcg_gen_ext8u_i32(TCGv ret, TCGv arg)
1115 86831435 pbrook
{
1116 86831435 pbrook
    tcg_gen_andi_i32(ret, arg, 0xffu);
1117 86831435 pbrook
}
1118 86831435 pbrook
1119 86831435 pbrook
static inline void tcg_gen_ext16u_i32(TCGv ret, TCGv arg)
1120 86831435 pbrook
{
1121 86831435 pbrook
    tcg_gen_andi_i32(ret, arg, 0xffffu);
1122 86831435 pbrook
}
1123 86831435 pbrook
1124 c896fe29 bellard
/* Note: we assume the two high bytes are set to zero */
1125 ac56dd48 pbrook
static inline void tcg_gen_bswap16_i32(TCGv ret, TCGv arg)
1126 c896fe29 bellard
{
1127 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap16_i32
1128 c896fe29 bellard
    tcg_gen_op2(INDEX_op_bswap16_i32, ret, arg);
1129 c896fe29 bellard
#else
1130 ac56dd48 pbrook
    TCGv t0, t1;
1131 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
1132 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
1133 c896fe29 bellard
    
1134 c896fe29 bellard
    tcg_gen_shri_i32(t0, arg, 8);
1135 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x000000ff);
1136 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
1137 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
1138 e8996ee0 bellard
    tcg_temp_free(t0);
1139 e8996ee0 bellard
    tcg_temp_free(t1);
1140 c896fe29 bellard
#endif
1141 c896fe29 bellard
}
1142 c896fe29 bellard
1143 ac56dd48 pbrook
static inline void tcg_gen_bswap_i32(TCGv ret, TCGv arg)
1144 c896fe29 bellard
{
1145 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap_i32
1146 c896fe29 bellard
    tcg_gen_op2(INDEX_op_bswap_i32, ret, arg);
1147 c896fe29 bellard
#else
1148 ac56dd48 pbrook
    TCGv t0, t1;
1149 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
1150 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
1151 c896fe29 bellard
    
1152 c896fe29 bellard
    tcg_gen_shli_i32(t0, arg, 24);
1153 c896fe29 bellard
    
1154 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1155 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
1156 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
1157 c896fe29 bellard
    
1158 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 8);
1159 c896fe29 bellard
    tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1160 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
1161 c896fe29 bellard
    
1162 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 24);
1163 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
1164 e8996ee0 bellard
    tcg_temp_free(t0);
1165 e8996ee0 bellard
    tcg_temp_free(t1);
1166 c896fe29 bellard
#endif
1167 c896fe29 bellard
}
1168 c896fe29 bellard
1169 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1170 ac56dd48 pbrook
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg)
1171 c896fe29 bellard
{
1172 c896fe29 bellard
    tcg_gen_ext8s_i32(ret, arg);
1173 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1174 c896fe29 bellard
}
1175 c896fe29 bellard
1176 ac56dd48 pbrook
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg)
1177 c896fe29 bellard
{
1178 c896fe29 bellard
    tcg_gen_ext16s_i32(ret, arg);
1179 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1180 c896fe29 bellard
}
1181 c896fe29 bellard
1182 ac56dd48 pbrook
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg)
1183 c896fe29 bellard
{
1184 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1185 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1186 c896fe29 bellard
}
1187 c896fe29 bellard
1188 86831435 pbrook
static inline void tcg_gen_ext8u_i64(TCGv ret, TCGv arg)
1189 86831435 pbrook
{
1190 86831435 pbrook
    tcg_gen_ext8u_i32(ret, arg);
1191 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1192 86831435 pbrook
}
1193 86831435 pbrook
1194 86831435 pbrook
static inline void tcg_gen_ext16u_i64(TCGv ret, TCGv arg)
1195 86831435 pbrook
{
1196 86831435 pbrook
    tcg_gen_ext16u_i32(ret, arg);
1197 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1198 86831435 pbrook
}
1199 86831435 pbrook
1200 86831435 pbrook
static inline void tcg_gen_ext32u_i64(TCGv ret, TCGv arg)
1201 86831435 pbrook
{
1202 86831435 pbrook
    tcg_gen_mov_i32(ret, arg);
1203 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1204 86831435 pbrook
}
1205 86831435 pbrook
1206 ac56dd48 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg)
1207 c896fe29 bellard
{
1208 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1209 c896fe29 bellard
}
1210 c896fe29 bellard
1211 ac56dd48 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg)
1212 c896fe29 bellard
{
1213 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1214 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1215 c896fe29 bellard
}
1216 c896fe29 bellard
1217 ac56dd48 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg)
1218 c896fe29 bellard
{
1219 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1220 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1221 c896fe29 bellard
}
1222 c896fe29 bellard
1223 ac56dd48 pbrook
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg)
1224 c896fe29 bellard
{
1225 ac56dd48 pbrook
    TCGv t0, t1;
1226 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
1227 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
1228 c896fe29 bellard
1229 c896fe29 bellard
    tcg_gen_bswap_i32(t0, arg);
1230 ac56dd48 pbrook
    tcg_gen_bswap_i32(t1, TCGV_HIGH(arg));
1231 c896fe29 bellard
    tcg_gen_mov_i32(ret, t1);
1232 ac56dd48 pbrook
    tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1233 e8996ee0 bellard
    tcg_temp_free(t0);
1234 e8996ee0 bellard
    tcg_temp_free(t1);
1235 c896fe29 bellard
}
1236 c896fe29 bellard
#else
1237 c896fe29 bellard
1238 ac56dd48 pbrook
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg)
1239 c896fe29 bellard
{
1240 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i64
1241 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext8s_i64, ret, arg);
1242 c896fe29 bellard
#else
1243 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 56);
1244 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 56);
1245 c896fe29 bellard
#endif
1246 c896fe29 bellard
}
1247 c896fe29 bellard
1248 ac56dd48 pbrook
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg)
1249 c896fe29 bellard
{
1250 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i64
1251 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext16s_i64, ret, arg);
1252 c896fe29 bellard
#else
1253 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 48);
1254 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 48);
1255 c896fe29 bellard
#endif
1256 c896fe29 bellard
}
1257 c896fe29 bellard
1258 ac56dd48 pbrook
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg)
1259 c896fe29 bellard
{
1260 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext32s_i64
1261 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext32s_i64, ret, arg);
1262 c896fe29 bellard
#else
1263 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 32);
1264 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 32);
1265 c896fe29 bellard
#endif
1266 c896fe29 bellard
}
1267 c896fe29 bellard
1268 86831435 pbrook
static inline void tcg_gen_ext8u_i64(TCGv ret, TCGv arg)
1269 86831435 pbrook
{
1270 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffu);
1271 86831435 pbrook
}
1272 86831435 pbrook
1273 86831435 pbrook
static inline void tcg_gen_ext16u_i64(TCGv ret, TCGv arg)
1274 86831435 pbrook
{
1275 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffu);
1276 86831435 pbrook
}
1277 86831435 pbrook
1278 86831435 pbrook
static inline void tcg_gen_ext32u_i64(TCGv ret, TCGv arg)
1279 86831435 pbrook
{
1280 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1281 86831435 pbrook
}
1282 86831435 pbrook
1283 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1284 ac56dd48 pbrook
   registers.  This will probably break MIPS64 targets.  */
1285 ac56dd48 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg)
1286 c896fe29 bellard
{
1287 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1288 c896fe29 bellard
}
1289 c896fe29 bellard
1290 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1291 c896fe29 bellard
   registers */
1292 ac56dd48 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg)
1293 c896fe29 bellard
{
1294 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1295 c896fe29 bellard
}
1296 c896fe29 bellard
1297 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1298 c896fe29 bellard
   registers */
1299 ac56dd48 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg)
1300 c896fe29 bellard
{
1301 c896fe29 bellard
    tcg_gen_ext32s_i64(ret, arg);
1302 c896fe29 bellard
}
1303 c896fe29 bellard
1304 ac56dd48 pbrook
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg)
1305 c896fe29 bellard
{
1306 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap_i64
1307 c896fe29 bellard
    tcg_gen_op2(INDEX_op_bswap_i64, ret, arg);
1308 c896fe29 bellard
#else
1309 ac56dd48 pbrook
    TCGv t0, t1;
1310 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
1311 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
1312 c896fe29 bellard
    
1313 c896fe29 bellard
    tcg_gen_shli_i64(t0, arg, 56);
1314 c896fe29 bellard
    
1315 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1316 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 40);
1317 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1318 c896fe29 bellard
    
1319 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1320 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 24);
1321 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1322 c896fe29 bellard
1323 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0xff000000);
1324 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 8);
1325 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1326 c896fe29 bellard
1327 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 8);
1328 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0xff000000);
1329 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1330 c896fe29 bellard
    
1331 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 24);
1332 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1333 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1334 c896fe29 bellard
1335 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 40);
1336 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1337 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1338 c896fe29 bellard
1339 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 56);
1340 c896fe29 bellard
    tcg_gen_or_i64(ret, t0, t1);
1341 e8996ee0 bellard
    tcg_temp_free(t0);
1342 e8996ee0 bellard
    tcg_temp_free(t1);
1343 c896fe29 bellard
#endif
1344 c896fe29 bellard
}
1345 c896fe29 bellard
1346 c896fe29 bellard
#endif
1347 c896fe29 bellard
1348 390efc54 pbrook
static inline void tcg_gen_neg_i32(TCGv ret, TCGv arg)
1349 390efc54 pbrook
{
1350 390efc54 pbrook
#ifdef TCG_TARGET_HAS_neg_i32
1351 390efc54 pbrook
    tcg_gen_op2(INDEX_op_neg_i32, ret, arg);
1352 390efc54 pbrook
#else
1353 e8996ee0 bellard
    TCGv t0 = tcg_const_i32(0);
1354 e8996ee0 bellard
    tcg_gen_sub_i32(ret, t0, arg);
1355 e8996ee0 bellard
    tcg_temp_free(t0);
1356 390efc54 pbrook
#endif
1357 390efc54 pbrook
}
1358 390efc54 pbrook
1359 390efc54 pbrook
static inline void tcg_gen_neg_i64(TCGv ret, TCGv arg)
1360 390efc54 pbrook
{
1361 390efc54 pbrook
#ifdef TCG_TARGET_HAS_neg_i64
1362 390efc54 pbrook
    tcg_gen_op2(INDEX_op_neg_i64, ret, arg);
1363 390efc54 pbrook
#else
1364 e8996ee0 bellard
    TCGv t0 = tcg_const_i64(0);
1365 e8996ee0 bellard
    tcg_gen_sub_i64(ret, t0, arg);
1366 e8996ee0 bellard
    tcg_temp_free(t0);
1367 390efc54 pbrook
#endif
1368 390efc54 pbrook
}
1369 390efc54 pbrook
1370 0b6ce4cf bellard
static inline void tcg_gen_not_i32(TCGv ret, TCGv arg)
1371 0b6ce4cf bellard
{
1372 e8996ee0 bellard
    tcg_gen_xori_i32(ret, arg, -1);
1373 0b6ce4cf bellard
}
1374 0b6ce4cf bellard
1375 0b6ce4cf bellard
static inline void tcg_gen_not_i64(TCGv ret, TCGv arg)
1376 0b6ce4cf bellard
{
1377 e8996ee0 bellard
    tcg_gen_xori_i64(ret, arg, -1);
1378 0b6ce4cf bellard
}
1379 5ff9d6a4 bellard
1380 5ff9d6a4 bellard
static inline void tcg_gen_discard_i32(TCGv arg)
1381 5ff9d6a4 bellard
{
1382 5ff9d6a4 bellard
    tcg_gen_op1(INDEX_op_discard, arg);
1383 5ff9d6a4 bellard
}
1384 5ff9d6a4 bellard
1385 5ff9d6a4 bellard
#if TCG_TARGET_REG_BITS == 32
1386 5ff9d6a4 bellard
static inline void tcg_gen_discard_i64(TCGv arg)
1387 5ff9d6a4 bellard
{
1388 5ff9d6a4 bellard
    tcg_gen_discard_i32(arg);
1389 5ff9d6a4 bellard
    tcg_gen_discard_i32(TCGV_HIGH(arg));
1390 5ff9d6a4 bellard
}
1391 5ff9d6a4 bellard
#else
1392 5ff9d6a4 bellard
static inline void tcg_gen_discard_i64(TCGv arg)
1393 5ff9d6a4 bellard
{
1394 5ff9d6a4 bellard
    tcg_gen_op1(INDEX_op_discard, arg);
1395 5ff9d6a4 bellard
}
1396 5ff9d6a4 bellard
#endif
1397 5ff9d6a4 bellard
1398 36aa55dc pbrook
static inline void tcg_gen_concat_i32_i64(TCGv dest, TCGv low, TCGv high)
1399 36aa55dc pbrook
{
1400 36aa55dc pbrook
#if TCG_TARGET_REG_BITS == 32
1401 36aa55dc pbrook
    tcg_gen_mov_i32(dest, low);
1402 36aa55dc pbrook
    tcg_gen_mov_i32(TCGV_HIGH(dest), high);
1403 36aa55dc pbrook
#else
1404 36aa55dc pbrook
    TCGv tmp = tcg_temp_new (TCG_TYPE_I64);
1405 36aa55dc pbrook
    /* This extension is only needed for type correctness.
1406 36aa55dc pbrook
       We may be able to do better given target specific information.  */
1407 36aa55dc pbrook
    tcg_gen_extu_i32_i64(tmp, high);
1408 36aa55dc pbrook
    tcg_gen_shli_i64(tmp, tmp, 32);
1409 36aa55dc pbrook
    tcg_gen_extu_i32_i64(dest, low);
1410 36aa55dc pbrook
    tcg_gen_or_i64(dest, dest, tmp);
1411 36aa55dc pbrook
    tcg_temp_free(tmp);
1412 36aa55dc pbrook
#endif
1413 36aa55dc pbrook
}
1414 36aa55dc pbrook
1415 945ca823 blueswir1
static inline void tcg_gen_concat32_i64(TCGv dest, TCGv low, TCGv high)
1416 945ca823 blueswir1
{
1417 945ca823 blueswir1
#if TCG_TARGET_REG_BITS == 32
1418 945ca823 blueswir1
    tcg_gen_concat_i32_i64(dest, low, high);
1419 945ca823 blueswir1
#else
1420 945ca823 blueswir1
    TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
1421 88422e2e pbrook
    tcg_gen_ext32u_i64(dest, low);
1422 945ca823 blueswir1
    tcg_gen_shli_i64(tmp, high, 32);
1423 88422e2e pbrook
    tcg_gen_or_i64(dest, dest, tmp);
1424 945ca823 blueswir1
    tcg_temp_free(tmp);
1425 945ca823 blueswir1
#endif
1426 945ca823 blueswir1
}
1427 945ca823 blueswir1
1428 f24cb33e aurel32
static inline void tcg_gen_andc_i32(TCGv ret, TCGv arg1, TCGv arg2)
1429 f24cb33e aurel32
{
1430 f24cb33e aurel32
    TCGv t0;
1431 f24cb33e aurel32
    t0 = tcg_temp_new(TCG_TYPE_I32);
1432 f24cb33e aurel32
    tcg_gen_not_i32(t0, arg2);
1433 f24cb33e aurel32
    tcg_gen_and_i32(ret, arg1, t0);
1434 f24cb33e aurel32
    tcg_temp_free(t0);
1435 f24cb33e aurel32
}
1436 f24cb33e aurel32
1437 f24cb33e aurel32
static inline void tcg_gen_andc_i64(TCGv ret, TCGv arg1, TCGv arg2)
1438 f24cb33e aurel32
{
1439 f24cb33e aurel32
    TCGv t0;
1440 f24cb33e aurel32
    t0 = tcg_temp_new(TCG_TYPE_I64);
1441 f24cb33e aurel32
    tcg_gen_not_i64(t0, arg2);
1442 f24cb33e aurel32
    tcg_gen_and_i64(ret, arg1, t0);
1443 f24cb33e aurel32
    tcg_temp_free(t0);
1444 f24cb33e aurel32
}
1445 f24cb33e aurel32
1446 f24cb33e aurel32
static inline void tcg_gen_eqv_i32(TCGv ret, TCGv arg1, TCGv arg2)
1447 f24cb33e aurel32
{
1448 f24cb33e aurel32
    TCGv t0;
1449 f24cb33e aurel32
    t0 = tcg_temp_new(TCG_TYPE_I32);
1450 f24cb33e aurel32
    tcg_gen_xor_i32(t0, arg1, arg2);
1451 f24cb33e aurel32
    tcg_gen_not_i32(ret, t0);
1452 f24cb33e aurel32
    tcg_temp_free(t0);
1453 f24cb33e aurel32
}
1454 f24cb33e aurel32
1455 f24cb33e aurel32
static inline void tcg_gen_eqv_i64(TCGv ret, TCGv arg1, TCGv arg2)
1456 f24cb33e aurel32
{
1457 f24cb33e aurel32
    TCGv t0;
1458 f24cb33e aurel32
    t0 = tcg_temp_new(TCG_TYPE_I64);
1459 f24cb33e aurel32
    tcg_gen_xor_i64(t0, arg1, arg2);
1460 f24cb33e aurel32
    tcg_gen_not_i64(ret, t0);
1461 f24cb33e aurel32
    tcg_temp_free(t0);
1462 f24cb33e aurel32
}
1463 f24cb33e aurel32
1464 f24cb33e aurel32
static inline void tcg_gen_nand_i32(TCGv ret, TCGv arg1, TCGv arg2)
1465 f24cb33e aurel32
{
1466 f24cb33e aurel32
    TCGv t0;
1467 f24cb33e aurel32
    t0 = tcg_temp_new(TCG_TYPE_I32);
1468 f24cb33e aurel32
    tcg_gen_and_i32(t0, arg1, arg2);
1469 f24cb33e aurel32
    tcg_gen_not_i32(ret, t0);
1470 f24cb33e aurel32
    tcg_temp_free(t0);
1471 f24cb33e aurel32
}
1472 f24cb33e aurel32
1473 f24cb33e aurel32
static inline void tcg_gen_nand_i64(TCGv ret, TCGv arg1, TCGv arg2)
1474 f24cb33e aurel32
{
1475 f24cb33e aurel32
    TCGv t0;
1476 f24cb33e aurel32
    t0 = tcg_temp_new(TCG_TYPE_I64);
1477 f24cb33e aurel32
    tcg_gen_and_i64(t0, arg1, arg2);
1478 f24cb33e aurel32
    tcg_gen_not_i64(ret, t0);
1479 f24cb33e aurel32
    tcg_temp_free(t0);
1480 f24cb33e aurel32
}
1481 f24cb33e aurel32
1482 f24cb33e aurel32
static inline void tcg_gen_nor_i32(TCGv ret, TCGv arg1, TCGv arg2)
1483 f24cb33e aurel32
{
1484 f24cb33e aurel32
    TCGv t0;
1485 f24cb33e aurel32
    t0 = tcg_temp_new(TCG_TYPE_I32);
1486 f24cb33e aurel32
    tcg_gen_or_i32(t0, arg1, arg2);
1487 f24cb33e aurel32
    tcg_gen_not_i32(ret, t0);
1488 f24cb33e aurel32
    tcg_temp_free(t0);
1489 f24cb33e aurel32
}
1490 f24cb33e aurel32
1491 f24cb33e aurel32
static inline void tcg_gen_nor_i64(TCGv ret, TCGv arg1, TCGv arg2)
1492 f24cb33e aurel32
{
1493 f24cb33e aurel32
    TCGv t0;
1494 f24cb33e aurel32
    t0 = tcg_temp_new(TCG_TYPE_I64);
1495 f24cb33e aurel32
    tcg_gen_or_i64(t0, arg1, arg2);
1496 f24cb33e aurel32
    tcg_gen_not_i64(ret, t0);
1497 f24cb33e aurel32
    tcg_temp_free(t0);
1498 f24cb33e aurel32
}
1499 f24cb33e aurel32
1500 f24cb33e aurel32
static inline void tcg_gen_orc_i32(TCGv ret, TCGv arg1, TCGv arg2)
1501 f24cb33e aurel32
{
1502 f24cb33e aurel32
    TCGv t0;
1503 f24cb33e aurel32
    t0 = tcg_temp_new(TCG_TYPE_I32);
1504 f24cb33e aurel32
    tcg_gen_not_i32(t0, arg2);
1505 f24cb33e aurel32
    tcg_gen_or_i32(ret, arg1, t0);
1506 f24cb33e aurel32
    tcg_temp_free(t0);
1507 f24cb33e aurel32
}
1508 f24cb33e aurel32
1509 f24cb33e aurel32
static inline void tcg_gen_orc_i64(TCGv ret, TCGv arg1, TCGv arg2)
1510 f24cb33e aurel32
{
1511 f24cb33e aurel32
    TCGv t0;
1512 f24cb33e aurel32
    t0 = tcg_temp_new(TCG_TYPE_I64);
1513 f24cb33e aurel32
    tcg_gen_not_i64(t0, arg2);
1514 f24cb33e aurel32
    tcg_gen_or_i64(ret, arg1, t0);
1515 f24cb33e aurel32
    tcg_temp_free(t0);
1516 f24cb33e aurel32
}
1517 f24cb33e aurel32
1518 c896fe29 bellard
/***************************************/
1519 c896fe29 bellard
/* QEMU specific operations. Their type depend on the QEMU CPU
1520 c896fe29 bellard
   type. */
1521 c896fe29 bellard
#ifndef TARGET_LONG_BITS
1522 c896fe29 bellard
#error must include QEMU headers
1523 c896fe29 bellard
#endif
1524 c896fe29 bellard
1525 7e4597d7 bellard
/* debug info: write the PC of the corresponding QEMU CPU instruction */
1526 7e4597d7 bellard
static inline void tcg_gen_debug_insn_start(uint64_t pc)
1527 7e4597d7 bellard
{
1528 7e4597d7 bellard
    /* XXX: must really use a 32 bit size for TCGArg in all cases */
1529 7e4597d7 bellard
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1530 bcb0126f pbrook
    tcg_gen_op2ii(INDEX_op_debug_insn_start, 
1531 bcb0126f pbrook
                  (uint32_t)(pc), (uint32_t)(pc >> 32));
1532 7e4597d7 bellard
#else
1533 7e4597d7 bellard
    tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
1534 7e4597d7 bellard
#endif
1535 7e4597d7 bellard
}
1536 7e4597d7 bellard
1537 c896fe29 bellard
static inline void tcg_gen_exit_tb(tcg_target_long val)
1538 c896fe29 bellard
{
1539 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_exit_tb, val);
1540 c896fe29 bellard
}
1541 c896fe29 bellard
1542 c896fe29 bellard
static inline void tcg_gen_goto_tb(int idx)
1543 c896fe29 bellard
{
1544 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_goto_tb, idx);
1545 c896fe29 bellard
}
1546 c896fe29 bellard
1547 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1548 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1549 c896fe29 bellard
{
1550 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1551 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1552 c896fe29 bellard
#else
1553 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld8u, ret, addr, TCGV_HIGH(addr), mem_index);
1554 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1555 c896fe29 bellard
#endif
1556 c896fe29 bellard
}
1557 c896fe29 bellard
1558 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1559 c896fe29 bellard
{
1560 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1561 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1562 c896fe29 bellard
#else
1563 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld8s, ret, addr, TCGV_HIGH(addr), mem_index);
1564 21fc3cfc pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1565 c896fe29 bellard
#endif
1566 c896fe29 bellard
}
1567 c896fe29 bellard
1568 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1569 c896fe29 bellard
{
1570 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1571 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1572 c896fe29 bellard
#else
1573 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld16u, ret, addr, TCGV_HIGH(addr), mem_index);
1574 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1575 c896fe29 bellard
#endif
1576 c896fe29 bellard
}
1577 c896fe29 bellard
1578 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1579 c896fe29 bellard
{
1580 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1581 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1582 c896fe29 bellard
#else
1583 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld16s, ret, addr, TCGV_HIGH(addr), mem_index);
1584 21fc3cfc pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1585 c896fe29 bellard
#endif
1586 c896fe29 bellard
}
1587 c896fe29 bellard
1588 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1589 c896fe29 bellard
{
1590 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1591 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1592 c896fe29 bellard
#else
1593 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index);
1594 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1595 c896fe29 bellard
#endif
1596 c896fe29 bellard
}
1597 c896fe29 bellard
1598 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1599 c896fe29 bellard
{
1600 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1601 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1602 c896fe29 bellard
#else
1603 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index);
1604 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1605 c896fe29 bellard
#endif
1606 c896fe29 bellard
}
1607 c896fe29 bellard
1608 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index)
1609 c896fe29 bellard
{
1610 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1611 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret), addr, mem_index);
1612 c896fe29 bellard
#else
1613 ac56dd48 pbrook
    tcg_gen_op5i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret),
1614 ac56dd48 pbrook
                 addr, TCGV_HIGH(addr), mem_index);
1615 c896fe29 bellard
#endif
1616 c896fe29 bellard
}
1617 c896fe29 bellard
1618 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1619 c896fe29 bellard
{
1620 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1621 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index);
1622 c896fe29 bellard
#else
1623 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st8, arg, addr, TCGV_HIGH(addr), mem_index);
1624 c896fe29 bellard
#endif
1625 c896fe29 bellard
}
1626 c896fe29 bellard
1627 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1628 c896fe29 bellard
{
1629 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1630 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index);
1631 c896fe29 bellard
#else
1632 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st16, arg, addr, TCGV_HIGH(addr), mem_index);
1633 c896fe29 bellard
#endif
1634 c896fe29 bellard
}
1635 c896fe29 bellard
1636 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1637 c896fe29 bellard
{
1638 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1639 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index);
1640 c896fe29 bellard
#else
1641 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st32, arg, addr, TCGV_HIGH(addr), mem_index);
1642 c896fe29 bellard
#endif
1643 c896fe29 bellard
}
1644 c896fe29 bellard
1645 ac56dd48 pbrook
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index)
1646 c896fe29 bellard
{
1647 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1648 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg), addr, mem_index);
1649 c896fe29 bellard
#else
1650 ac56dd48 pbrook
    tcg_gen_op5i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg),
1651 ac56dd48 pbrook
                 addr, TCGV_HIGH(addr), mem_index);
1652 c896fe29 bellard
#endif
1653 c896fe29 bellard
}
1654 c896fe29 bellard
1655 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i32
1656 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i32
1657 f8422f52 blueswir1
1658 c896fe29 bellard
#else /* TCG_TARGET_REG_BITS == 32 */
1659 c896fe29 bellard
1660 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1661 c896fe29 bellard
{
1662 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1663 c896fe29 bellard
}
1664 c896fe29 bellard
1665 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1666 c896fe29 bellard
{
1667 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1668 c896fe29 bellard
}
1669 c896fe29 bellard
1670 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1671 c896fe29 bellard
{
1672 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1673 c896fe29 bellard
}
1674 c896fe29 bellard
1675 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1676 c896fe29 bellard
{
1677 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1678 c896fe29 bellard
}
1679 c896fe29 bellard
1680 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1681 c896fe29 bellard
{
1682 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1683 c896fe29 bellard
}
1684 c896fe29 bellard
1685 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1686 c896fe29 bellard
{
1687 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32s, ret, addr, mem_index);
1688 c896fe29 bellard
}
1689 c896fe29 bellard
1690 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index)
1691 c896fe29 bellard
{
1692 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld64, ret, addr, mem_index);
1693 c896fe29 bellard
}
1694 c896fe29 bellard
1695 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1696 c896fe29 bellard
{
1697 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index);
1698 c896fe29 bellard
}
1699 c896fe29 bellard
1700 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1701 c896fe29 bellard
{
1702 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index);
1703 c896fe29 bellard
}
1704 c896fe29 bellard
1705 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1706 c896fe29 bellard
{
1707 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index);
1708 c896fe29 bellard
}
1709 c896fe29 bellard
1710 ac56dd48 pbrook
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index)
1711 c896fe29 bellard
{
1712 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st64, arg, addr, mem_index);
1713 c896fe29 bellard
}
1714 c896fe29 bellard
1715 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i64
1716 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i64
1717 f8422f52 blueswir1
1718 c896fe29 bellard
#endif /* TCG_TARGET_REG_BITS != 32 */
1719 f8422f52 blueswir1
1720 f8422f52 blueswir1
#if TARGET_LONG_BITS == 64
1721 f8422f52 blueswir1
#define TCG_TYPE_TL TCG_TYPE_I64
1722 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i64
1723 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i64
1724 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
1725 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
1726 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
1727 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
1728 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
1729 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
1730 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i64
1731 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i64
1732 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i64
1733 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st32_i64
1734 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i64
1735 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i64
1736 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i64
1737 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i64
1738 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i64
1739 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i64
1740 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i64
1741 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i64
1742 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i64
1743 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i64
1744 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i64
1745 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i64
1746 0b6ce4cf bellard
#define tcg_gen_not_tl tcg_gen_not_i64
1747 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i64
1748 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i64
1749 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i64
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#define tcg_gen_shri_tl tcg_gen_shri_i64
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#define tcg_gen_sar_tl tcg_gen_sar_i64
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#define tcg_gen_sari_tl tcg_gen_sari_i64
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#define tcg_gen_brcond_tl tcg_gen_brcond_i64
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#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
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#define tcg_gen_mul_tl tcg_gen_mul_i64
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#define tcg_gen_muli_tl tcg_gen_muli_i64
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#define tcg_gen_discard_tl tcg_gen_discard_i64
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#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
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#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
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#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
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#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
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#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
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#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
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#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
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#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
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#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
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#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
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#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
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#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
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#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
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#define tcg_gen_andc_tl tcg_gen_andc_i64
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#define tcg_gen_eqv_tl tcg_gen_eqv_i64
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#define tcg_gen_nand_tl tcg_gen_nand_i64
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#define tcg_gen_nor_tl tcg_gen_nor_i64
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#define tcg_gen_orc_tl tcg_gen_orc_i64
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#define tcg_const_tl tcg_const_i64
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#else
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#define TCG_TYPE_TL TCG_TYPE_I32
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#define tcg_gen_movi_tl tcg_gen_movi_i32
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#define tcg_gen_mov_tl tcg_gen_mov_i32
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#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
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#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
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#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
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#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
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#define tcg_gen_ld32u_tl tcg_gen_ld_i32
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#define tcg_gen_ld32s_tl tcg_gen_ld_i32
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#define tcg_gen_ld_tl tcg_gen_ld_i32
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#define tcg_gen_st8_tl tcg_gen_st8_i32
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#define tcg_gen_st16_tl tcg_gen_st16_i32
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#define tcg_gen_st32_tl tcg_gen_st_i32
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#define tcg_gen_st_tl tcg_gen_st_i32
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#define tcg_gen_add_tl tcg_gen_add_i32
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#define tcg_gen_addi_tl tcg_gen_addi_i32
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#define tcg_gen_sub_tl tcg_gen_sub_i32
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#define tcg_gen_neg_tl tcg_gen_neg_i32
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#define tcg_gen_subi_tl tcg_gen_subi_i32
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#define tcg_gen_and_tl tcg_gen_and_i32
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#define tcg_gen_andi_tl tcg_gen_andi_i32
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#define tcg_gen_or_tl tcg_gen_or_i32
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#define tcg_gen_ori_tl tcg_gen_ori_i32
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#define tcg_gen_xor_tl tcg_gen_xor_i32
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#define tcg_gen_xori_tl tcg_gen_xori_i32
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#define tcg_gen_not_tl tcg_gen_not_i32
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#define tcg_gen_shl_tl tcg_gen_shl_i32
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#define tcg_gen_shli_tl tcg_gen_shli_i32
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#define tcg_gen_shr_tl tcg_gen_shr_i32
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#define tcg_gen_shri_tl tcg_gen_shri_i32
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#define tcg_gen_sar_tl tcg_gen_sar_i32
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#define tcg_gen_sari_tl tcg_gen_sari_i32
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#define tcg_gen_brcond_tl tcg_gen_brcond_i32
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#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
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#define tcg_gen_mul_tl tcg_gen_mul_i32
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#define tcg_gen_muli_tl tcg_gen_muli_i32
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#define tcg_gen_discard_tl tcg_gen_discard_i32
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#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
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#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
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#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
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#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
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#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
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#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
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#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
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#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
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#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
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#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
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#define tcg_gen_ext32u_tl tcg_gen_mov_i32
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#define tcg_gen_ext32s_tl tcg_gen_mov_i32
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#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
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#define tcg_gen_andc_tl tcg_gen_andc_i32
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#define tcg_gen_eqv_tl tcg_gen_eqv_i32
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#define tcg_gen_nand_tl tcg_gen_nand_i32
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#define tcg_gen_nor_tl tcg_gen_nor_i32
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#define tcg_gen_orc_tl tcg_gen_orc_i32
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#define tcg_const_tl tcg_const_i32
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#endif
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#if TCG_TARGET_REG_BITS == 32
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#define tcg_gen_add_ptr tcg_gen_add_i32
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#define tcg_gen_addi_ptr tcg_gen_addi_i32
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#define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
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#else /* TCG_TARGET_REG_BITS == 32 */
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#define tcg_gen_add_ptr tcg_gen_add_i64
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#define tcg_gen_addi_ptr tcg_gen_addi_i64
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#define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
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#endif /* TCG_TARGET_REG_BITS != 32 */