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SH4: sleep instruction bug fix
fix a bug on 'sleep' instruction, which have caused halt of idle task.As i386 'hlt' instruction does, it should save PC before sleep.
(Shin-ichiro KAWASAKI)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5220 c046a42c-6fe2-441c-8c8c-71466251a162
sh4: CPU versioning.
Trivial patch adding CPU listing and the ability to do per-subtypeCVR/PVR/PRR values. Presently SH7750R and SH7751R definitions areprovided, as these are the ones in present use in-tree.
The CVR value for SH7751R is intentionally restricted so the kernel...
SH4: fix a regression introduced in r5122
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5132 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Remove dyngen leftovers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5126 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: final conversion to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5125 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert floating-point ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5124 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Remove most uses of cpu_T0 and cpu_T1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5122 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: TCG optimisations
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5121 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Convert remaining non-fp ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5120 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Convert shift functions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5119 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert control/status register load/store to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5118 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Convert memory loads/stores to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5117 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert some more arithmetics ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5116 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert a few helpers to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5112 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert branch/jump instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5111 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert simple compare instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5108 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert a few control or system register functions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5107 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Fix bugs introduce in r5099
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5106 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: fix xtrct Rm,Rn (broken in r5103)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5105 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert logic and arithmetic ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5103 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: use TCG variables for gregs
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5102 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: use uint32_t/i32 based types/ops
Use uint32_t/i32 based types/ops to stay consistent with previous dyngencode. Thanks to Paul Brook for noticing that.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5101 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Convert register moves to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5100 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Convert dyngen registers moves to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5099 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Convert immediate loads to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5098 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: add support for TCG helpers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5096 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Init TCG variables
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5095 c046a42c-6fe2-441c-8c8c-71466251a162
sh4: fix tas.b @Rn instruction
(Shin-ichiro KAWASAKI, based on a patch from Andrzej Zaborowski)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5074 c046a42c-6fe2-441c-8c8c-71466251a162
[sh4] code translation bug fix
When a TLB miss occurs while pre-decrement store instruction such as"mov.l Rm, @-Rn" is executed, re-execution of such instruction causestatus confusion. Because pre Rn decrement is executed before TLB miss,re-execution decrements Rn again....
[sh4] delay slot bug fix
Two bugs about delay slot handlings are fixed.
- After an exception occurred in delay slot, the branch instruction before delay slot should be executed again. To judge such re-execution is necessery or not, delay slot status is kept in SH4 CPU data structure....
[sh4] sleep instruction
This patch adds sleep instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5065 c046a42c-6fe2-441c-8c8c-71466251a162
Fix warnings that would be generated by gcc -Wstrict-prototypes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5021 c046a42c-6fe2-441c-8c8c-71466251a162
Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
Add missing static qualifiers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4801 c046a42c-6fe2-441c-8c8c-71466251a162
Add instruction counter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
SH4 MMU improvements
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4396 c046a42c-6fe2-441c-8c8c-71466251a162
Factorize code in translate.c
(Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162
Remove osdep.c/qemu-img code duplication
(Kevin Wolf)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
SH4, fix several instructions
fix instruction code for frchg, fschg, ocbp.fix addressing mode handling for Rn+, -Rn, (disp,gbr).fix operation for div0s.fix comments for mov imm, add imm, (r0+,gbr), mac.l Rm+,@Rn+.fix ldb to ldub for or/tst/xor.b #imm,(r0,gbr)....
Rn+,
(disp,gbr).fix operation for div0s.fix comments for mov imm, add imm,
Rm+,@Rn+.fix ldb to ldub for or/tst/xor.b #imm,
use the TCG code generator
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
SH4 delay slot code update, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3761 c046a42c-6fe2-441c-8c8c-71466251a162
fixed FPU rounding init
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3615 c046a42c-6fe2-441c-8c8c-71466251a162
added cpu_model parameter to cpu_init()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
Fix rte opcode, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3273 c046a42c-6fe2-441c-8c8c-71466251a162
find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
Fix tb->size mishandling, by Daniel Jacobowitz.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3160 c046a42c-6fe2-441c-8c8c-71466251a162
SH4 mov.b fix, by Vince Weaver.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3152 c046a42c-6fe2-441c-8c8c-71466251a162
Ignore PR flag in FPSCR when performing fmov, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3005 c046a42c-6fe2-441c-8c8c-71466251a162
Document FPSCR usage, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3004 c046a42c-6fe2-441c-8c8c-71466251a162
Use DREG instead of XREG wherever possible, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3003 c046a42c-6fe2-441c-8c8c-71466251a162
Emulate more fpu opcodes, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3002 c046a42c-6fe2-441c-8c8c-71466251a162
Set FD bit in SR to emulate kernel behaviour, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2999 c046a42c-6fe2-441c-8c8c-71466251a162
Fix XHACK macro and use FREG if possible, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2815 c046a42c-6fe2-441c-8c8c-71466251a162
Fix opcode for sts.l fpul/cpscr, by Magnus Damm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2729 c046a42c-6fe2-441c-8c8c-71466251a162
Define gen_intermediate_code_internal as "static inline".
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2512 c046a42c-6fe2-441c-8c8c-71466251a162
SH bugfixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1991 c046a42c-6fe2-441c-8c8c-71466251a162
Remove debug output.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1990 c046a42c-6fe2-441c-8c8c-71466251a162
SH usermode fault handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1988 c046a42c-6fe2-441c-8c8c-71466251a162
SH4 rts fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1987 c046a42c-6fe2-441c-8c8c-71466251a162
sh4 fmov et al instructions (amatus)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1971 c046a42c-6fe2-441c-8c8c-71466251a162
sh4 target (Samuel Tardieu)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1861 c046a42c-6fe2-441c-8c8c-71466251a162