Revision f2bc7e7f target-sparc/helper.c
| b/target-sparc/helper.c | ||
|---|---|---|
| 32 | 32 |
|
| 33 | 33 |
//#define DEBUG_MMU |
| 34 | 34 |
//#define DEBUG_FEATURES |
| 35 |
//#define DEBUG_PCALL |
|
| 35 | 36 |
|
| 36 | 37 |
typedef struct sparc_def_t sparc_def_t; |
| 37 | 38 |
|
| ... | ... | |
| 651 | 652 |
} |
| 652 | 653 |
#endif |
| 653 | 654 |
|
| 655 |
#ifdef TARGET_SPARC64 |
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| 656 |
#ifdef DEBUG_PCALL |
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| 657 |
static const char * const excp_names[0x50] = {
|
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| 658 |
[TT_TFAULT] = "Instruction Access Fault", |
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| 659 |
[TT_TMISS] = "Instruction Access MMU Miss", |
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| 660 |
[TT_CODE_ACCESS] = "Instruction Access Error", |
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| 661 |
[TT_ILL_INSN] = "Illegal Instruction", |
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| 662 |
[TT_PRIV_INSN] = "Privileged Instruction", |
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[TT_NFPU_INSN] = "FPU Disabled", |
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[TT_FP_EXCP] = "FPU Exception", |
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[TT_TOVF] = "Tag Overflow", |
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[TT_CLRWIN] = "Clean Windows", |
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[TT_DIV_ZERO] = "Division By Zero", |
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[TT_DFAULT] = "Data Access Fault", |
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[TT_DMISS] = "Data Access MMU Miss", |
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[TT_DATA_ACCESS] = "Data Access Error", |
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[TT_DPROT] = "Data Protection Error", |
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[TT_UNALIGNED] = "Unaligned Memory Access", |
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[TT_PRIV_ACT] = "Privileged Action", |
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[TT_EXTINT | 0x1] = "External Interrupt 1", |
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[TT_EXTINT | 0x2] = "External Interrupt 2", |
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[TT_EXTINT | 0x3] = "External Interrupt 3", |
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[TT_EXTINT | 0x4] = "External Interrupt 4", |
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[TT_EXTINT | 0x5] = "External Interrupt 5", |
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[TT_EXTINT | 0x6] = "External Interrupt 6", |
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[TT_EXTINT | 0x7] = "External Interrupt 7", |
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[TT_EXTINT | 0x8] = "External Interrupt 8", |
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[TT_EXTINT | 0x9] = "External Interrupt 9", |
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[TT_EXTINT | 0xa] = "External Interrupt 10", |
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[TT_EXTINT | 0xb] = "External Interrupt 11", |
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[TT_EXTINT | 0xc] = "External Interrupt 12", |
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[TT_EXTINT | 0xd] = "External Interrupt 13", |
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[TT_EXTINT | 0xe] = "External Interrupt 14", |
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[TT_EXTINT | 0xf] = "External Interrupt 15", |
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}; |
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#endif |
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|
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void do_interrupt(CPUState *env) |
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{
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int intno = env->exception_index; |
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|
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#ifdef DEBUG_PCALL |
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if (loglevel & CPU_LOG_INT) {
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static int count; |
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const char *name; |
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|
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if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80)) |
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name = "Unknown"; |
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else if (intno >= 0x100) |
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name = "Trap Instruction"; |
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else if (intno >= 0xc0) |
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name = "Window Fill"; |
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else if (intno >= 0x80) |
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name = "Window Spill"; |
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else {
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name = excp_names[intno]; |
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if (!name) |
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name = "Unknown"; |
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} |
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|
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fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64 |
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" SP=%016" PRIx64 "\n", |
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count, name, intno, |
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env->pc, |
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env->npc, env->regwptr[6]); |
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cpu_dump_state(env, logfile, fprintf, 0); |
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#if 0 |
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{
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int i; |
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uint8_t *ptr; |
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|
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fprintf(logfile, " code="); |
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ptr = (uint8_t *)env->pc; |
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for(i = 0; i < 16; i++) {
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fprintf(logfile, " %02x", ldub(ptr + i)); |
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} |
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fprintf(logfile, "\n"); |
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} |
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#endif |
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count++; |
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} |
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#endif |
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#if !defined(CONFIG_USER_ONLY) |
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if (env->tl == MAXTL) {
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cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", |
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env->exception_index); |
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return; |
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} |
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#endif |
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env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) | |
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((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | |
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GET_CWP64(env); |
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env->tsptr->tpc = env->pc; |
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env->tsptr->tnpc = env->npc; |
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env->tsptr->tt = intno; |
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change_pstate(PS_PEF | PS_PRIV | PS_AG); |
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|
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if (intno == TT_CLRWIN) |
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cpu_set_cwp(env, (env->cwp - 1) & (NWINDOWS - 1)); |
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else if ((intno & 0x1c0) == TT_SPILL) |
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cpu_set_cwp(env, (env->cwp - env->cansave - 2) & (NWINDOWS - 1)); |
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else if ((intno & 0x1c0) == TT_FILL) |
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cpu_set_cwp(env, (env->cwp + 1) & (NWINDOWS - 1)); |
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env->tbr &= ~0x7fffULL; |
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env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); |
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if (env->tl < MAXTL - 1) {
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env->tl++; |
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} else {
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env->pstate |= PS_RED; |
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if (env->tl != MAXTL) |
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env->tl++; |
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} |
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env->tsptr = &env->ts[env->tl]; |
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env->pc = env->tbr; |
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env->npc = env->pc + 4; |
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env->exception_index = 0; |
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} |
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#else |
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#ifdef DEBUG_PCALL |
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static const char * const excp_names[0x80] = {
|
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[TT_TFAULT] = "Instruction Access Fault", |
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[TT_ILL_INSN] = "Illegal Instruction", |
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[TT_PRIV_INSN] = "Privileged Instruction", |
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[TT_NFPU_INSN] = "FPU Disabled", |
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[TT_WIN_OVF] = "Window Overflow", |
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[TT_WIN_UNF] = "Window Underflow", |
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[TT_UNALIGNED] = "Unaligned Memory Access", |
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[TT_FP_EXCP] = "FPU Exception", |
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[TT_DFAULT] = "Data Access Fault", |
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[TT_TOVF] = "Tag Overflow", |
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[TT_EXTINT | 0x1] = "External Interrupt 1", |
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[TT_EXTINT | 0x2] = "External Interrupt 2", |
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[TT_EXTINT | 0x3] = "External Interrupt 3", |
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[TT_EXTINT | 0x4] = "External Interrupt 4", |
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[TT_EXTINT | 0x5] = "External Interrupt 5", |
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[TT_EXTINT | 0x6] = "External Interrupt 6", |
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[TT_EXTINT | 0x7] = "External Interrupt 7", |
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[TT_EXTINT | 0x8] = "External Interrupt 8", |
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[TT_EXTINT | 0x9] = "External Interrupt 9", |
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[TT_EXTINT | 0xa] = "External Interrupt 10", |
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[TT_EXTINT | 0xb] = "External Interrupt 11", |
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[TT_EXTINT | 0xc] = "External Interrupt 12", |
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[TT_EXTINT | 0xd] = "External Interrupt 13", |
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[TT_EXTINT | 0xe] = "External Interrupt 14", |
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[TT_EXTINT | 0xf] = "External Interrupt 15", |
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| 800 |
[TT_TOVF] = "Tag Overflow", |
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[TT_CODE_ACCESS] = "Instruction Access Error", |
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[TT_DATA_ACCESS] = "Data Access Error", |
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| 803 |
[TT_DIV_ZERO] = "Division By Zero", |
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| 804 |
[TT_NCP_INSN] = "Coprocessor Disabled", |
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| 805 |
}; |
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| 806 |
#endif |
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| 807 |
|
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| 808 |
void do_interrupt(CPUState *env) |
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| 809 |
{
|
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| 810 |
int cwp, intno = env->exception_index; |
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| 811 |
|
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| 812 |
#ifdef DEBUG_PCALL |
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| 813 |
if (loglevel & CPU_LOG_INT) {
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| 814 |
static int count; |
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| 815 |
const char *name; |
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| 816 |
|
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| 817 |
if (intno < 0 || intno >= 0x100) |
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name = "Unknown"; |
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else if (intno >= 0x80) |
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name = "Trap Instruction"; |
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| 821 |
else {
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name = excp_names[intno]; |
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if (!name) |
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| 824 |
name = "Unknown"; |
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| 825 |
} |
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| 826 |
|
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fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n", |
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| 828 |
count, name, intno, |
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| 829 |
env->pc, |
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| 830 |
env->npc, env->regwptr[6]); |
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| 831 |
cpu_dump_state(env, logfile, fprintf, 0); |
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| 832 |
#if 0 |
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| 833 |
{
|
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| 834 |
int i; |
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| 835 |
uint8_t *ptr; |
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| 836 |
|
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fprintf(logfile, " code="); |
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ptr = (uint8_t *)env->pc; |
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| 839 |
for(i = 0; i < 16; i++) {
|
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| 840 |
fprintf(logfile, " %02x", ldub(ptr + i)); |
|
| 841 |
} |
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| 842 |
fprintf(logfile, "\n"); |
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| 843 |
} |
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| 844 |
#endif |
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| 845 |
count++; |
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| 846 |
} |
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| 847 |
#endif |
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| 848 |
#if !defined(CONFIG_USER_ONLY) |
|
| 849 |
if (env->psret == 0) {
|
|
| 850 |
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", |
|
| 851 |
env->exception_index); |
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| 852 |
return; |
|
| 853 |
} |
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| 854 |
#endif |
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| 855 |
env->psret = 0; |
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| 856 |
cwp = (env->cwp - 1) & (NWINDOWS - 1); |
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| 857 |
cpu_set_cwp(env, cwp); |
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| 858 |
env->regwptr[9] = env->pc; |
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| 859 |
env->regwptr[10] = env->npc; |
|
| 860 |
env->psrps = env->psrs; |
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| 861 |
env->psrs = 1; |
|
| 862 |
env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); |
|
| 863 |
env->pc = env->tbr; |
|
| 864 |
env->npc = env->pc + 4; |
|
| 865 |
env->exception_index = 0; |
|
| 866 |
} |
|
| 867 |
#endif |
|
| 868 |
|
|
| 654 | 869 |
void memcpy32(target_ulong *dst, const target_ulong *src) |
| 655 | 870 |
{
|
| 656 | 871 |
dst[0] = src[0]; |
| ... | ... | |
| 663 | 878 |
dst[7] = src[7]; |
| 664 | 879 |
} |
| 665 | 880 |
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| 666 |
void helper_flush(target_ulong addr) |
|
| 667 |
{
|
|
| 668 |
addr &= ~7; |
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| 669 |
tb_invalidate_page_range(addr, addr + 8); |
|
| 670 |
} |
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| 671 |
|
|
| 672 | 881 |
void cpu_reset(CPUSPARCState *env) |
| 673 | 882 |
{
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| 674 | 883 |
tlb_flush(env, 1); |
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