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Revision f364515c

IDf364515c836fcc7caa1606a8c27edae25f27a6ce

Added by aurel32 about 12 years ago

target-mips: fix FPU in 64-bit mode

TCG does not allow the same memory location to be aliased in two
different global registers, fpu_fpr32 and fpu_fpr64.

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6915 c046a42c-6fe2-441c-8c8c-71466251a162

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