Revision f364515c
| b/target-mips/translate.c | ||
|---|---|---|
| 432 | 432 |
static TCGv cpu_dspctrl, btarget; |
| 433 | 433 |
static TCGv_i32 bcond; |
| 434 | 434 |
static TCGv_i32 fpu_fpr32[32], fpu_fpr32h[32]; |
| 435 |
static TCGv_i64 fpu_fpr64[32]; |
|
| 436 | 435 |
static TCGv_i32 fpu_fcr0, fpu_fcr31; |
| 437 | 436 |
|
| 438 | 437 |
#include "gen-icount.h" |
| ... | ... | |
| 501 | 500 |
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 502 | 501 |
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; |
| 503 | 502 |
|
| 504 |
static const char *fregnames_64[] = |
|
| 505 |
{ "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
|
|
| 506 |
"F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15", |
|
| 507 |
"F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23", |
|
| 508 |
"F24", "F25", "F26", "F27", "F28", "F29", "F30", "F31", }; |
|
| 509 |
|
|
| 510 | 503 |
static const char *fregnames_h[] = |
| 511 | 504 |
{ "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
|
| 512 | 505 |
"h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", |
| ... | ... | |
| 617 | 610 |
|
| 618 | 611 |
static inline void gen_load_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg) |
| 619 | 612 |
{
|
| 620 |
if (ctx->hflags & MIPS_HFLAG_F64) |
|
| 621 |
tcg_gen_mov_i64(t, fpu_fpr64[reg]);
|
|
| 622 |
else {
|
|
| 613 |
if (ctx->hflags & MIPS_HFLAG_F64) {
|
|
| 614 |
tcg_gen_concat_i32_i64(t, fpu_fpr32[reg], fpu_fpr32h[reg]);
|
|
| 615 |
} else {
|
|
| 623 | 616 |
tcg_gen_concat_i32_i64(t, fpu_fpr32[reg & ~1], fpu_fpr32[reg | 1]); |
| 624 | 617 |
} |
| 625 | 618 |
} |
| 626 | 619 |
|
| 627 | 620 |
static inline void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg) |
| 628 | 621 |
{
|
| 629 |
if (ctx->hflags & MIPS_HFLAG_F64) |
|
| 630 |
tcg_gen_mov_i64(fpu_fpr64[reg], t); |
|
| 631 |
else {
|
|
| 622 |
if (ctx->hflags & MIPS_HFLAG_F64) {
|
|
| 623 |
tcg_gen_trunc_i64_i32(fpu_fpr32[reg], t); |
|
| 624 |
tcg_gen_shri_i64(t, t, 32); |
|
| 625 |
tcg_gen_trunc_i64_i32(fpu_fpr32h[reg], t); |
|
| 626 |
} else {
|
|
| 632 | 627 |
tcg_gen_trunc_i64_i32(fpu_fpr32[reg & ~1], t); |
| 633 | 628 |
tcg_gen_shri_i64(t, t, 32); |
| 634 | 629 |
tcg_gen_trunc_i64_i32(fpu_fpr32[reg | 1], t); |
| ... | ... | |
| 8442 | 8437 |
offsetof(CPUState, active_fpu.fpr[i].w[FP_ENDIAN_IDX]), |
| 8443 | 8438 |
fregnames[i]); |
| 8444 | 8439 |
for (i = 0; i < 32; i++) |
| 8445 |
fpu_fpr64[i] = tcg_global_mem_new_i64(TCG_AREG0, |
|
| 8446 |
offsetof(CPUState, active_fpu.fpr[i]), |
|
| 8447 |
fregnames_64[i]); |
|
| 8448 |
for (i = 0; i < 32; i++) |
|
| 8449 | 8440 |
fpu_fpr32h[i] = tcg_global_mem_new_i32(TCG_AREG0, |
| 8450 | 8441 |
offsetof(CPUState, active_fpu.fpr[i].w[!FP_ENDIAN_IDX]), |
| 8451 | 8442 |
fregnames_h[i]); |
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