Revision f41c52f1
| b/target-mips/op.c | ||
|---|---|---|
| 1360 | 1360 |
no 64bit addressing implemented. */ |
| 1361 | 1361 |
val = (int32_t)T0 & 0xF878FF17; |
| 1362 | 1362 |
old = env->CP0_Status; |
| 1363 |
if (!(val & (1 << CP0St_EXL)) && |
|
| 1364 |
!(val & (1 << CP0St_ERL)) && |
|
| 1365 |
!(env->hflags & MIPS_HFLAG_DM) && |
|
| 1366 |
(val & (1 << CP0St_UM))) |
|
| 1367 |
env->hflags |= MIPS_HFLAG_UM; |
|
| 1363 | 1368 |
env->CP0_Status = val; |
| 1364 |
if (loglevel & CPU_LOG_TB_IN_ASM)
|
|
| 1365 |
CALL_FROM_TB2(do_mtc0_status_debug, old, val); |
|
| 1369 |
if (loglevel & CPU_LOG_EXEC)
|
|
| 1370 |
CALL_FROM_TB2(do_mtc0_status_debug, old, val);
|
|
| 1366 | 1371 |
CALL_FROM_TB1(cpu_mips_update_irq, env); |
| 1367 | 1372 |
RETURN(); |
| 1368 | 1373 |
} |
| ... | ... | |
| 2077 | 2082 |
RETURN(); |
| 2078 | 2083 |
} |
| 2079 | 2084 |
|
| 2080 |
void debug_eret (void); |
|
| 2085 |
void debug_pre_eret (void); |
|
| 2086 |
void debug_post_eret (void); |
|
| 2081 | 2087 |
void op_eret (void) |
| 2082 | 2088 |
{
|
| 2083 |
CALL_FROM_TB0(debug_eret); |
|
| 2089 |
if (loglevel & CPU_LOG_EXEC) |
|
| 2090 |
CALL_FROM_TB0(debug_pre_eret); |
|
| 2084 | 2091 |
if (env->CP0_Status & (1 << CP0St_ERL)) {
|
| 2085 | 2092 |
env->PC = env->CP0_ErrorEPC; |
| 2086 | 2093 |
env->CP0_Status &= ~(1 << CP0St_ERL); |
| ... | ... | |
| 2093 | 2100 |
!(env->hflags & MIPS_HFLAG_DM) && |
| 2094 | 2101 |
(env->CP0_Status & (1 << CP0St_UM))) |
| 2095 | 2102 |
env->hflags |= MIPS_HFLAG_UM; |
| 2103 |
if (loglevel & CPU_LOG_EXEC) |
|
| 2104 |
CALL_FROM_TB0(debug_post_eret); |
|
| 2096 | 2105 |
env->CP0_LLAddr = 1; |
| 2097 | 2106 |
RETURN(); |
| 2098 | 2107 |
} |
| 2099 | 2108 |
|
| 2100 | 2109 |
void op_deret (void) |
| 2101 | 2110 |
{
|
| 2102 |
CALL_FROM_TB0(debug_eret); |
|
| 2111 |
if (loglevel & CPU_LOG_EXEC) |
|
| 2112 |
CALL_FROM_TB0(debug_pre_eret); |
|
| 2103 | 2113 |
env->PC = env->CP0_DEPC; |
| 2104 | 2114 |
env->hflags |= MIPS_HFLAG_DM; |
| 2105 | 2115 |
if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
| ... | ... | |
| 2107 | 2117 |
!(env->hflags & MIPS_HFLAG_DM) && |
| 2108 | 2118 |
(env->CP0_Status & (1 << CP0St_UM))) |
| 2109 | 2119 |
env->hflags |= MIPS_HFLAG_UM; |
| 2120 |
if (loglevel & CPU_LOG_EXEC) |
|
| 2121 |
CALL_FROM_TB0(debug_post_eret); |
|
| 2110 | 2122 |
env->CP0_LLAddr = 1; |
| 2111 | 2123 |
RETURN(); |
| 2112 | 2124 |
} |
| b/target-mips/op_helper.c | ||
|---|---|---|
| 329 | 329 |
|
| 330 | 330 |
void do_mtc0_status_debug(uint32_t old, uint32_t val) |
| 331 | 331 |
{
|
| 332 |
const uint32_t mask = 0x0000FF00; |
|
| 333 |
fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n", |
|
| 334 |
old, val, env->CP0_Cause, old & mask, val & mask, |
|
| 335 |
env->CP0_Cause & mask); |
|
| 332 |
fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x", |
|
| 333 |
old, old & env->CP0_Cause & CP0Ca_IP_mask, |
|
| 334 |
val, val & env->CP0_Cause & CP0Ca_IP_mask, |
|
| 335 |
env->CP0_Cause); |
|
| 336 |
(env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
|
|
| 337 |
: fputs("\n", logfile);
|
|
| 336 | 338 |
} |
| 337 | 339 |
|
| 338 | 340 |
void do_mtc0_status_irqraise_debug(void) |
| ... | ... | |
| 508 | 510 |
} |
| 509 | 511 |
} |
| 510 | 512 |
|
| 511 |
void debug_eret (void) |
|
| 513 |
void debug_pre_eret (void)
|
|
| 512 | 514 |
{
|
| 513 |
if (loglevel) {
|
|
| 514 |
fprintf(logfile, "ERET: pc " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
|
| 515 |
env->PC, env->CP0_EPC); |
|
| 516 |
if (env->CP0_Status & (1 << CP0St_ERL)) |
|
| 517 |
fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); |
|
| 515 |
fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
|
| 516 |
env->PC, env->CP0_EPC); |
|
| 517 |
if (env->CP0_Status & (1 << CP0St_ERL)) |
|
| 518 |
fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); |
|
| 519 |
if (env->hflags & MIPS_HFLAG_DM) |
|
| 520 |
fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC); |
|
| 521 |
fputs("\n", logfile);
|
|
| 522 |
} |
|
| 523 |
|
|
| 524 |
void debug_post_eret (void) |
|
| 525 |
{
|
|
| 526 |
fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
|
| 527 |
env->PC, env->CP0_EPC); |
|
| 528 |
if (env->CP0_Status & (1 << CP0St_ERL)) |
|
| 529 |
fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); |
|
| 530 |
if (env->hflags & MIPS_HFLAG_DM) |
|
| 531 |
fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC); |
|
| 532 |
if (env->hflags & MIPS_HFLAG_UM) |
|
| 533 |
fputs(", UM\n", logfile);
|
|
| 534 |
else |
|
| 518 | 535 |
fputs("\n", logfile);
|
| 519 |
} |
|
| 520 | 536 |
} |
| 521 | 537 |
|
| 522 | 538 |
void do_pmon (int function) |
| b/target-mips/translate.c | ||
|---|---|---|
| 4880 | 4880 |
} |
| 4881 | 4881 |
break; |
| 4882 | 4882 |
case OPC_CP0: |
| 4883 |
save_cpu_state(ctx, 1); |
|
| 4883 | 4884 |
gen_op_cp0_enabled(); |
| 4884 | 4885 |
op1 = MASK_CP0(ctx->opcode); |
| 4885 | 4886 |
switch (op1) {
|
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