Revision f41c52f1 target-mips/op_helper.c
| b/target-mips/op_helper.c | ||
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| 329 | 329 |
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void do_mtc0_status_debug(uint32_t old, uint32_t val) |
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{
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const uint32_t mask = 0x0000FF00; |
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fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n", |
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old, val, env->CP0_Cause, old & mask, val & mask, |
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env->CP0_Cause & mask); |
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fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x", |
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old, old & env->CP0_Cause & CP0Ca_IP_mask, |
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val, val & env->CP0_Cause & CP0Ca_IP_mask, |
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env->CP0_Cause); |
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(env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
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: fputs("\n", logfile);
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} |
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void do_mtc0_status_irqraise_debug(void) |
| ... | ... | |
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} |
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} |
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void debug_eret (void) |
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void debug_pre_eret (void)
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{
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if (loglevel) {
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fprintf(logfile, "ERET: pc " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
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env->PC, env->CP0_EPC); |
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if (env->CP0_Status & (1 << CP0St_ERL)) |
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fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); |
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fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
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env->PC, env->CP0_EPC); |
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if (env->CP0_Status & (1 << CP0St_ERL)) |
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fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); |
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if (env->hflags & MIPS_HFLAG_DM) |
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fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC); |
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fputs("\n", logfile);
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} |
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void debug_post_eret (void) |
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{
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fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
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env->PC, env->CP0_EPC); |
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if (env->CP0_Status & (1 << CP0St_ERL)) |
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fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); |
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if (env->hflags & MIPS_HFLAG_DM) |
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fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC); |
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if (env->hflags & MIPS_HFLAG_UM) |
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fputs(", UM\n", logfile);
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else |
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fputs("\n", logfile);
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} |
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} |
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void do_pmon (int function) |
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