root / hw / ide / microdrive.c @ f455e98c
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/*
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* QEMU IDE Emulation: microdrive (CF / PCMCIA)
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <hw/hw.h> |
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#include <hw/pc.h> |
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#include <hw/pcmcia.h> |
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#include "block.h" |
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#include "block_int.h" |
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#include "sysemu.h" |
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#include "dma.h" |
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#include <hw/ide/internal.h> |
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|
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/***********************************************************/
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/* CF-ATA Microdrive */
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#define METADATA_SIZE 0x20 |
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|
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/* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
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typedef struct { |
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IDEBus bus; |
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PCMCIACardState card; |
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uint32_t attr_base; |
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uint32_t io_base; |
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|
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/* Card state */
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uint8_t opt; |
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uint8_t stat; |
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uint8_t pins; |
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|
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uint8_t ctrl; |
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uint16_t io; |
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int cycle;
|
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} MicroDriveState; |
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|
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/* Register bitfields */
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enum md_opt {
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OPT_MODE_MMAP = 0,
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OPT_MODE_IOMAP16 = 1,
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OPT_MODE_IOMAP1 = 2,
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OPT_MODE_IOMAP2 = 3,
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OPT_MODE = 0x3f,
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OPT_LEVIREQ = 0x40,
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OPT_SRESET = 0x80,
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}; |
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enum md_cstat {
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STAT_INT = 0x02,
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STAT_PWRDWN = 0x04,
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STAT_XE = 0x10,
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STAT_IOIS8 = 0x20,
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STAT_SIGCHG = 0x40,
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STAT_CHANGED = 0x80,
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}; |
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enum md_pins {
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PINS_MRDY = 0x02,
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PINS_CRDY = 0x20,
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}; |
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enum md_ctrl {
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CTRL_IEN = 0x02,
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CTRL_SRST = 0x04,
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}; |
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|
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static inline void md_interrupt_update(MicroDriveState *s) |
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{
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if (!s->card.slot)
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return;
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|
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qemu_set_irq(s->card.slot->irq, |
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!(s->stat & STAT_INT) && /* Inverted */
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!(s->ctrl & (CTRL_IEN | CTRL_SRST)) && |
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!(s->opt & OPT_SRESET)); |
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} |
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|
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static void md_set_irq(void *opaque, int irq, int level) |
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{
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MicroDriveState *s = (MicroDriveState *) opaque; |
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if (level)
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s->stat |= STAT_INT; |
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else
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s->stat &= ~STAT_INT; |
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|
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md_interrupt_update(s); |
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} |
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|
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static void md_reset(MicroDriveState *s) |
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{
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s->opt = OPT_MODE_MMAP; |
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s->stat = 0;
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s->pins = 0;
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s->cycle = 0;
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s->ctrl = 0;
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ide_reset(s->bus.ifs); |
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} |
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|
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static uint8_t md_attr_read(void *opaque, uint32_t at) |
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{
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MicroDriveState *s = (MicroDriveState *) opaque; |
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if (at < s->attr_base) {
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if (at < s->card.cis_len)
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return s->card.cis[at];
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else
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return 0x00; |
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} |
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at -= s->attr_base; |
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switch (at) {
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case 0x00: /* Configuration Option Register */ |
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return s->opt;
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case 0x02: /* Card Configuration Status Register */ |
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if (s->ctrl & CTRL_IEN)
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return s->stat & ~STAT_INT;
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else
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return s->stat;
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case 0x04: /* Pin Replacement Register */ |
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return (s->pins & PINS_CRDY) | 0x0c; |
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case 0x06: /* Socket and Copy Register */ |
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return 0x00; |
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#ifdef VERBOSE
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default:
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printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
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#endif
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} |
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return 0; |
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} |
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static void md_attr_write(void *opaque, uint32_t at, uint8_t value) |
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{
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MicroDriveState *s = (MicroDriveState *) opaque; |
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at -= s->attr_base; |
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switch (at) {
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case 0x00: /* Configuration Option Register */ |
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s->opt = value & 0xcf;
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if (value & OPT_SRESET)
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md_reset(s); |
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md_interrupt_update(s); |
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break;
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case 0x02: /* Card Configuration Status Register */ |
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if ((s->stat ^ value) & STAT_PWRDWN)
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s->pins |= PINS_CRDY; |
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s->stat &= 0x82;
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s->stat |= value & 0x74;
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md_interrupt_update(s); |
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/* Word 170 in Identify Device must be equal to STAT_XE */
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break;
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case 0x04: /* Pin Replacement Register */ |
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s->pins &= PINS_CRDY; |
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s->pins |= value & PINS_MRDY; |
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break;
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case 0x06: /* Socket and Copy Register */ |
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break;
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default:
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printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
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} |
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} |
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static uint16_t md_common_read(void *opaque, uint32_t at) |
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{
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MicroDriveState *s = (MicroDriveState *) opaque; |
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IDEState *ifs; |
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uint16_t ret; |
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at -= s->io_base; |
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switch (s->opt & OPT_MODE) {
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case OPT_MODE_MMAP:
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if ((at & ~0x3ff) == 0x400) |
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at = 0;
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break;
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case OPT_MODE_IOMAP16:
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at &= 0xf;
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break;
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case OPT_MODE_IOMAP1:
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if ((at & ~0xf) == 0x3f0) |
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at -= 0x3e8;
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else if ((at & ~0xf) == 0x1f0) |
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at -= 0x1f0;
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break;
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case OPT_MODE_IOMAP2:
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if ((at & ~0xf) == 0x370) |
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at -= 0x368;
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else if ((at & ~0xf) == 0x170) |
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at -= 0x170;
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} |
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switch (at) {
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case 0x0: /* Even RD Data */ |
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case 0x8: |
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return ide_data_readw(&s->bus, 0); |
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/* TODO: 8-bit accesses */
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if (s->cycle)
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ret = s->io >> 8;
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else {
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s->io = ide_data_readw(&s->bus, 0);
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ret = s->io & 0xff;
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} |
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s->cycle = !s->cycle; |
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return ret;
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case 0x9: /* Odd RD Data */ |
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return s->io >> 8; |
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case 0xd: /* Error */ |
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return ide_ioport_read(&s->bus, 0x1); |
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case 0xe: /* Alternate Status */ |
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ifs = idebus_active_if(&s->bus); |
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if (ifs->bs)
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return ifs->status;
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else
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return 0; |
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case 0xf: /* Device Address */ |
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ifs = idebus_active_if(&s->bus); |
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return 0xc2 | ((~ifs->select << 2) & 0x3c); |
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default:
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return ide_ioport_read(&s->bus, at);
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} |
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return 0; |
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} |
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|
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static void md_common_write(void *opaque, uint32_t at, uint16_t value) |
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{
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MicroDriveState *s = (MicroDriveState *) opaque; |
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at -= s->io_base; |
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|
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switch (s->opt & OPT_MODE) {
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case OPT_MODE_MMAP:
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if ((at & ~0x3ff) == 0x400) |
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at = 0;
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break;
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case OPT_MODE_IOMAP16:
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at &= 0xf;
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break;
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case OPT_MODE_IOMAP1:
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if ((at & ~0xf) == 0x3f0) |
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at -= 0x3e8;
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else if ((at & ~0xf) == 0x1f0) |
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at -= 0x1f0;
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break;
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case OPT_MODE_IOMAP2:
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if ((at & ~0xf) == 0x370) |
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at -= 0x368;
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else if ((at & ~0xf) == 0x170) |
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at -= 0x170;
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} |
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switch (at) {
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case 0x0: /* Even WR Data */ |
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case 0x8: |
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ide_data_writew(&s->bus, 0, value);
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break;
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|
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/* TODO: 8-bit accesses */
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if (s->cycle)
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ide_data_writew(&s->bus, 0, s->io | (value << 8)); |
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else
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s->io = value & 0xff;
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s->cycle = !s->cycle; |
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break;
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case 0x9: |
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s->io = value & 0xff;
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s->cycle = !s->cycle; |
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break;
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case 0xd: /* Features */ |
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ide_ioport_write(&s->bus, 0x1, value);
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break;
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case 0xe: /* Device Control */ |
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s->ctrl = value; |
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if (value & CTRL_SRST)
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md_reset(s); |
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md_interrupt_update(s); |
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break;
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default:
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if (s->stat & STAT_PWRDWN) {
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s->pins |= PINS_CRDY; |
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s->stat &= ~STAT_PWRDWN; |
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} |
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ide_ioport_write(&s->bus, at, value); |
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} |
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} |
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|
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static void md_save(QEMUFile *f, void *opaque) |
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{
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MicroDriveState *s = (MicroDriveState *) opaque; |
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int i;
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|
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qemu_put_8s(f, &s->opt); |
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qemu_put_8s(f, &s->stat); |
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qemu_put_8s(f, &s->pins); |
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|
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qemu_put_8s(f, &s->ctrl); |
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qemu_put_be16s(f, &s->io); |
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qemu_put_byte(f, s->cycle); |
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idebus_save(f, &s->bus); |
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for (i = 0; i < 2; i ++) |
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ide_save(f, &s->bus.ifs[i]); |
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} |
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|
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static int md_load(QEMUFile *f, void *opaque, int version_id) |
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{
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MicroDriveState *s = (MicroDriveState *) opaque; |
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int i;
|
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|
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if (version_id != 0 && version_id != 3) |
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return -EINVAL;
|
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|
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qemu_get_8s(f, &s->opt); |
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qemu_get_8s(f, &s->stat); |
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qemu_get_8s(f, &s->pins); |
| 333 |
|
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qemu_get_8s(f, &s->ctrl); |
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qemu_get_be16s(f, &s->io); |
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s->cycle = qemu_get_byte(f); |
| 337 |
|
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idebus_load(f, &s->bus, version_id); |
| 339 |
|
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for (i = 0; i < 2; i ++) |
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ide_load(f, &s->bus.ifs[i], version_id); |
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|
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return 0; |
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} |
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|
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static const uint8_t dscm1xxxx_cis[0x14a] = { |
| 347 |
[0x000] = CISTPL_DEVICE, /* 5V Device Information */ |
| 348 |
[0x002] = 0x03, /* Tuple length = 4 bytes */ |
| 349 |
[0x004] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */ |
| 350 |
[0x006] = 0x01, /* Size = 2K bytes */ |
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[0x008] = CISTPL_ENDMARK,
|
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|
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[0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */ |
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[0x00c] = 0x04, /* Tuple length = 4 byest */ |
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[0x00e] = 0x03, /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */ |
| 356 |
[0x010] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */ |
| 357 |
[0x012] = 0x01, /* Size = 2K bytes */ |
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[0x014] = CISTPL_ENDMARK,
|
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|
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[0x016] = CISTPL_JEDEC_C, /* JEDEC ID */ |
| 361 |
[0x018] = 0x02, /* Tuple length = 2 bytes */ |
| 362 |
[0x01a] = 0xdf, /* PC Card ATA with no Vpp required */ |
| 363 |
[0x01c] = 0x01, |
| 364 |
|
| 365 |
[0x01e] = CISTPL_MANFID, /* Manufacture ID */ |
| 366 |
[0x020] = 0x04, /* Tuple length = 4 bytes */ |
| 367 |
[0x022] = 0xa4, /* TPLMID_MANF = 00a4 (IBM) */ |
| 368 |
[0x024] = 0x00, |
| 369 |
[0x026] = 0x00, /* PLMID_CARD = 0000 */ |
| 370 |
[0x028] = 0x00, |
| 371 |
|
| 372 |
[0x02a] = CISTPL_VERS_1, /* Level 1 Version */ |
| 373 |
[0x02c] = 0x12, /* Tuple length = 23 bytes */ |
| 374 |
[0x02e] = 0x04, /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */ |
| 375 |
[0x030] = 0x01, /* Minor Version = 1 */ |
| 376 |
[0x032] = 'I', |
| 377 |
[0x034] = 'B', |
| 378 |
[0x036] = 'M', |
| 379 |
[0x038] = 0x00, |
| 380 |
[0x03a] = 'm', |
| 381 |
[0x03c] = 'i', |
| 382 |
[0x03e] = 'c', |
| 383 |
[0x040] = 'r', |
| 384 |
[0x042] = 'o', |
| 385 |
[0x044] = 'd', |
| 386 |
[0x046] = 'r', |
| 387 |
[0x048] = 'i', |
| 388 |
[0x04a] = 'v', |
| 389 |
[0x04c] = 'e', |
| 390 |
[0x04e] = 0x00, |
| 391 |
[0x050] = CISTPL_ENDMARK,
|
| 392 |
|
| 393 |
[0x052] = CISTPL_FUNCID, /* Function ID */ |
| 394 |
[0x054] = 0x02, /* Tuple length = 2 bytes */ |
| 395 |
[0x056] = 0x04, /* TPLFID_FUNCTION = Fixed Disk */ |
| 396 |
[0x058] = 0x01, /* TPLFID_SYSINIT: POST = 1, ROM = 0 */ |
| 397 |
|
| 398 |
[0x05a] = CISTPL_FUNCE, /* Function Extension */ |
| 399 |
[0x05c] = 0x02, /* Tuple length = 2 bytes */ |
| 400 |
[0x05e] = 0x01, /* TPLFE_TYPE = Disk Device Interface */ |
| 401 |
[0x060] = 0x01, /* TPLFE_DATA = PC Card ATA Interface */ |
| 402 |
|
| 403 |
[0x062] = CISTPL_FUNCE, /* Function Extension */ |
| 404 |
[0x064] = 0x03, /* Tuple length = 3 bytes */ |
| 405 |
[0x066] = 0x02, /* TPLFE_TYPE = Basic PC Card ATA Interface */ |
| 406 |
[0x068] = 0x08, /* TPLFE_DATA: Rotating, Unique, Single */ |
| 407 |
[0x06a] = 0x0f, /* TPLFE_DATA: Sleep, Standby, Idle, Auto */ |
| 408 |
|
| 409 |
[0x06c] = CISTPL_CONFIG, /* Configuration */ |
| 410 |
[0x06e] = 0x05, /* Tuple length = 5 bytes */ |
| 411 |
[0x070] = 0x01, /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */ |
| 412 |
[0x072] = 0x07, /* TPCC_LAST = 7 */ |
| 413 |
[0x074] = 0x00, /* TPCC_RADR = 0200 */ |
| 414 |
[0x076] = 0x02, |
| 415 |
[0x078] = 0x0f, /* TPCC_RMSK = 200, 202, 204, 206 */ |
| 416 |
|
| 417 |
[0x07a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
| 418 |
[0x07c] = 0x0b, /* Tuple length = 11 bytes */ |
| 419 |
[0x07e] = 0xc0, /* TPCE_INDX = Memory Mode, Default, Iface */ |
| 420 |
[0x080] = 0xc0, /* TPCE_IF = Memory, no BVDs, no WP, READY */ |
| 421 |
[0x082] = 0xa1, /* TPCE_FS = Vcc only, no I/O, Memory, Misc */ |
| 422 |
[0x084] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ |
| 423 |
[0x086] = 0x55, /* NomV: 5.0 V */ |
| 424 |
[0x088] = 0x4d, /* MinV: 4.5 V */ |
| 425 |
[0x08a] = 0x5d, /* MaxV: 5.5 V */ |
| 426 |
[0x08c] = 0x4e, /* Peakl: 450 mA */ |
| 427 |
[0x08e] = 0x08, /* TPCE_MS = 1 window, 1 byte, Host address */ |
| 428 |
[0x090] = 0x00, /* Window descriptor: Window length = 0 */ |
| 429 |
[0x092] = 0x20, /* TPCE_MI: support power down mode, RW */ |
| 430 |
|
| 431 |
[0x094] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
| 432 |
[0x096] = 0x06, /* Tuple length = 6 bytes */ |
| 433 |
[0x098] = 0x00, /* TPCE_INDX = Memory Mode, no Default */ |
| 434 |
[0x09a] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ |
| 435 |
[0x09c] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ |
| 436 |
[0x09e] = 0xb5, /* NomV: 3.3 V */ |
| 437 |
[0x0a0] = 0x1e, |
| 438 |
[0x0a2] = 0x3e, /* Peakl: 350 mA */ |
| 439 |
|
| 440 |
[0x0a4] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
| 441 |
[0x0a6] = 0x0d, /* Tuple length = 13 bytes */ |
| 442 |
[0x0a8] = 0xc1, /* TPCE_INDX = I/O and Memory Mode, Default */ |
| 443 |
[0x0aa] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */ |
| 444 |
[0x0ac] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */ |
| 445 |
[0x0ae] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ |
| 446 |
[0x0b0] = 0x55, /* NomV: 5.0 V */ |
| 447 |
[0x0b2] = 0x4d, /* MinV: 4.5 V */ |
| 448 |
[0x0b4] = 0x5d, /* MaxV: 5.5 V */ |
| 449 |
[0x0b6] = 0x4e, /* Peakl: 450 mA */ |
| 450 |
[0x0b8] = 0x64, /* TPCE_IO = 16-byte boundary, 16/8 accesses */ |
| 451 |
[0x0ba] = 0xf0, /* TPCE_IR = MASK, Level, Pulse, Share */ |
| 452 |
[0x0bc] = 0xff, /* IRQ0..IRQ7 supported */ |
| 453 |
[0x0be] = 0xff, /* IRQ8..IRQ15 supported */ |
| 454 |
[0x0c0] = 0x20, /* TPCE_MI = support power down mode */ |
| 455 |
|
| 456 |
[0x0c2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
| 457 |
[0x0c4] = 0x06, /* Tuple length = 6 bytes */ |
| 458 |
[0x0c6] = 0x01, /* TPCE_INDX = I/O and Memory Mode */ |
| 459 |
[0x0c8] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ |
| 460 |
[0x0ca] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ |
| 461 |
[0x0cc] = 0xb5, /* NomV: 3.3 V */ |
| 462 |
[0x0ce] = 0x1e, |
| 463 |
[0x0d0] = 0x3e, /* Peakl: 350 mA */ |
| 464 |
|
| 465 |
[0x0d2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
| 466 |
[0x0d4] = 0x12, /* Tuple length = 18 bytes */ |
| 467 |
[0x0d6] = 0xc2, /* TPCE_INDX = I/O Primary Mode */ |
| 468 |
[0x0d8] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */ |
| 469 |
[0x0da] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */ |
| 470 |
[0x0dc] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ |
| 471 |
[0x0de] = 0x55, /* NomV: 5.0 V */ |
| 472 |
[0x0e0] = 0x4d, /* MinV: 4.5 V */ |
| 473 |
[0x0e2] = 0x5d, /* MaxV: 5.5 V */ |
| 474 |
[0x0e4] = 0x4e, /* Peakl: 450 mA */ |
| 475 |
[0x0e6] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */ |
| 476 |
[0x0e8] = 0x61, /* Range: 2 fields, 2 bytes addr, 1 byte len */ |
| 477 |
[0x0ea] = 0xf0, /* Field 1 address = 0x01f0 */ |
| 478 |
[0x0ec] = 0x01, |
| 479 |
[0x0ee] = 0x07, /* Address block length = 8 */ |
| 480 |
[0x0f0] = 0xf6, /* Field 2 address = 0x03f6 */ |
| 481 |
[0x0f2] = 0x03, |
| 482 |
[0x0f4] = 0x01, /* Address block length = 2 */ |
| 483 |
[0x0f6] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */ |
| 484 |
[0x0f8] = 0x20, /* TPCE_MI = support power down mode */ |
| 485 |
|
| 486 |
[0x0fa] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
| 487 |
[0x0fc] = 0x06, /* Tuple length = 6 bytes */ |
| 488 |
[0x0fe] = 0x02, /* TPCE_INDX = I/O Primary Mode, no Default */ |
| 489 |
[0x100] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ |
| 490 |
[0x102] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ |
| 491 |
[0x104] = 0xb5, /* NomV: 3.3 V */ |
| 492 |
[0x106] = 0x1e, |
| 493 |
[0x108] = 0x3e, /* Peakl: 350 mA */ |
| 494 |
|
| 495 |
[0x10a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
| 496 |
[0x10c] = 0x12, /* Tuple length = 18 bytes */ |
| 497 |
[0x10e] = 0xc3, /* TPCE_INDX = I/O Secondary Mode, Default */ |
| 498 |
[0x110] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */ |
| 499 |
[0x112] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */ |
| 500 |
[0x114] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */ |
| 501 |
[0x116] = 0x55, /* NomV: 5.0 V */ |
| 502 |
[0x118] = 0x4d, /* MinV: 4.5 V */ |
| 503 |
[0x11a] = 0x5d, /* MaxV: 5.5 V */ |
| 504 |
[0x11c] = 0x4e, /* Peakl: 450 mA */ |
| 505 |
[0x11e] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */ |
| 506 |
[0x120] = 0x61, /* Range: 2 fields, 2 byte addr, 1 byte len */ |
| 507 |
[0x122] = 0x70, /* Field 1 address = 0x0170 */ |
| 508 |
[0x124] = 0x01, |
| 509 |
[0x126] = 0x07, /* Address block length = 8 */ |
| 510 |
[0x128] = 0x76, /* Field 2 address = 0x0376 */ |
| 511 |
[0x12a] = 0x03, |
| 512 |
[0x12c] = 0x01, /* Address block length = 2 */ |
| 513 |
[0x12e] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */ |
| 514 |
[0x130] = 0x20, /* TPCE_MI = support power down mode */ |
| 515 |
|
| 516 |
[0x132] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */ |
| 517 |
[0x134] = 0x06, /* Tuple length = 6 bytes */ |
| 518 |
[0x136] = 0x03, /* TPCE_INDX = I/O Secondary Mode */ |
| 519 |
[0x138] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */ |
| 520 |
[0x13a] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */ |
| 521 |
[0x13c] = 0xb5, /* NomV: 3.3 V */ |
| 522 |
[0x13e] = 0x1e, |
| 523 |
[0x140] = 0x3e, /* Peakl: 350 mA */ |
| 524 |
|
| 525 |
[0x142] = CISTPL_NO_LINK, /* No Link */ |
| 526 |
[0x144] = 0x00, /* Tuple length = 0 bytes */ |
| 527 |
|
| 528 |
[0x146] = CISTPL_END, /* Tuple End */ |
| 529 |
}; |
| 530 |
|
| 531 |
static int dscm1xxxx_attach(void *opaque) |
| 532 |
{
|
| 533 |
MicroDriveState *md = (MicroDriveState *) opaque; |
| 534 |
md->card.attr_read = md_attr_read; |
| 535 |
md->card.attr_write = md_attr_write; |
| 536 |
md->card.common_read = md_common_read; |
| 537 |
md->card.common_write = md_common_write; |
| 538 |
md->card.io_read = md_common_read; |
| 539 |
md->card.io_write = md_common_write; |
| 540 |
|
| 541 |
md->attr_base = md->card.cis[0x74] | (md->card.cis[0x76] << 8); |
| 542 |
md->io_base = 0x0;
|
| 543 |
|
| 544 |
md_reset(md); |
| 545 |
md_interrupt_update(md); |
| 546 |
|
| 547 |
md->card.slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
|
| 548 |
return 0; |
| 549 |
} |
| 550 |
|
| 551 |
static int dscm1xxxx_detach(void *opaque) |
| 552 |
{
|
| 553 |
MicroDriveState *md = (MicroDriveState *) opaque; |
| 554 |
md_reset(md); |
| 555 |
return 0; |
| 556 |
} |
| 557 |
|
| 558 |
PCMCIACardState *dscm1xxxx_init(DriveInfo *bdrv) |
| 559 |
{
|
| 560 |
MicroDriveState *md = (MicroDriveState *) qemu_mallocz(sizeof(MicroDriveState));
|
| 561 |
md->card.state = md; |
| 562 |
md->card.attach = dscm1xxxx_attach; |
| 563 |
md->card.detach = dscm1xxxx_detach; |
| 564 |
md->card.cis = dscm1xxxx_cis; |
| 565 |
md->card.cis_len = sizeof(dscm1xxxx_cis);
|
| 566 |
|
| 567 |
ide_init2(&md->bus, bdrv, NULL, qemu_allocate_irqs(md_set_irq, md, 1)[0]); |
| 568 |
md->bus.ifs[0].is_cf = 1; |
| 569 |
md->bus.ifs[0].mdata_size = METADATA_SIZE;
|
| 570 |
md->bus.ifs[0].mdata_storage = (uint8_t *) qemu_mallocz(METADATA_SIZE);
|
| 571 |
|
| 572 |
register_savevm("microdrive", -1, 3, md_save, md_load, md); |
| 573 |
|
| 574 |
return &md->card;
|
| 575 |
} |