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/*
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* MIPS emulation micro-operations for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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* Copyright (c) 2006 Marius Groeger (FPU operations)
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "config.h" |
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#include "exec.h" |
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|
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#ifndef CALL_FROM_TB0
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#define CALL_FROM_TB0(func) func()
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#endif
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#ifndef CALL_FROM_TB1
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#define CALL_FROM_TB1(func, arg0) func(arg0)
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#endif
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#ifndef CALL_FROM_TB1_CONST16
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#define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0)
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#endif
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#ifndef CALL_FROM_TB2
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#define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1)
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#endif
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#ifndef CALL_FROM_TB2_CONST16
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#define CALL_FROM_TB2_CONST16(func, arg0, arg1) \
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CALL_FROM_TB2(func, arg0, arg1) |
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#endif
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#ifndef CALL_FROM_TB3
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#define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2)
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#endif
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#ifndef CALL_FROM_TB4
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#define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
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func(arg0, arg1, arg2, arg3) |
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#endif
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#define REG 1 |
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#include "op_template.c" |
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#undef REG
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#define REG 2 |
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#include "op_template.c" |
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#undef REG
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#define REG 3 |
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#include "op_template.c" |
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#undef REG
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#define REG 4 |
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#include "op_template.c" |
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#undef REG
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#define REG 5 |
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#include "op_template.c" |
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#undef REG
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#define REG 6 |
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#include "op_template.c" |
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#undef REG
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#define REG 7 |
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#include "op_template.c" |
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#undef REG
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#define REG 8 |
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#include "op_template.c" |
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#undef REG
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#define REG 9 |
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#include "op_template.c" |
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#undef REG
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#define REG 10 |
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#include "op_template.c" |
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#undef REG
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#define REG 11 |
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#include "op_template.c" |
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#undef REG
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#define REG 12 |
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#include "op_template.c" |
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#undef REG
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#define REG 13 |
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#include "op_template.c" |
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#undef REG
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#define REG 14 |
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#include "op_template.c" |
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#undef REG
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#define REG 15 |
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#include "op_template.c" |
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#undef REG
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#define REG 16 |
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#include "op_template.c" |
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#undef REG
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#define REG 17 |
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#include "op_template.c" |
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#undef REG
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#define REG 18 |
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#include "op_template.c" |
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#undef REG
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#define REG 19 |
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#include "op_template.c" |
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#undef REG
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#define REG 20 |
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#include "op_template.c" |
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#undef REG
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#define REG 21 |
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#include "op_template.c" |
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#undef REG
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#define REG 22 |
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#include "op_template.c" |
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#undef REG
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#define REG 23 |
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#include "op_template.c" |
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#undef REG
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#define REG 24 |
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#include "op_template.c" |
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#undef REG
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#define REG 25 |
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#include "op_template.c" |
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#undef REG
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#define REG 26 |
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#include "op_template.c" |
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#undef REG
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#define REG 27 |
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#include "op_template.c" |
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#undef REG
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#define REG 28 |
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#include "op_template.c" |
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#undef REG
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#define REG 29 |
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#include "op_template.c" |
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#undef REG
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#define REG 30 |
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#include "op_template.c" |
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#undef REG
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#define REG 31 |
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#include "op_template.c" |
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#undef REG
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#define TN
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#include "op_template.c" |
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#undef TN
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#define FREG 0 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 1 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 2 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 3 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 4 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 5 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 6 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 7 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 8 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 9 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 10 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 11 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 12 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 13 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 14 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 15 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 16 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 17 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 18 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 19 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 20 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 21 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 22 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 23 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 24 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 25 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 26 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 27 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 28 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 29 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 30 |
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#include "fop_template.c" |
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#undef FREG
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#define FREG 31 |
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#include "fop_template.c" |
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#undef FREG
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#define FTN
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#include "fop_template.c" |
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#undef FTN
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void op_dup_T0 (void) |
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{ |
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T2 = T0; |
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RETURN(); |
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} |
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void op_load_HI (void) |
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{ |
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T0 = env->HI; |
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RETURN(); |
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} |
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void op_store_HI (void) |
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{ |
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env->HI = T0; |
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RETURN(); |
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} |
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void op_load_LO (void) |
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{ |
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T0 = env->LO; |
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RETURN(); |
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} |
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void op_store_LO (void) |
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{ |
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env->LO = T0; |
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RETURN(); |
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} |
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/* Load and store */
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#define MEMSUFFIX _raw
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#include "op_mem.c" |
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#undef MEMSUFFIX
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_mem.c" |
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#undef MEMSUFFIX
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#define MEMSUFFIX _kernel
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#include "op_mem.c" |
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#undef MEMSUFFIX
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#endif
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/* Addresses computation */
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void op_addr_add (void) |
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{ |
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/* For compatibility with 32-bit code, data reference in user mode
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with Status_UX = 0 should be casted to 32-bit and sign extended.
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See the MIPS64 PRA manual, section 4.10. */
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#ifdef TARGET_MIPS64
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if ((env->CP0_Status & (1 << CP0St_UM)) && |
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!(env->CP0_Status & (1 << CP0St_UX)))
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T0 = (int64_t)(int32_t)(T0 + T1); |
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else
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#endif
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T0 += T1; |
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RETURN(); |
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} |
307 |
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/* Arithmetic */
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void op_add (void) |
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{ |
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T0 = (int32_t)((int32_t)T0 + (int32_t)T1); |
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RETURN(); |
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} |
314 |
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void op_addo (void) |
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{ |
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target_ulong tmp; |
318 |
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tmp = (int32_t)T0; |
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T0 = (int32_t)T0 + (int32_t)T1; |
321 |
if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) { |
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/* operands of same sign, result different sign */
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CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
324 |
} |
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T0 = (int32_t)T0; |
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RETURN(); |
327 |
} |
328 |
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void op_sub (void) |
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{ |
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T0 = (int32_t)((int32_t)T0 - (int32_t)T1); |
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RETURN(); |
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} |
334 |
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void op_subo (void) |
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{ |
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target_ulong tmp; |
338 |
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tmp = (int32_t)T0; |
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T0 = (int32_t)T0 - (int32_t)T1; |
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if (((tmp ^ T1) & (tmp ^ T0)) >> 31) { |
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/* operands of different sign, first operand and result different sign */
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CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
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} |
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T0 = (int32_t)T0; |
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RETURN(); |
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} |
348 |
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void op_mul (void) |
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{ |
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T0 = (int32_t)((int32_t)T0 * (int32_t)T1); |
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RETURN(); |
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} |
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#if HOST_LONG_BITS < 64 |
356 |
void op_div (void) |
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{ |
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CALL_FROM_TB0(do_div); |
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RETURN(); |
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} |
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#else
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void op_div (void) |
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{ |
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if (T1 != 0) { |
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env->LO = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1); |
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env->HI = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1); |
367 |
} |
368 |
RETURN(); |
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} |
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#endif
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371 |
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372 |
void op_divu (void) |
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{ |
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if (T1 != 0) { |
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env->LO = (int32_t)((uint32_t)T0 / (uint32_t)T1); |
376 |
env->HI = (int32_t)((uint32_t)T0 % (uint32_t)T1); |
377 |
} |
378 |
RETURN(); |
379 |
} |
380 |
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381 |
#ifdef TARGET_MIPS64
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382 |
/* Arithmetic */
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383 |
void op_dadd (void) |
384 |
{ |
385 |
T0 += T1; |
386 |
RETURN(); |
387 |
} |
388 |
|
389 |
void op_daddo (void) |
390 |
{ |
391 |
target_long tmp; |
392 |
|
393 |
tmp = T0; |
394 |
T0 += T1; |
395 |
if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) { |
396 |
/* operands of same sign, result different sign */
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397 |
CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
398 |
} |
399 |
RETURN(); |
400 |
} |
401 |
|
402 |
void op_dsub (void) |
403 |
{ |
404 |
T0 -= T1; |
405 |
RETURN(); |
406 |
} |
407 |
|
408 |
void op_dsubo (void) |
409 |
{ |
410 |
target_long tmp; |
411 |
|
412 |
tmp = T0; |
413 |
T0 = (int64_t)T0 - (int64_t)T1; |
414 |
if (((tmp ^ T1) & (tmp ^ T0)) >> 63) { |
415 |
/* operands of different sign, first operand and result different sign */
|
416 |
CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
417 |
} |
418 |
RETURN(); |
419 |
} |
420 |
|
421 |
void op_dmul (void) |
422 |
{ |
423 |
T0 = (int64_t)T0 * (int64_t)T1; |
424 |
RETURN(); |
425 |
} |
426 |
|
427 |
/* Those might call libgcc functions. */
|
428 |
void op_ddiv (void) |
429 |
{ |
430 |
do_ddiv(); |
431 |
RETURN(); |
432 |
} |
433 |
|
434 |
#if TARGET_LONG_BITS > HOST_LONG_BITS
|
435 |
void op_ddivu (void) |
436 |
{ |
437 |
do_ddivu(); |
438 |
RETURN(); |
439 |
} |
440 |
#else
|
441 |
void op_ddivu (void) |
442 |
{ |
443 |
if (T1 != 0) { |
444 |
env->LO = T0 / T1; |
445 |
env->HI = T0 % T1; |
446 |
} |
447 |
RETURN(); |
448 |
} |
449 |
#endif
|
450 |
#endif /* TARGET_MIPS64 */ |
451 |
|
452 |
/* Logical */
|
453 |
void op_and (void) |
454 |
{ |
455 |
T0 &= T1; |
456 |
RETURN(); |
457 |
} |
458 |
|
459 |
void op_nor (void) |
460 |
{ |
461 |
T0 = ~(T0 | T1); |
462 |
RETURN(); |
463 |
} |
464 |
|
465 |
void op_or (void) |
466 |
{ |
467 |
T0 |= T1; |
468 |
RETURN(); |
469 |
} |
470 |
|
471 |
void op_xor (void) |
472 |
{ |
473 |
T0 ^= T1; |
474 |
RETURN(); |
475 |
} |
476 |
|
477 |
void op_sll (void) |
478 |
{ |
479 |
T0 = (int32_t)((uint32_t)T0 << T1); |
480 |
RETURN(); |
481 |
} |
482 |
|
483 |
void op_sra (void) |
484 |
{ |
485 |
T0 = (int32_t)((int32_t)T0 >> T1); |
486 |
RETURN(); |
487 |
} |
488 |
|
489 |
void op_srl (void) |
490 |
{ |
491 |
T0 = (int32_t)((uint32_t)T0 >> T1); |
492 |
RETURN(); |
493 |
} |
494 |
|
495 |
void op_rotr (void) |
496 |
{ |
497 |
target_ulong tmp; |
498 |
|
499 |
if (T1) {
|
500 |
tmp = (int32_t)((uint32_t)T0 << (0x20 - T1));
|
501 |
T0 = (int32_t)((uint32_t)T0 >> T1) | tmp; |
502 |
} |
503 |
RETURN(); |
504 |
} |
505 |
|
506 |
void op_sllv (void) |
507 |
{ |
508 |
T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
|
509 |
RETURN(); |
510 |
} |
511 |
|
512 |
void op_srav (void) |
513 |
{ |
514 |
T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
|
515 |
RETURN(); |
516 |
} |
517 |
|
518 |
void op_srlv (void) |
519 |
{ |
520 |
T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
|
521 |
RETURN(); |
522 |
} |
523 |
|
524 |
void op_rotrv (void) |
525 |
{ |
526 |
target_ulong tmp; |
527 |
|
528 |
T0 &= 0x1F;
|
529 |
if (T0) {
|
530 |
tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
|
531 |
T0 = (int32_t)((uint32_t)T1 >> T0) | tmp; |
532 |
} else
|
533 |
T0 = T1; |
534 |
RETURN(); |
535 |
} |
536 |
|
537 |
void op_clo (void) |
538 |
{ |
539 |
int n;
|
540 |
|
541 |
if (T0 == ~((target_ulong)0)) { |
542 |
T0 = 32;
|
543 |
} else {
|
544 |
for (n = 0; n < 32; n++) { |
545 |
if (!(T0 & (1 << 31))) |
546 |
break;
|
547 |
T0 = T0 << 1;
|
548 |
} |
549 |
T0 = n; |
550 |
} |
551 |
RETURN(); |
552 |
} |
553 |
|
554 |
void op_clz (void) |
555 |
{ |
556 |
int n;
|
557 |
|
558 |
if (T0 == 0) { |
559 |
T0 = 32;
|
560 |
} else {
|
561 |
for (n = 0; n < 32; n++) { |
562 |
if (T0 & (1 << 31)) |
563 |
break;
|
564 |
T0 = T0 << 1;
|
565 |
} |
566 |
T0 = n; |
567 |
} |
568 |
RETURN(); |
569 |
} |
570 |
|
571 |
#ifdef TARGET_MIPS64
|
572 |
|
573 |
#if TARGET_LONG_BITS > HOST_LONG_BITS
|
574 |
/* Those might call libgcc functions. */
|
575 |
void op_dsll (void) |
576 |
{ |
577 |
CALL_FROM_TB0(do_dsll); |
578 |
RETURN(); |
579 |
} |
580 |
|
581 |
void op_dsll32 (void) |
582 |
{ |
583 |
CALL_FROM_TB0(do_dsll32); |
584 |
RETURN(); |
585 |
} |
586 |
|
587 |
void op_dsra (void) |
588 |
{ |
589 |
CALL_FROM_TB0(do_dsra); |
590 |
RETURN(); |
591 |
} |
592 |
|
593 |
void op_dsra32 (void) |
594 |
{ |
595 |
CALL_FROM_TB0(do_dsra32); |
596 |
RETURN(); |
597 |
} |
598 |
|
599 |
void op_dsrl (void) |
600 |
{ |
601 |
CALL_FROM_TB0(do_dsrl); |
602 |
RETURN(); |
603 |
} |
604 |
|
605 |
void op_dsrl32 (void) |
606 |
{ |
607 |
CALL_FROM_TB0(do_dsrl32); |
608 |
RETURN(); |
609 |
} |
610 |
|
611 |
void op_drotr (void) |
612 |
{ |
613 |
CALL_FROM_TB0(do_drotr); |
614 |
RETURN(); |
615 |
} |
616 |
|
617 |
void op_drotr32 (void) |
618 |
{ |
619 |
CALL_FROM_TB0(do_drotr32); |
620 |
RETURN(); |
621 |
} |
622 |
|
623 |
void op_dsllv (void) |
624 |
{ |
625 |
CALL_FROM_TB0(do_dsllv); |
626 |
RETURN(); |
627 |
} |
628 |
|
629 |
void op_dsrav (void) |
630 |
{ |
631 |
CALL_FROM_TB0(do_dsrav); |
632 |
RETURN(); |
633 |
} |
634 |
|
635 |
void op_dsrlv (void) |
636 |
{ |
637 |
CALL_FROM_TB0(do_dsrlv); |
638 |
RETURN(); |
639 |
} |
640 |
|
641 |
void op_drotrv (void) |
642 |
{ |
643 |
CALL_FROM_TB0(do_drotrv); |
644 |
RETURN(); |
645 |
} |
646 |
|
647 |
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
648 |
|
649 |
void op_dsll (void) |
650 |
{ |
651 |
T0 = T0 << T1; |
652 |
RETURN(); |
653 |
} |
654 |
|
655 |
void op_dsll32 (void) |
656 |
{ |
657 |
T0 = T0 << (T1 + 32);
|
658 |
RETURN(); |
659 |
} |
660 |
|
661 |
void op_dsra (void) |
662 |
{ |
663 |
T0 = (int64_t)T0 >> T1; |
664 |
RETURN(); |
665 |
} |
666 |
|
667 |
void op_dsra32 (void) |
668 |
{ |
669 |
T0 = (int64_t)T0 >> (T1 + 32);
|
670 |
RETURN(); |
671 |
} |
672 |
|
673 |
void op_dsrl (void) |
674 |
{ |
675 |
T0 = T0 >> T1; |
676 |
RETURN(); |
677 |
} |
678 |
|
679 |
void op_dsrl32 (void) |
680 |
{ |
681 |
T0 = T0 >> (T1 + 32);
|
682 |
RETURN(); |
683 |
} |
684 |
|
685 |
void op_drotr (void) |
686 |
{ |
687 |
target_ulong tmp; |
688 |
|
689 |
if (T1) {
|
690 |
tmp = T0 << (0x40 - T1);
|
691 |
T0 = (T0 >> T1) | tmp; |
692 |
} |
693 |
RETURN(); |
694 |
} |
695 |
|
696 |
void op_drotr32 (void) |
697 |
{ |
698 |
target_ulong tmp; |
699 |
|
700 |
if (T1) {
|
701 |
tmp = T0 << (0x40 - (32 + T1)); |
702 |
T0 = (T0 >> (32 + T1)) | tmp;
|
703 |
} |
704 |
RETURN(); |
705 |
} |
706 |
|
707 |
void op_dsllv (void) |
708 |
{ |
709 |
T0 = T1 << (T0 & 0x3F);
|
710 |
RETURN(); |
711 |
} |
712 |
|
713 |
void op_dsrav (void) |
714 |
{ |
715 |
T0 = (int64_t)T1 >> (T0 & 0x3F);
|
716 |
RETURN(); |
717 |
} |
718 |
|
719 |
void op_dsrlv (void) |
720 |
{ |
721 |
T0 = T1 >> (T0 & 0x3F);
|
722 |
RETURN(); |
723 |
} |
724 |
|
725 |
void op_drotrv (void) |
726 |
{ |
727 |
target_ulong tmp; |
728 |
|
729 |
T0 &= 0x3F;
|
730 |
if (T0) {
|
731 |
tmp = T1 << (0x40 - T0);
|
732 |
T0 = (T1 >> T0) | tmp; |
733 |
} else
|
734 |
T0 = T1; |
735 |
RETURN(); |
736 |
} |
737 |
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
738 |
|
739 |
void op_dclo (void) |
740 |
{ |
741 |
int n;
|
742 |
|
743 |
if (T0 == ~((target_ulong)0)) { |
744 |
T0 = 64;
|
745 |
} else {
|
746 |
for (n = 0; n < 64; n++) { |
747 |
if (!(T0 & (1ULL << 63))) |
748 |
break;
|
749 |
T0 = T0 << 1;
|
750 |
} |
751 |
T0 = n; |
752 |
} |
753 |
RETURN(); |
754 |
} |
755 |
|
756 |
void op_dclz (void) |
757 |
{ |
758 |
int n;
|
759 |
|
760 |
if (T0 == 0) { |
761 |
T0 = 64;
|
762 |
} else {
|
763 |
for (n = 0; n < 64; n++) { |
764 |
if (T0 & (1ULL << 63)) |
765 |
break;
|
766 |
T0 = T0 << 1;
|
767 |
} |
768 |
T0 = n; |
769 |
} |
770 |
RETURN(); |
771 |
} |
772 |
#endif
|
773 |
|
774 |
/* 64 bits arithmetic */
|
775 |
#if TARGET_LONG_BITS > HOST_LONG_BITS
|
776 |
void op_mult (void) |
777 |
{ |
778 |
CALL_FROM_TB0(do_mult); |
779 |
RETURN(); |
780 |
} |
781 |
|
782 |
void op_multu (void) |
783 |
{ |
784 |
CALL_FROM_TB0(do_multu); |
785 |
RETURN(); |
786 |
} |
787 |
|
788 |
void op_madd (void) |
789 |
{ |
790 |
CALL_FROM_TB0(do_madd); |
791 |
RETURN(); |
792 |
} |
793 |
|
794 |
void op_maddu (void) |
795 |
{ |
796 |
CALL_FROM_TB0(do_maddu); |
797 |
RETURN(); |
798 |
} |
799 |
|
800 |
void op_msub (void) |
801 |
{ |
802 |
CALL_FROM_TB0(do_msub); |
803 |
RETURN(); |
804 |
} |
805 |
|
806 |
void op_msubu (void) |
807 |
{ |
808 |
CALL_FROM_TB0(do_msubu); |
809 |
RETURN(); |
810 |
} |
811 |
|
812 |
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
813 |
|
814 |
static inline uint64_t get_HILO (void) |
815 |
{ |
816 |
return ((uint64_t)env->HI << 32) | ((uint64_t)(uint32_t)env->LO); |
817 |
} |
818 |
|
819 |
static inline void set_HILO (uint64_t HILO) |
820 |
{ |
821 |
env->LO = (int32_t)(HILO & 0xFFFFFFFF);
|
822 |
env->HI = (int32_t)(HILO >> 32);
|
823 |
} |
824 |
|
825 |
void op_mult (void) |
826 |
{ |
827 |
set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
828 |
RETURN(); |
829 |
} |
830 |
|
831 |
void op_multu (void) |
832 |
{ |
833 |
set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
834 |
RETURN(); |
835 |
} |
836 |
|
837 |
void op_madd (void) |
838 |
{ |
839 |
int64_t tmp; |
840 |
|
841 |
tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
842 |
set_HILO((int64_t)get_HILO() + tmp); |
843 |
RETURN(); |
844 |
} |
845 |
|
846 |
void op_maddu (void) |
847 |
{ |
848 |
uint64_t tmp; |
849 |
|
850 |
tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
851 |
set_HILO(get_HILO() + tmp); |
852 |
RETURN(); |
853 |
} |
854 |
|
855 |
void op_msub (void) |
856 |
{ |
857 |
int64_t tmp; |
858 |
|
859 |
tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
860 |
set_HILO((int64_t)get_HILO() - tmp); |
861 |
RETURN(); |
862 |
} |
863 |
|
864 |
void op_msubu (void) |
865 |
{ |
866 |
uint64_t tmp; |
867 |
|
868 |
tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
869 |
set_HILO(get_HILO() - tmp); |
870 |
RETURN(); |
871 |
} |
872 |
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
873 |
|
874 |
#ifdef TARGET_MIPS64
|
875 |
void op_dmult (void) |
876 |
{ |
877 |
CALL_FROM_TB4(muls64, &(env->HI), &(env->LO), T0, T1); |
878 |
RETURN(); |
879 |
} |
880 |
|
881 |
void op_dmultu (void) |
882 |
{ |
883 |
CALL_FROM_TB4(mulu64, &(env->HI), &(env->LO), T0, T1); |
884 |
RETURN(); |
885 |
} |
886 |
#endif
|
887 |
|
888 |
/* Conditional moves */
|
889 |
void op_movn (void) |
890 |
{ |
891 |
if (T1 != 0) |
892 |
env->gpr[PARAM1] = T0; |
893 |
RETURN(); |
894 |
} |
895 |
|
896 |
void op_movz (void) |
897 |
{ |
898 |
if (T1 == 0) |
899 |
env->gpr[PARAM1] = T0; |
900 |
RETURN(); |
901 |
} |
902 |
|
903 |
void op_movf (void) |
904 |
{ |
905 |
if (!(env->fcr31 & PARAM1))
|
906 |
T0 = T1; |
907 |
RETURN(); |
908 |
} |
909 |
|
910 |
void op_movt (void) |
911 |
{ |
912 |
if (env->fcr31 & PARAM1)
|
913 |
T0 = T1; |
914 |
RETURN(); |
915 |
} |
916 |
|
917 |
/* Tests */
|
918 |
#define OP_COND(name, cond) \
|
919 |
void glue(op_, name) (void) \ |
920 |
{ \ |
921 |
if (cond) { \
|
922 |
T0 = 1; \
|
923 |
} else { \
|
924 |
T0 = 0; \
|
925 |
} \ |
926 |
RETURN(); \ |
927 |
} |
928 |
|
929 |
OP_COND(eq, T0 == T1); |
930 |
OP_COND(ne, T0 != T1); |
931 |
OP_COND(ge, (target_long)T0 >= (target_long)T1); |
932 |
OP_COND(geu, T0 >= T1); |
933 |
OP_COND(lt, (target_long)T0 < (target_long)T1); |
934 |
OP_COND(ltu, T0 < T1); |
935 |
OP_COND(gez, (target_long)T0 >= 0);
|
936 |
OP_COND(gtz, (target_long)T0 > 0);
|
937 |
OP_COND(lez, (target_long)T0 <= 0);
|
938 |
OP_COND(ltz, (target_long)T0 < 0);
|
939 |
|
940 |
/* Branches */
|
941 |
void OPPROTO op_goto_tb0(void) |
942 |
{ |
943 |
GOTO_TB(op_goto_tb0, PARAM1, 0);
|
944 |
RETURN(); |
945 |
} |
946 |
|
947 |
void OPPROTO op_goto_tb1(void) |
948 |
{ |
949 |
GOTO_TB(op_goto_tb1, PARAM1, 1);
|
950 |
RETURN(); |
951 |
} |
952 |
|
953 |
/* Branch to register */
|
954 |
void op_save_breg_target (void) |
955 |
{ |
956 |
env->btarget = T2; |
957 |
RETURN(); |
958 |
} |
959 |
|
960 |
void op_restore_breg_target (void) |
961 |
{ |
962 |
T2 = env->btarget; |
963 |
RETURN(); |
964 |
} |
965 |
|
966 |
void op_breg (void) |
967 |
{ |
968 |
env->PC = T2; |
969 |
RETURN(); |
970 |
} |
971 |
|
972 |
void op_save_btarget (void) |
973 |
{ |
974 |
env->btarget = PARAM1; |
975 |
RETURN(); |
976 |
} |
977 |
|
978 |
/* Conditional branch */
|
979 |
void op_set_bcond (void) |
980 |
{ |
981 |
T2 = T0; |
982 |
RETURN(); |
983 |
} |
984 |
|
985 |
void op_save_bcond (void) |
986 |
{ |
987 |
env->bcond = T2; |
988 |
RETURN(); |
989 |
} |
990 |
|
991 |
void op_restore_bcond (void) |
992 |
{ |
993 |
T2 = env->bcond; |
994 |
RETURN(); |
995 |
} |
996 |
|
997 |
void op_jnz_T2 (void) |
998 |
{ |
999 |
if (T2)
|
1000 |
GOTO_LABEL_PARAM(1);
|
1001 |
RETURN(); |
1002 |
} |
1003 |
|
1004 |
void op_flush_icache_range(void) { |
1005 |
CALL_FROM_TB2(tlb_flush_page, env, T0 + T1); |
1006 |
RETURN(); |
1007 |
} |
1008 |
|
1009 |
void op_flush_icache_all(void) { |
1010 |
CALL_FROM_TB1(tb_flush, env); |
1011 |
RETURN(); |
1012 |
} |
1013 |
|
1014 |
/* CP0 functions */
|
1015 |
void op_mfc0_index (void) |
1016 |
{ |
1017 |
T0 = env->CP0_Index; |
1018 |
RETURN(); |
1019 |
} |
1020 |
|
1021 |
void op_mfc0_random (void) |
1022 |
{ |
1023 |
CALL_FROM_TB0(do_mfc0_random); |
1024 |
RETURN(); |
1025 |
} |
1026 |
|
1027 |
void op_mfc0_entrylo0 (void) |
1028 |
{ |
1029 |
T0 = (int32_t)env->CP0_EntryLo0; |
1030 |
RETURN(); |
1031 |
} |
1032 |
|
1033 |
void op_mfc0_entrylo1 (void) |
1034 |
{ |
1035 |
T0 = (int32_t)env->CP0_EntryLo1; |
1036 |
RETURN(); |
1037 |
} |
1038 |
|
1039 |
void op_mfc0_context (void) |
1040 |
{ |
1041 |
T0 = (int32_t)env->CP0_Context; |
1042 |
RETURN(); |
1043 |
} |
1044 |
|
1045 |
void op_mfc0_pagemask (void) |
1046 |
{ |
1047 |
T0 = env->CP0_PageMask; |
1048 |
RETURN(); |
1049 |
} |
1050 |
|
1051 |
void op_mfc0_pagegrain (void) |
1052 |
{ |
1053 |
T0 = env->CP0_PageGrain; |
1054 |
RETURN(); |
1055 |
} |
1056 |
|
1057 |
void op_mfc0_wired (void) |
1058 |
{ |
1059 |
T0 = env->CP0_Wired; |
1060 |
RETURN(); |
1061 |
} |
1062 |
|
1063 |
void op_mfc0_hwrena (void) |
1064 |
{ |
1065 |
T0 = env->CP0_HWREna; |
1066 |
RETURN(); |
1067 |
} |
1068 |
|
1069 |
void op_mfc0_badvaddr (void) |
1070 |
{ |
1071 |
T0 = (int32_t)env->CP0_BadVAddr; |
1072 |
RETURN(); |
1073 |
} |
1074 |
|
1075 |
void op_mfc0_count (void) |
1076 |
{ |
1077 |
CALL_FROM_TB0(do_mfc0_count); |
1078 |
RETURN(); |
1079 |
} |
1080 |
|
1081 |
void op_mfc0_entryhi (void) |
1082 |
{ |
1083 |
T0 = (int32_t)env->CP0_EntryHi; |
1084 |
RETURN(); |
1085 |
} |
1086 |
|
1087 |
void op_mfc0_compare (void) |
1088 |
{ |
1089 |
T0 = env->CP0_Compare; |
1090 |
RETURN(); |
1091 |
} |
1092 |
|
1093 |
void op_mfc0_status (void) |
1094 |
{ |
1095 |
T0 = env->CP0_Status; |
1096 |
RETURN(); |
1097 |
} |
1098 |
|
1099 |
void op_mfc0_intctl (void) |
1100 |
{ |
1101 |
T0 = env->CP0_IntCtl; |
1102 |
RETURN(); |
1103 |
} |
1104 |
|
1105 |
void op_mfc0_srsctl (void) |
1106 |
{ |
1107 |
T0 = env->CP0_SRSCtl; |
1108 |
RETURN(); |
1109 |
} |
1110 |
|
1111 |
void op_mfc0_srsmap (void) |
1112 |
{ |
1113 |
T0 = env->CP0_SRSMap; |
1114 |
RETURN(); |
1115 |
} |
1116 |
|
1117 |
void op_mfc0_cause (void) |
1118 |
{ |
1119 |
T0 = env->CP0_Cause; |
1120 |
RETURN(); |
1121 |
} |
1122 |
|
1123 |
void op_mfc0_epc (void) |
1124 |
{ |
1125 |
T0 = (int32_t)env->CP0_EPC; |
1126 |
RETURN(); |
1127 |
} |
1128 |
|
1129 |
void op_mfc0_prid (void) |
1130 |
{ |
1131 |
T0 = env->CP0_PRid; |
1132 |
RETURN(); |
1133 |
} |
1134 |
|
1135 |
void op_mfc0_ebase (void) |
1136 |
{ |
1137 |
T0 = env->CP0_EBase; |
1138 |
RETURN(); |
1139 |
} |
1140 |
|
1141 |
void op_mfc0_config0 (void) |
1142 |
{ |
1143 |
T0 = env->CP0_Config0; |
1144 |
RETURN(); |
1145 |
} |
1146 |
|
1147 |
void op_mfc0_config1 (void) |
1148 |
{ |
1149 |
T0 = env->CP0_Config1; |
1150 |
RETURN(); |
1151 |
} |
1152 |
|
1153 |
void op_mfc0_config2 (void) |
1154 |
{ |
1155 |
T0 = env->CP0_Config2; |
1156 |
RETURN(); |
1157 |
} |
1158 |
|
1159 |
void op_mfc0_config3 (void) |
1160 |
{ |
1161 |
T0 = env->CP0_Config3; |
1162 |
RETURN(); |
1163 |
} |
1164 |
|
1165 |
void op_mfc0_config6 (void) |
1166 |
{ |
1167 |
T0 = env->CP0_Config6; |
1168 |
RETURN(); |
1169 |
} |
1170 |
|
1171 |
void op_mfc0_config7 (void) |
1172 |
{ |
1173 |
T0 = env->CP0_Config7; |
1174 |
RETURN(); |
1175 |
} |
1176 |
|
1177 |
void op_mfc0_lladdr (void) |
1178 |
{ |
1179 |
T0 = (int32_t)env->CP0_LLAddr >> 4;
|
1180 |
RETURN(); |
1181 |
} |
1182 |
|
1183 |
void op_mfc0_watchlo0 (void) |
1184 |
{ |
1185 |
T0 = (int32_t)env->CP0_WatchLo; |
1186 |
RETURN(); |
1187 |
} |
1188 |
|
1189 |
void op_mfc0_watchhi0 (void) |
1190 |
{ |
1191 |
T0 = env->CP0_WatchHi; |
1192 |
RETURN(); |
1193 |
} |
1194 |
|
1195 |
void op_mfc0_xcontext (void) |
1196 |
{ |
1197 |
T0 = (int32_t)env->CP0_XContext; |
1198 |
RETURN(); |
1199 |
} |
1200 |
|
1201 |
void op_mfc0_framemask (void) |
1202 |
{ |
1203 |
T0 = env->CP0_Framemask; |
1204 |
RETURN(); |
1205 |
} |
1206 |
|
1207 |
void op_mfc0_debug (void) |
1208 |
{ |
1209 |
T0 = env->CP0_Debug; |
1210 |
if (env->hflags & MIPS_HFLAG_DM)
|
1211 |
T0 |= 1 << CP0DB_DM;
|
1212 |
RETURN(); |
1213 |
} |
1214 |
|
1215 |
void op_mfc0_depc (void) |
1216 |
{ |
1217 |
T0 = (int32_t)env->CP0_DEPC; |
1218 |
RETURN(); |
1219 |
} |
1220 |
|
1221 |
void op_mfc0_performance0 (void) |
1222 |
{ |
1223 |
T0 = env->CP0_Performance0; |
1224 |
RETURN(); |
1225 |
} |
1226 |
|
1227 |
void op_mfc0_taglo (void) |
1228 |
{ |
1229 |
T0 = env->CP0_TagLo; |
1230 |
RETURN(); |
1231 |
} |
1232 |
|
1233 |
void op_mfc0_datalo (void) |
1234 |
{ |
1235 |
T0 = env->CP0_DataLo; |
1236 |
RETURN(); |
1237 |
} |
1238 |
|
1239 |
void op_mfc0_taghi (void) |
1240 |
{ |
1241 |
T0 = env->CP0_TagHi; |
1242 |
RETURN(); |
1243 |
} |
1244 |
|
1245 |
void op_mfc0_datahi (void) |
1246 |
{ |
1247 |
T0 = env->CP0_DataHi; |
1248 |
RETURN(); |
1249 |
} |
1250 |
|
1251 |
void op_mfc0_errorepc (void) |
1252 |
{ |
1253 |
T0 = (int32_t)env->CP0_ErrorEPC; |
1254 |
RETURN(); |
1255 |
} |
1256 |
|
1257 |
void op_mfc0_desave (void) |
1258 |
{ |
1259 |
T0 = env->CP0_DESAVE; |
1260 |
RETURN(); |
1261 |
} |
1262 |
|
1263 |
void op_mtc0_index (void) |
1264 |
{ |
1265 |
env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 % env->nb_tlb);
|
1266 |
RETURN(); |
1267 |
} |
1268 |
|
1269 |
void op_mtc0_entrylo0 (void) |
1270 |
{ |
1271 |
/* Large physaddr not implemented */
|
1272 |
/* 1k pages not implemented */
|
1273 |
env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
|
1274 |
RETURN(); |
1275 |
} |
1276 |
|
1277 |
void op_mtc0_entrylo1 (void) |
1278 |
{ |
1279 |
/* Large physaddr not implemented */
|
1280 |
/* 1k pages not implemented */
|
1281 |
env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
|
1282 |
RETURN(); |
1283 |
} |
1284 |
|
1285 |
void op_mtc0_context (void) |
1286 |
{ |
1287 |
env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF); |
1288 |
RETURN(); |
1289 |
} |
1290 |
|
1291 |
void op_mtc0_pagemask (void) |
1292 |
{ |
1293 |
/* 1k pages not implemented */
|
1294 |
env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); |
1295 |
RETURN(); |
1296 |
} |
1297 |
|
1298 |
void op_mtc0_pagegrain (void) |
1299 |
{ |
1300 |
/* SmartMIPS not implemented */
|
1301 |
/* Large physaddr not implemented */
|
1302 |
/* 1k pages not implemented */
|
1303 |
env->CP0_PageGrain = 0;
|
1304 |
RETURN(); |
1305 |
} |
1306 |
|
1307 |
void op_mtc0_wired (void) |
1308 |
{ |
1309 |
env->CP0_Wired = T0 % env->nb_tlb; |
1310 |
RETURN(); |
1311 |
} |
1312 |
|
1313 |
void op_mtc0_hwrena (void) |
1314 |
{ |
1315 |
env->CP0_HWREna = T0 & 0x0000000F;
|
1316 |
RETURN(); |
1317 |
} |
1318 |
|
1319 |
void op_mtc0_count (void) |
1320 |
{ |
1321 |
CALL_FROM_TB2(cpu_mips_store_count, env, T0); |
1322 |
RETURN(); |
1323 |
} |
1324 |
|
1325 |
void op_mtc0_entryhi (void) |
1326 |
{ |
1327 |
target_ulong old, val; |
1328 |
|
1329 |
/* 1k pages not implemented */
|
1330 |
val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF); |
1331 |
#ifdef TARGET_MIPS64
|
1332 |
val = T0 & 0xC00000FFFFFFFFFFULL;
|
1333 |
#endif
|
1334 |
old = env->CP0_EntryHi; |
1335 |
env->CP0_EntryHi = val; |
1336 |
/* If the ASID changes, flush qemu's TLB. */
|
1337 |
if ((old & 0xFF) != (val & 0xFF)) |
1338 |
CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
|
1339 |
RETURN(); |
1340 |
} |
1341 |
|
1342 |
void op_mtc0_compare (void) |
1343 |
{ |
1344 |
CALL_FROM_TB2(cpu_mips_store_compare, env, T0); |
1345 |
RETURN(); |
1346 |
} |
1347 |
|
1348 |
void op_mtc0_status (void) |
1349 |
{ |
1350 |
uint32_t val, old; |
1351 |
uint32_t mask = env->Status_rw_bitmask; |
1352 |
|
1353 |
/* No reverse endianness, no MDMX/DSP, no 64bit ops
|
1354 |
implemented. */
|
1355 |
val = T0 & mask; |
1356 |
old = env->CP0_Status; |
1357 |
if (!(val & (1 << CP0St_EXL)) && |
1358 |
!(val & (1 << CP0St_ERL)) &&
|
1359 |
!(env->hflags & MIPS_HFLAG_DM) && |
1360 |
(val & (1 << CP0St_UM)))
|
1361 |
env->hflags |= MIPS_HFLAG_UM; |
1362 |
env->CP0_Status = (env->CP0_Status & ~mask) | val; |
1363 |
if (loglevel & CPU_LOG_EXEC)
|
1364 |
CALL_FROM_TB2(do_mtc0_status_debug, old, val); |
1365 |
CALL_FROM_TB1(cpu_mips_update_irq, env); |
1366 |
RETURN(); |
1367 |
} |
1368 |
|
1369 |
void op_mtc0_intctl (void) |
1370 |
{ |
1371 |
/* vectored interrupts not implemented, timer on int 7,
|
1372 |
no performance counters. */
|
1373 |
env->CP0_IntCtl |= T0 & 0x000002e0;
|
1374 |
RETURN(); |
1375 |
} |
1376 |
|
1377 |
void op_mtc0_srsctl (void) |
1378 |
{ |
1379 |
/* shadow registers not implemented */
|
1380 |
env->CP0_SRSCtl = 0;
|
1381 |
RETURN(); |
1382 |
} |
1383 |
|
1384 |
void op_mtc0_srsmap (void) |
1385 |
{ |
1386 |
/* shadow registers not implemented */
|
1387 |
env->CP0_SRSMap = 0;
|
1388 |
RETURN(); |
1389 |
} |
1390 |
|
1391 |
void op_mtc0_cause (void) |
1392 |
{ |
1393 |
uint32_t mask = 0x00C00300;
|
1394 |
|
1395 |
if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) |
1396 |
mask |= 1 << CP0Ca_DC;
|
1397 |
|
1398 |
env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask); |
1399 |
|
1400 |
/* Handle the software interrupt as an hardware one, as they
|
1401 |
are very similar */
|
1402 |
if (T0 & CP0Ca_IP_mask) {
|
1403 |
CALL_FROM_TB1(cpu_mips_update_irq, env); |
1404 |
} |
1405 |
RETURN(); |
1406 |
} |
1407 |
|
1408 |
void op_mtc0_epc (void) |
1409 |
{ |
1410 |
env->CP0_EPC = T0; |
1411 |
RETURN(); |
1412 |
} |
1413 |
|
1414 |
void op_mtc0_ebase (void) |
1415 |
{ |
1416 |
/* vectored interrupts not implemented */
|
1417 |
/* Multi-CPU not implemented */
|
1418 |
env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000); |
1419 |
RETURN(); |
1420 |
} |
1421 |
|
1422 |
void op_mtc0_config0 (void) |
1423 |
{ |
1424 |
env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000001); |
1425 |
RETURN(); |
1426 |
} |
1427 |
|
1428 |
void op_mtc0_config2 (void) |
1429 |
{ |
1430 |
/* tertiary/secondary caches not implemented */
|
1431 |
env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
|
1432 |
RETURN(); |
1433 |
} |
1434 |
|
1435 |
void op_mtc0_watchlo0 (void) |
1436 |
{ |
1437 |
/* Watch exceptions for instructions, data loads, data stores
|
1438 |
not implemented. */
|
1439 |
env->CP0_WatchLo = (T0 & ~0x7);
|
1440 |
RETURN(); |
1441 |
} |
1442 |
|
1443 |
void op_mtc0_watchhi0 (void) |
1444 |
{ |
1445 |
env->CP0_WatchHi = (T0 & 0x40FF0FF8);
|
1446 |
env->CP0_WatchHi &= ~(env->CP0_WatchHi & T0 & 0x7);
|
1447 |
RETURN(); |
1448 |
} |
1449 |
|
1450 |
void op_mtc0_framemask (void) |
1451 |
{ |
1452 |
env->CP0_Framemask = T0; /* XXX */
|
1453 |
RETURN(); |
1454 |
} |
1455 |
|
1456 |
void op_mtc0_debug (void) |
1457 |
{ |
1458 |
env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); |
1459 |
if (T0 & (1 << CP0DB_DM)) |
1460 |
env->hflags |= MIPS_HFLAG_DM; |
1461 |
else
|
1462 |
env->hflags &= ~MIPS_HFLAG_DM; |
1463 |
RETURN(); |
1464 |
} |
1465 |
|
1466 |
void op_mtc0_depc (void) |
1467 |
{ |
1468 |
env->CP0_DEPC = T0; |
1469 |
RETURN(); |
1470 |
} |
1471 |
|
1472 |
void op_mtc0_performance0 (void) |
1473 |
{ |
1474 |
env->CP0_Performance0 = T0; /* XXX */
|
1475 |
RETURN(); |
1476 |
} |
1477 |
|
1478 |
void op_mtc0_taglo (void) |
1479 |
{ |
1480 |
env->CP0_TagLo = T0 & 0xFFFFFCF6;
|
1481 |
RETURN(); |
1482 |
} |
1483 |
|
1484 |
void op_mtc0_datalo (void) |
1485 |
{ |
1486 |
env->CP0_DataLo = T0; /* XXX */
|
1487 |
RETURN(); |
1488 |
} |
1489 |
|
1490 |
void op_mtc0_taghi (void) |
1491 |
{ |
1492 |
env->CP0_TagHi = T0; /* XXX */
|
1493 |
RETURN(); |
1494 |
} |
1495 |
|
1496 |
void op_mtc0_datahi (void) |
1497 |
{ |
1498 |
env->CP0_DataHi = T0; /* XXX */
|
1499 |
RETURN(); |
1500 |
} |
1501 |
|
1502 |
void op_mtc0_errorepc (void) |
1503 |
{ |
1504 |
env->CP0_ErrorEPC = T0; |
1505 |
RETURN(); |
1506 |
} |
1507 |
|
1508 |
void op_mtc0_desave (void) |
1509 |
{ |
1510 |
env->CP0_DESAVE = T0; |
1511 |
RETURN(); |
1512 |
} |
1513 |
|
1514 |
#ifdef TARGET_MIPS64
|
1515 |
void op_mtc0_xcontext (void) |
1516 |
{ |
1517 |
env->CP0_XContext = (env->CP0_XContext & 0x1ffffffffULL) | (T0 & ~0x1ffffffffULL); |
1518 |
RETURN(); |
1519 |
} |
1520 |
|
1521 |
void op_dmfc0_entrylo0 (void) |
1522 |
{ |
1523 |
T0 = env->CP0_EntryLo0; |
1524 |
RETURN(); |
1525 |
} |
1526 |
|
1527 |
void op_dmfc0_entrylo1 (void) |
1528 |
{ |
1529 |
T0 = env->CP0_EntryLo1; |
1530 |
RETURN(); |
1531 |
} |
1532 |
|
1533 |
void op_dmfc0_context (void) |
1534 |
{ |
1535 |
T0 = env->CP0_Context; |
1536 |
RETURN(); |
1537 |
} |
1538 |
|
1539 |
void op_dmfc0_badvaddr (void) |
1540 |
{ |
1541 |
T0 = env->CP0_BadVAddr; |
1542 |
RETURN(); |
1543 |
} |
1544 |
|
1545 |
void op_dmfc0_entryhi (void) |
1546 |
{ |
1547 |
T0 = env->CP0_EntryHi; |
1548 |
RETURN(); |
1549 |
} |
1550 |
|
1551 |
void op_dmfc0_epc (void) |
1552 |
{ |
1553 |
T0 = env->CP0_EPC; |
1554 |
RETURN(); |
1555 |
} |
1556 |
|
1557 |
void op_dmfc0_lladdr (void) |
1558 |
{ |
1559 |
T0 = env->CP0_LLAddr >> 4;
|
1560 |
RETURN(); |
1561 |
} |
1562 |
|
1563 |
void op_dmfc0_watchlo0 (void) |
1564 |
{ |
1565 |
T0 = env->CP0_WatchLo; |
1566 |
RETURN(); |
1567 |
} |
1568 |
|
1569 |
void op_dmfc0_xcontext (void) |
1570 |
{ |
1571 |
T0 = env->CP0_XContext; |
1572 |
RETURN(); |
1573 |
} |
1574 |
|
1575 |
void op_dmfc0_depc (void) |
1576 |
{ |
1577 |
T0 = env->CP0_DEPC; |
1578 |
RETURN(); |
1579 |
} |
1580 |
|
1581 |
void op_dmfc0_errorepc (void) |
1582 |
{ |
1583 |
T0 = env->CP0_ErrorEPC; |
1584 |
RETURN(); |
1585 |
} |
1586 |
#endif /* TARGET_MIPS64 */ |
1587 |
|
1588 |
/* CP1 functions */
|
1589 |
#if 0
|
1590 |
# define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
|
1591 |
#else
|
1592 |
# define DEBUG_FPU_STATE() do { } while(0) |
1593 |
#endif
|
1594 |
|
1595 |
void op_cp0_enabled(void) |
1596 |
{ |
1597 |
if (!(env->CP0_Status & (1 << CP0St_CU0)) && |
1598 |
(env->hflags & MIPS_HFLAG_UM)) { |
1599 |
CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 0);
|
1600 |
} |
1601 |
RETURN(); |
1602 |
} |
1603 |
|
1604 |
void op_cp1_enabled(void) |
1605 |
{ |
1606 |
if (!(env->CP0_Status & (1 << CP0St_CU1))) { |
1607 |
CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1);
|
1608 |
} |
1609 |
RETURN(); |
1610 |
} |
1611 |
|
1612 |
/*
|
1613 |
* Verify if floating point register is valid; an operation is not defined
|
1614 |
* if bit 0 of any register specification is set and the FR bit in the
|
1615 |
* Status register equals zero, since the register numbers specify an
|
1616 |
* even-odd pair of adjacent coprocessor general registers. When the FR bit
|
1617 |
* in the Status register equals one, both even and odd register numbers
|
1618 |
* are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
|
1619 |
*
|
1620 |
* Multiple 64 bit wide registers can be checked by calling
|
1621 |
* gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
|
1622 |
*/
|
1623 |
void op_cp1_registers(void) |
1624 |
{ |
1625 |
if (!(env->CP0_Status & (1 << CP0St_FR)) && (PARAM1 & 1)) { |
1626 |
CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
1627 |
} |
1628 |
RETURN(); |
1629 |
} |
1630 |
|
1631 |
void op_cfc1 (void) |
1632 |
{ |
1633 |
switch (T1) {
|
1634 |
case 0: |
1635 |
T0 = (int32_t)env->fcr0; |
1636 |
break;
|
1637 |
case 25: |
1638 |
T0 = ((env->fcr31 >> 24) & 0xfe) | ((env->fcr31 >> 23) & 0x1); |
1639 |
break;
|
1640 |
case 26: |
1641 |
T0 = env->fcr31 & 0x0003f07c;
|
1642 |
break;
|
1643 |
case 28: |
1644 |
T0 = (env->fcr31 & 0x00000f83) | ((env->fcr31 >> 22) & 0x4); |
1645 |
break;
|
1646 |
default:
|
1647 |
T0 = (int32_t)env->fcr31; |
1648 |
break;
|
1649 |
} |
1650 |
DEBUG_FPU_STATE(); |
1651 |
RETURN(); |
1652 |
} |
1653 |
|
1654 |
void op_ctc1 (void) |
1655 |
{ |
1656 |
CALL_FROM_TB0(do_ctc1); |
1657 |
DEBUG_FPU_STATE(); |
1658 |
RETURN(); |
1659 |
} |
1660 |
|
1661 |
void op_mfc1 (void) |
1662 |
{ |
1663 |
T0 = WT0; |
1664 |
DEBUG_FPU_STATE(); |
1665 |
RETURN(); |
1666 |
} |
1667 |
|
1668 |
void op_mtc1 (void) |
1669 |
{ |
1670 |
WT0 = T0; |
1671 |
DEBUG_FPU_STATE(); |
1672 |
RETURN(); |
1673 |
} |
1674 |
|
1675 |
void op_dmfc1 (void) |
1676 |
{ |
1677 |
T0 = DT0; |
1678 |
DEBUG_FPU_STATE(); |
1679 |
RETURN(); |
1680 |
} |
1681 |
|
1682 |
void op_dmtc1 (void) |
1683 |
{ |
1684 |
DT0 = T0; |
1685 |
DEBUG_FPU_STATE(); |
1686 |
RETURN(); |
1687 |
} |
1688 |
|
1689 |
void op_mfhc1 (void) |
1690 |
{ |
1691 |
T0 = WTH0; |
1692 |
DEBUG_FPU_STATE(); |
1693 |
RETURN(); |
1694 |
} |
1695 |
|
1696 |
void op_mthc1 (void) |
1697 |
{ |
1698 |
WTH0 = T0; |
1699 |
DEBUG_FPU_STATE(); |
1700 |
RETURN(); |
1701 |
} |
1702 |
|
1703 |
/* Float support.
|
1704 |
Single precition routines have a "s" suffix, double precision a
|
1705 |
"d" suffix, 32bit integer "w", 64bit integer "l", paired singe "ps",
|
1706 |
paired single lowwer "pl", paired single upper "pu". */
|
1707 |
|
1708 |
#define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void) |
1709 |
|
1710 |
FLOAT_OP(cvtd, s) |
1711 |
{ |
1712 |
CALL_FROM_TB0(do_float_cvtd_s); |
1713 |
DEBUG_FPU_STATE(); |
1714 |
RETURN(); |
1715 |
} |
1716 |
FLOAT_OP(cvtd, w) |
1717 |
{ |
1718 |
CALL_FROM_TB0(do_float_cvtd_w); |
1719 |
DEBUG_FPU_STATE(); |
1720 |
RETURN(); |
1721 |
} |
1722 |
FLOAT_OP(cvtd, l) |
1723 |
{ |
1724 |
CALL_FROM_TB0(do_float_cvtd_l); |
1725 |
DEBUG_FPU_STATE(); |
1726 |
RETURN(); |
1727 |
} |
1728 |
FLOAT_OP(cvtl, d) |
1729 |
{ |
1730 |
CALL_FROM_TB0(do_float_cvtl_d); |
1731 |
DEBUG_FPU_STATE(); |
1732 |
RETURN(); |
1733 |
} |
1734 |
FLOAT_OP(cvtl, s) |
1735 |
{ |
1736 |
CALL_FROM_TB0(do_float_cvtl_s); |
1737 |
DEBUG_FPU_STATE(); |
1738 |
RETURN(); |
1739 |
} |
1740 |
FLOAT_OP(cvtps, s) |
1741 |
{ |
1742 |
WT2 = WT0; |
1743 |
WTH2 = WT1; |
1744 |
DEBUG_FPU_STATE(); |
1745 |
RETURN(); |
1746 |
} |
1747 |
FLOAT_OP(cvtps, pw) |
1748 |
{ |
1749 |
CALL_FROM_TB0(do_float_cvtps_pw); |
1750 |
DEBUG_FPU_STATE(); |
1751 |
RETURN(); |
1752 |
} |
1753 |
FLOAT_OP(cvtpw, ps) |
1754 |
{ |
1755 |
CALL_FROM_TB0(do_float_cvtpw_ps); |
1756 |
DEBUG_FPU_STATE(); |
1757 |
RETURN(); |
1758 |
} |
1759 |
FLOAT_OP(cvts, d) |
1760 |
{ |
1761 |
CALL_FROM_TB0(do_float_cvts_d); |
1762 |
DEBUG_FPU_STATE(); |
1763 |
RETURN(); |
1764 |
} |
1765 |
FLOAT_OP(cvts, w) |
1766 |
{ |
1767 |
CALL_FROM_TB0(do_float_cvts_w); |
1768 |
DEBUG_FPU_STATE(); |
1769 |
RETURN(); |
1770 |
} |
1771 |
FLOAT_OP(cvts, l) |
1772 |
{ |
1773 |
CALL_FROM_TB0(do_float_cvts_l); |
1774 |
DEBUG_FPU_STATE(); |
1775 |
RETURN(); |
1776 |
} |
1777 |
FLOAT_OP(cvts, pl) |
1778 |
{ |
1779 |
CALL_FROM_TB0(do_float_cvts_pl); |
1780 |
DEBUG_FPU_STATE(); |
1781 |
RETURN(); |
1782 |
} |
1783 |
FLOAT_OP(cvts, pu) |
1784 |
{ |
1785 |
CALL_FROM_TB0(do_float_cvts_pu); |
1786 |
DEBUG_FPU_STATE(); |
1787 |
RETURN(); |
1788 |
} |
1789 |
FLOAT_OP(cvtw, s) |
1790 |
{ |
1791 |
CALL_FROM_TB0(do_float_cvtw_s); |
1792 |
DEBUG_FPU_STATE(); |
1793 |
RETURN(); |
1794 |
} |
1795 |
FLOAT_OP(cvtw, d) |
1796 |
{ |
1797 |
CALL_FROM_TB0(do_float_cvtw_d); |
1798 |
DEBUG_FPU_STATE(); |
1799 |
RETURN(); |
1800 |
} |
1801 |
|
1802 |
FLOAT_OP(pll, ps) |
1803 |
{ |
1804 |
DT2 = ((uint64_t)WT0 << 32) | WT1;
|
1805 |
DEBUG_FPU_STATE(); |
1806 |
RETURN(); |
1807 |
} |
1808 |
FLOAT_OP(plu, ps) |
1809 |
{ |
1810 |
DT2 = ((uint64_t)WT0 << 32) | WTH1;
|
1811 |
DEBUG_FPU_STATE(); |
1812 |
RETURN(); |
1813 |
} |
1814 |
FLOAT_OP(pul, ps) |
1815 |
{ |
1816 |
DT2 = ((uint64_t)WTH0 << 32) | WT1;
|
1817 |
DEBUG_FPU_STATE(); |
1818 |
RETURN(); |
1819 |
} |
1820 |
FLOAT_OP(puu, ps) |
1821 |
{ |
1822 |
DT2 = ((uint64_t)WTH0 << 32) | WTH1;
|
1823 |
DEBUG_FPU_STATE(); |
1824 |
RETURN(); |
1825 |
} |
1826 |
|
1827 |
#define FLOAT_ROUNDOP(op, ttype, stype) \
|
1828 |
FLOAT_OP(op ## ttype, stype) \ |
1829 |
{ \ |
1830 |
CALL_FROM_TB0(do_float_ ## op ## ttype ## _ ## stype); \ |
1831 |
DEBUG_FPU_STATE(); \ |
1832 |
RETURN(); \ |
1833 |
} |
1834 |
|
1835 |
FLOAT_ROUNDOP(round, l, d) |
1836 |
FLOAT_ROUNDOP(round, l, s) |
1837 |
FLOAT_ROUNDOP(round, w, d) |
1838 |
FLOAT_ROUNDOP(round, w, s) |
1839 |
|
1840 |
FLOAT_ROUNDOP(trunc, l, d) |
1841 |
FLOAT_ROUNDOP(trunc, l, s) |
1842 |
FLOAT_ROUNDOP(trunc, w, d) |
1843 |
FLOAT_ROUNDOP(trunc, w, s) |
1844 |
|
1845 |
FLOAT_ROUNDOP(ceil, l, d) |
1846 |
FLOAT_ROUNDOP(ceil, l, s) |
1847 |
FLOAT_ROUNDOP(ceil, w, d) |
1848 |
FLOAT_ROUNDOP(ceil, w, s) |
1849 |
|
1850 |
FLOAT_ROUNDOP(floor, l, d) |
1851 |
FLOAT_ROUNDOP(floor, l, s) |
1852 |
FLOAT_ROUNDOP(floor, w, d) |
1853 |
FLOAT_ROUNDOP(floor, w, s) |
1854 |
#undef FLOAR_ROUNDOP
|
1855 |
|
1856 |
FLOAT_OP(movf, d) |
1857 |
{ |
1858 |
if (!(env->fcr31 & PARAM1))
|
1859 |
DT2 = DT0; |
1860 |
DEBUG_FPU_STATE(); |
1861 |
RETURN(); |
1862 |
} |
1863 |
FLOAT_OP(movf, s) |
1864 |
{ |
1865 |
if (!(env->fcr31 & PARAM1))
|
1866 |
WT2 = WT0; |
1867 |
DEBUG_FPU_STATE(); |
1868 |
RETURN(); |
1869 |
} |
1870 |
FLOAT_OP(movf, ps) |
1871 |
{ |
1872 |
if (!(env->fcr31 & PARAM1)) {
|
1873 |
WT2 = WT0; |
1874 |
WTH2 = WTH0; |
1875 |
} |
1876 |
DEBUG_FPU_STATE(); |
1877 |
RETURN(); |
1878 |
} |
1879 |
FLOAT_OP(movt, d) |
1880 |
{ |
1881 |
if (env->fcr31 & PARAM1)
|
1882 |
DT2 = DT0; |
1883 |
DEBUG_FPU_STATE(); |
1884 |
RETURN(); |
1885 |
} |
1886 |
FLOAT_OP(movt, s) |
1887 |
{ |
1888 |
if (env->fcr31 & PARAM1)
|
1889 |
WT2 = WT0; |
1890 |
DEBUG_FPU_STATE(); |
1891 |
RETURN(); |
1892 |
} |
1893 |
FLOAT_OP(movt, ps) |
1894 |
{ |
1895 |
if (env->fcr31 & PARAM1) {
|
1896 |
WT2 = WT0; |
1897 |
WTH2 = WTH0; |
1898 |
} |
1899 |
DEBUG_FPU_STATE(); |
1900 |
RETURN(); |
1901 |
} |
1902 |
FLOAT_OP(movz, d) |
1903 |
{ |
1904 |
if (!T0)
|
1905 |
DT2 = DT0; |
1906 |
DEBUG_FPU_STATE(); |
1907 |
RETURN(); |
1908 |
} |
1909 |
FLOAT_OP(movz, s) |
1910 |
{ |
1911 |
if (!T0)
|
1912 |
WT2 = WT0; |
1913 |
DEBUG_FPU_STATE(); |
1914 |
RETURN(); |
1915 |
} |
1916 |
FLOAT_OP(movz, ps) |
1917 |
{ |
1918 |
if (!T0) {
|
1919 |
WT2 = WT0; |
1920 |
WTH2 = WTH0; |
1921 |
} |
1922 |
DEBUG_FPU_STATE(); |
1923 |
RETURN(); |
1924 |
} |
1925 |
FLOAT_OP(movn, d) |
1926 |
{ |
1927 |
if (T0)
|
1928 |
DT2 = DT0; |
1929 |
DEBUG_FPU_STATE(); |
1930 |
RETURN(); |
1931 |
} |
1932 |
FLOAT_OP(movn, s) |
1933 |
{ |
1934 |
if (T0)
|
1935 |
WT2 = WT0; |
1936 |
DEBUG_FPU_STATE(); |
1937 |
RETURN(); |
1938 |
} |
1939 |
FLOAT_OP(movn, ps) |
1940 |
{ |
1941 |
if (T0) {
|
1942 |
WT2 = WT0; |
1943 |
WTH2 = WTH0; |
1944 |
} |
1945 |
DEBUG_FPU_STATE(); |
1946 |
RETURN(); |
1947 |
} |
1948 |
|
1949 |
/* binary operations */
|
1950 |
#define FLOAT_BINOP(name) \
|
1951 |
FLOAT_OP(name, d) \ |
1952 |
{ \ |
1953 |
CALL_FROM_TB0(do_float_ ## name ## _d); \ |
1954 |
DEBUG_FPU_STATE(); \ |
1955 |
RETURN(); \ |
1956 |
} \ |
1957 |
FLOAT_OP(name, s) \ |
1958 |
{ \ |
1959 |
CALL_FROM_TB0(do_float_ ## name ## _s); \ |
1960 |
DEBUG_FPU_STATE(); \ |
1961 |
RETURN(); \ |
1962 |
} \ |
1963 |
FLOAT_OP(name, ps) \ |
1964 |
{ \ |
1965 |
CALL_FROM_TB0(do_float_ ## name ## _ps); \ |
1966 |
DEBUG_FPU_STATE(); \ |
1967 |
RETURN(); \ |
1968 |
} |
1969 |
FLOAT_BINOP(add) |
1970 |
FLOAT_BINOP(sub) |
1971 |
FLOAT_BINOP(mul) |
1972 |
FLOAT_BINOP(div) |
1973 |
#undef FLOAT_BINOP
|
1974 |
|
1975 |
FLOAT_OP(addr, ps) |
1976 |
{ |
1977 |
CALL_FROM_TB0(do_float_addr_ps); |
1978 |
DEBUG_FPU_STATE(); |
1979 |
RETURN(); |
1980 |
} |
1981 |
|
1982 |
/* ternary operations */
|
1983 |
#define FLOAT_TERNOP(name1, name2) \
|
1984 |
FLOAT_OP(name1 ## name2, d) \ |
1985 |
{ \ |
1986 |
FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fp_status); \ |
1987 |
FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fp_status); \ |
1988 |
DEBUG_FPU_STATE(); \ |
1989 |
RETURN(); \ |
1990 |
} \ |
1991 |
FLOAT_OP(name1 ## name2, s) \ |
1992 |
{ \ |
1993 |
FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status); \ |
1994 |
FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status); \ |
1995 |
DEBUG_FPU_STATE(); \ |
1996 |
RETURN(); \ |
1997 |
} \ |
1998 |
FLOAT_OP(name1 ## name2, ps) \ |
1999 |
{ \ |
2000 |
FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status); \ |
2001 |
FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fp_status); \ |
2002 |
FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status); \ |
2003 |
FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fp_status); \ |
2004 |
DEBUG_FPU_STATE(); \ |
2005 |
RETURN(); \ |
2006 |
} |
2007 |
FLOAT_TERNOP(mul, add) |
2008 |
FLOAT_TERNOP(mul, sub) |
2009 |
#undef FLOAT_TERNOP
|
2010 |
|
2011 |
/* negated ternary operations */
|
2012 |
#define FLOAT_NTERNOP(name1, name2) \
|
2013 |
FLOAT_OP(n ## name1 ## name2, d) \ |
2014 |
{ \ |
2015 |
FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fp_status); \ |
2016 |
FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fp_status); \ |
2017 |
FDT2 ^= 1ULL << 63; \ |
2018 |
DEBUG_FPU_STATE(); \ |
2019 |
RETURN(); \ |
2020 |
} \ |
2021 |
FLOAT_OP(n ## name1 ## name2, s) \ |
2022 |
{ \ |
2023 |
FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status); \ |
2024 |
FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status); \ |
2025 |
FST2 ^= 1 << 31; \ |
2026 |
DEBUG_FPU_STATE(); \ |
2027 |
RETURN(); \ |
2028 |
} \ |
2029 |
FLOAT_OP(n ## name1 ## name2, ps) \ |
2030 |
{ \ |
2031 |
FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status); \ |
2032 |
FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fp_status); \ |
2033 |
FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status); \ |
2034 |
FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fp_status); \ |
2035 |
FST2 ^= 1 << 31; \ |
2036 |
FSTH2 ^= 1 << 31; \ |
2037 |
DEBUG_FPU_STATE(); \ |
2038 |
RETURN(); \ |
2039 |
} |
2040 |
FLOAT_NTERNOP(mul, add) |
2041 |
FLOAT_NTERNOP(mul, sub) |
2042 |
#undef FLOAT_NTERNOP
|
2043 |
|
2044 |
/* unary operations, modifying fp status */
|
2045 |
#define FLOAT_UNOP(name) \
|
2046 |
FLOAT_OP(name, d) \ |
2047 |
{ \ |
2048 |
FDT2 = float64_ ## name(FDT0, &env->fp_status); \ |
2049 |
DEBUG_FPU_STATE(); \ |
2050 |
RETURN(); \ |
2051 |
} \ |
2052 |
FLOAT_OP(name, s) \ |
2053 |
{ \ |
2054 |
FST2 = float32_ ## name(FST0, &env->fp_status); \ |
2055 |
DEBUG_FPU_STATE(); \ |
2056 |
RETURN(); \ |
2057 |
} \ |
2058 |
FLOAT_OP(name, ps) \ |
2059 |
{ \ |
2060 |
FST2 = float32_ ## name(FST0, &env->fp_status); \ |
2061 |
FSTH2 = float32_ ## name(FSTH0, &env->fp_status); \ |
2062 |
DEBUG_FPU_STATE(); \ |
2063 |
RETURN(); \ |
2064 |
} |
2065 |
FLOAT_UNOP(sqrt) |
2066 |
#undef FLOAT_UNOP
|
2067 |
|
2068 |
/* unary operations, not modifying fp status */
|
2069 |
#define FLOAT_UNOP(name) \
|
2070 |
FLOAT_OP(name, d) \ |
2071 |
{ \ |
2072 |
FDT2 = float64_ ## name(FDT0); \ |
2073 |
DEBUG_FPU_STATE(); \ |
2074 |
RETURN(); \ |
2075 |
} \ |
2076 |
FLOAT_OP(name, s) \ |
2077 |
{ \ |
2078 |
FST2 = float32_ ## name(FST0); \ |
2079 |
DEBUG_FPU_STATE(); \ |
2080 |
RETURN(); \ |
2081 |
} \ |
2082 |
FLOAT_OP(name, ps) \ |
2083 |
{ \ |
2084 |
FST2 = float32_ ## name(FST0); \ |
2085 |
FSTH2 = float32_ ## name(FSTH0); \ |
2086 |
DEBUG_FPU_STATE(); \ |
2087 |
RETURN(); \ |
2088 |
} |
2089 |
FLOAT_UNOP(abs) |
2090 |
FLOAT_UNOP(chs) |
2091 |
#undef FLOAT_UNOP
|
2092 |
|
2093 |
FLOAT_OP(mov, d) |
2094 |
{ |
2095 |
FDT2 = FDT0; |
2096 |
DEBUG_FPU_STATE(); |
2097 |
RETURN(); |
2098 |
} |
2099 |
FLOAT_OP(mov, s) |
2100 |
{ |
2101 |
FST2 = FST0; |
2102 |
DEBUG_FPU_STATE(); |
2103 |
RETURN(); |
2104 |
} |
2105 |
FLOAT_OP(mov, ps) |
2106 |
{ |
2107 |
FST2 = FST0; |
2108 |
FSTH2 = FSTH0; |
2109 |
DEBUG_FPU_STATE(); |
2110 |
RETURN(); |
2111 |
} |
2112 |
FLOAT_OP(alnv, ps) |
2113 |
{ |
2114 |
switch (T0 & 0x7) { |
2115 |
case 0: |
2116 |
FST2 = FST0; |
2117 |
FSTH2 = FSTH0; |
2118 |
break;
|
2119 |
case 4: |
2120 |
#ifdef TARGET_WORDS_BIGENDIAN
|
2121 |
FSTH2 = FST0; |
2122 |
FST2 = FSTH1; |
2123 |
#else
|
2124 |
FSTH2 = FST1; |
2125 |
FST2 = FSTH0; |
2126 |
#endif
|
2127 |
break;
|
2128 |
default: /* unpredictable */ |
2129 |
break;
|
2130 |
} |
2131 |
DEBUG_FPU_STATE(); |
2132 |
RETURN(); |
2133 |
} |
2134 |
|
2135 |
#ifdef CONFIG_SOFTFLOAT
|
2136 |
#define clear_invalid() do { \ |
2137 |
int flags = get_float_exception_flags(&env->fp_status); \
|
2138 |
flags &= ~float_flag_invalid; \ |
2139 |
set_float_exception_flags(flags, &env->fp_status); \ |
2140 |
} while(0) |
2141 |
#else
|
2142 |
#define clear_invalid() do { } while(0) |
2143 |
#endif
|
2144 |
|
2145 |
extern void dump_fpu_s(CPUState *env); |
2146 |
|
2147 |
#define CMP_OP(fmt, op) \
|
2148 |
void OPPROTO op_cmp ## _ ## fmt ## _ ## op(void) \ |
2149 |
{ \ |
2150 |
CALL_FROM_TB1(do_cmp ## _ ## fmt ## _ ## op, PARAM1); \ |
2151 |
DEBUG_FPU_STATE(); \ |
2152 |
RETURN(); \ |
2153 |
} \ |
2154 |
void OPPROTO op_cmpabs ## _ ## fmt ## _ ## op(void) \ |
2155 |
{ \ |
2156 |
CALL_FROM_TB1(do_cmpabs ## _ ## fmt ## _ ## op, PARAM1); \ |
2157 |
DEBUG_FPU_STATE(); \ |
2158 |
RETURN(); \ |
2159 |
} |
2160 |
#define CMP_OPS(op) \
|
2161 |
CMP_OP(d, op) \ |
2162 |
CMP_OP(s, op) \ |
2163 |
CMP_OP(ps, op) |
2164 |
|
2165 |
CMP_OPS(f) |
2166 |
CMP_OPS(un) |
2167 |
CMP_OPS(eq) |
2168 |
CMP_OPS(ueq) |
2169 |
CMP_OPS(olt) |
2170 |
CMP_OPS(ult) |
2171 |
CMP_OPS(ole) |
2172 |
CMP_OPS(ule) |
2173 |
CMP_OPS(sf) |
2174 |
CMP_OPS(ngle) |
2175 |
CMP_OPS(seq) |
2176 |
CMP_OPS(ngl) |
2177 |
CMP_OPS(lt) |
2178 |
CMP_OPS(nge) |
2179 |
CMP_OPS(le) |
2180 |
CMP_OPS(ngt) |
2181 |
#undef CMP_OPS
|
2182 |
#undef CMP_OP
|
2183 |
|
2184 |
void op_bc1f (void) |
2185 |
{ |
2186 |
T0 = !!(~GET_FP_COND(env) & (0x1 << PARAM1));
|
2187 |
DEBUG_FPU_STATE(); |
2188 |
RETURN(); |
2189 |
} |
2190 |
void op_bc1any2f (void) |
2191 |
{ |
2192 |
T0 = !!(~GET_FP_COND(env) & (0x3 << PARAM1));
|
2193 |
DEBUG_FPU_STATE(); |
2194 |
RETURN(); |
2195 |
} |
2196 |
void op_bc1any4f (void) |
2197 |
{ |
2198 |
T0 = !!(~GET_FP_COND(env) & (0xf << PARAM1));
|
2199 |
DEBUG_FPU_STATE(); |
2200 |
RETURN(); |
2201 |
} |
2202 |
|
2203 |
void op_bc1t (void) |
2204 |
{ |
2205 |
T0 = !!(GET_FP_COND(env) & (0x1 << PARAM1));
|
2206 |
DEBUG_FPU_STATE(); |
2207 |
RETURN(); |
2208 |
} |
2209 |
void op_bc1any2t (void) |
2210 |
{ |
2211 |
T0 = !!(GET_FP_COND(env) & (0x3 << PARAM1));
|
2212 |
DEBUG_FPU_STATE(); |
2213 |
RETURN(); |
2214 |
} |
2215 |
void op_bc1any4t (void) |
2216 |
{ |
2217 |
T0 = !!(GET_FP_COND(env) & (0xf << PARAM1));
|
2218 |
DEBUG_FPU_STATE(); |
2219 |
RETURN(); |
2220 |
} |
2221 |
|
2222 |
void op_tlbwi (void) |
2223 |
{ |
2224 |
CALL_FROM_TB0(env->do_tlbwi); |
2225 |
RETURN(); |
2226 |
} |
2227 |
|
2228 |
void op_tlbwr (void) |
2229 |
{ |
2230 |
CALL_FROM_TB0(env->do_tlbwr); |
2231 |
RETURN(); |
2232 |
} |
2233 |
|
2234 |
void op_tlbp (void) |
2235 |
{ |
2236 |
CALL_FROM_TB0(env->do_tlbp); |
2237 |
RETURN(); |
2238 |
} |
2239 |
|
2240 |
void op_tlbr (void) |
2241 |
{ |
2242 |
CALL_FROM_TB0(env->do_tlbr); |
2243 |
RETURN(); |
2244 |
} |
2245 |
|
2246 |
/* Specials */
|
2247 |
#if defined (CONFIG_USER_ONLY)
|
2248 |
void op_tls_value (void) |
2249 |
{ |
2250 |
T0 = env->tls_value; |
2251 |
} |
2252 |
#endif
|
2253 |
|
2254 |
void op_pmon (void) |
2255 |
{ |
2256 |
CALL_FROM_TB1(do_pmon, PARAM1); |
2257 |
RETURN(); |
2258 |
} |
2259 |
|
2260 |
void op_di (void) |
2261 |
{ |
2262 |
T0 = env->CP0_Status; |
2263 |
env->CP0_Status = T0 & ~(1 << CP0St_IE);
|
2264 |
CALL_FROM_TB1(cpu_mips_update_irq, env); |
2265 |
RETURN(); |
2266 |
} |
2267 |
|
2268 |
void op_ei (void) |
2269 |
{ |
2270 |
T0 = env->CP0_Status; |
2271 |
env->CP0_Status = T0 | (1 << CP0St_IE);
|
2272 |
CALL_FROM_TB1(cpu_mips_update_irq, env); |
2273 |
RETURN(); |
2274 |
} |
2275 |
|
2276 |
void op_trap (void) |
2277 |
{ |
2278 |
if (T0) {
|
2279 |
CALL_FROM_TB1(do_raise_exception, EXCP_TRAP); |
2280 |
} |
2281 |
RETURN(); |
2282 |
} |
2283 |
|
2284 |
void op_debug (void) |
2285 |
{ |
2286 |
CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG); |
2287 |
RETURN(); |
2288 |
} |
2289 |
|
2290 |
void op_set_lladdr (void) |
2291 |
{ |
2292 |
env->CP0_LLAddr = T2; |
2293 |
RETURN(); |
2294 |
} |
2295 |
|
2296 |
void debug_pre_eret (void); |
2297 |
void debug_post_eret (void); |
2298 |
void op_eret (void) |
2299 |
{ |
2300 |
if (loglevel & CPU_LOG_EXEC)
|
2301 |
CALL_FROM_TB0(debug_pre_eret); |
2302 |
if (env->CP0_Status & (1 << CP0St_ERL)) { |
2303 |
env->PC = env->CP0_ErrorEPC; |
2304 |
env->CP0_Status &= ~(1 << CP0St_ERL);
|
2305 |
} else {
|
2306 |
env->PC = env->CP0_EPC; |
2307 |
env->CP0_Status &= ~(1 << CP0St_EXL);
|
2308 |
} |
2309 |
if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
2310 |
!(env->CP0_Status & (1 << CP0St_ERL)) &&
|
2311 |
!(env->hflags & MIPS_HFLAG_DM) && |
2312 |
(env->CP0_Status & (1 << CP0St_UM)))
|
2313 |
env->hflags |= MIPS_HFLAG_UM; |
2314 |
if (loglevel & CPU_LOG_EXEC)
|
2315 |
CALL_FROM_TB0(debug_post_eret); |
2316 |
env->CP0_LLAddr = 1;
|
2317 |
RETURN(); |
2318 |
} |
2319 |
|
2320 |
void op_deret (void) |
2321 |
{ |
2322 |
if (loglevel & CPU_LOG_EXEC)
|
2323 |
CALL_FROM_TB0(debug_pre_eret); |
2324 |
env->PC = env->CP0_DEPC; |
2325 |
env->hflags |= MIPS_HFLAG_DM; |
2326 |
if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
2327 |
!(env->CP0_Status & (1 << CP0St_ERL)) &&
|
2328 |
!(env->hflags & MIPS_HFLAG_DM) && |
2329 |
(env->CP0_Status & (1 << CP0St_UM)))
|
2330 |
env->hflags |= MIPS_HFLAG_UM; |
2331 |
if (loglevel & CPU_LOG_EXEC)
|
2332 |
CALL_FROM_TB0(debug_post_eret); |
2333 |
env->CP0_LLAddr = 1;
|
2334 |
RETURN(); |
2335 |
} |
2336 |
|
2337 |
void op_rdhwr_cpunum(void) |
2338 |
{ |
2339 |
if (!(env->hflags & MIPS_HFLAG_UM) ||
|
2340 |
(env->CP0_HWREna & (1 << 0)) || |
2341 |
(env->CP0_Status & (1 << CP0St_CU0)))
|
2342 |
T0 = env->CP0_EBase & 0x3ff;
|
2343 |
else
|
2344 |
CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
2345 |
RETURN(); |
2346 |
} |
2347 |
|
2348 |
void op_rdhwr_synci_step(void) |
2349 |
{ |
2350 |
if (!(env->hflags & MIPS_HFLAG_UM) ||
|
2351 |
(env->CP0_HWREna & (1 << 1)) || |
2352 |
(env->CP0_Status & (1 << CP0St_CU0)))
|
2353 |
T0 = env->SYNCI_Step; |
2354 |
else
|
2355 |
CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
2356 |
RETURN(); |
2357 |
} |
2358 |
|
2359 |
void op_rdhwr_cc(void) |
2360 |
{ |
2361 |
if (!(env->hflags & MIPS_HFLAG_UM) ||
|
2362 |
(env->CP0_HWREna & (1 << 2)) || |
2363 |
(env->CP0_Status & (1 << CP0St_CU0)))
|
2364 |
T0 = env->CP0_Count; |
2365 |
else
|
2366 |
CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
2367 |
RETURN(); |
2368 |
} |
2369 |
|
2370 |
void op_rdhwr_ccres(void) |
2371 |
{ |
2372 |
if (!(env->hflags & MIPS_HFLAG_UM) ||
|
2373 |
(env->CP0_HWREna & (1 << 3)) || |
2374 |
(env->CP0_Status & (1 << CP0St_CU0)))
|
2375 |
T0 = env->CCRes; |
2376 |
else
|
2377 |
CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
2378 |
RETURN(); |
2379 |
} |
2380 |
|
2381 |
void op_save_state (void) |
2382 |
{ |
2383 |
env->hflags = PARAM1; |
2384 |
RETURN(); |
2385 |
} |
2386 |
|
2387 |
void op_save_pc (void) |
2388 |
{ |
2389 |
env->PC = PARAM1; |
2390 |
RETURN(); |
2391 |
} |
2392 |
|
2393 |
void op_interrupt_restart (void) |
2394 |
{ |
2395 |
if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
2396 |
!(env->CP0_Status & (1 << CP0St_ERL)) &&
|
2397 |
!(env->hflags & MIPS_HFLAG_DM) && |
2398 |
(env->CP0_Status & (1 << CP0St_IE)) &&
|
2399 |
(env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) { |
2400 |
env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
|
2401 |
CALL_FROM_TB1(do_raise_exception, EXCP_EXT_INTERRUPT); |
2402 |
} |
2403 |
RETURN(); |
2404 |
} |
2405 |
|
2406 |
void op_raise_exception (void) |
2407 |
{ |
2408 |
CALL_FROM_TB1(do_raise_exception, PARAM1); |
2409 |
RETURN(); |
2410 |
} |
2411 |
|
2412 |
void op_raise_exception_err (void) |
2413 |
{ |
2414 |
CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2); |
2415 |
RETURN(); |
2416 |
} |
2417 |
|
2418 |
void op_exit_tb (void) |
2419 |
{ |
2420 |
EXIT_TB(); |
2421 |
RETURN(); |
2422 |
} |
2423 |
|
2424 |
void op_wait (void) |
2425 |
{ |
2426 |
env->halted = 1;
|
2427 |
CALL_FROM_TB1(do_raise_exception, EXCP_HLT); |
2428 |
RETURN(); |
2429 |
} |
2430 |
|
2431 |
/* Bitfield operations. */
|
2432 |
void op_ext(void) |
2433 |
{ |
2434 |
unsigned int pos = PARAM1; |
2435 |
unsigned int size = PARAM2; |
2436 |
|
2437 |
T0 = ((uint32_t)T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0); |
2438 |
RETURN(); |
2439 |
} |
2440 |
|
2441 |
void op_ins(void) |
2442 |
{ |
2443 |
unsigned int pos = PARAM1; |
2444 |
unsigned int size = PARAM2; |
2445 |
target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos; |
2446 |
|
2447 |
T0 = (T0 & ~mask) | (((uint32_t)T1 << pos) & mask); |
2448 |
RETURN(); |
2449 |
} |
2450 |
|
2451 |
void op_wsbh(void) |
2452 |
{ |
2453 |
T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF); |
2454 |
RETURN(); |
2455 |
} |
2456 |
|
2457 |
#ifdef TARGET_MIPS64
|
2458 |
void op_dext(void) |
2459 |
{ |
2460 |
unsigned int pos = PARAM1; |
2461 |
unsigned int size = PARAM2; |
2462 |
|
2463 |
T0 = (T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0); |
2464 |
RETURN(); |
2465 |
} |
2466 |
|
2467 |
void op_dins(void) |
2468 |
{ |
2469 |
unsigned int pos = PARAM1; |
2470 |
unsigned int size = PARAM2; |
2471 |
target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos; |
2472 |
|
2473 |
T0 = (T0 & ~mask) | ((T1 << pos) & mask); |
2474 |
RETURN(); |
2475 |
} |
2476 |
|
2477 |
void op_dsbh(void) |
2478 |
{ |
2479 |
T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL); |
2480 |
RETURN(); |
2481 |
} |
2482 |
|
2483 |
void op_dshd(void) |
2484 |
{ |
2485 |
T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL); |
2486 |
RETURN(); |
2487 |
} |
2488 |
#endif
|
2489 |
|
2490 |
void op_seb(void) |
2491 |
{ |
2492 |
T0 = ((T1 & 0xFF) ^ 0x80) - 0x80; |
2493 |
RETURN(); |
2494 |
} |
2495 |
|
2496 |
void op_seh(void) |
2497 |
{ |
2498 |
T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000; |
2499 |
RETURN(); |
2500 |
} |