root / hw / pci_bridge.c @ f4c817e0
History | View | Annotate | Download (7.3 kB)
1 |
/*
|
---|---|
2 |
* QEMU PCI bus manager
|
3 |
*
|
4 |
* Copyright (c) 2004 Fabrice Bellard
|
5 |
*
|
6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 |
* of this software and associated documentation files (the "Software"), to dea
|
8 |
|
9 |
* in the Software without restriction, including without limitation the rights
|
10 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
11 |
* copies of the Software, and to permit persons to whom the Software is
|
12 |
* furnished to do so, subject to the following conditions:
|
13 |
*
|
14 |
* The above copyright notice and this permission notice shall be included in
|
15 |
* all copies or substantial portions of the Software.
|
16 |
*
|
17 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
18 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
19 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
20 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
21 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM
|
22 |
|
23 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
24 |
* THE SOFTWARE.
|
25 |
*/
|
26 |
/*
|
27 |
* split out from pci.c
|
28 |
* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
|
29 |
* VA Linux Systems Japan K.K.
|
30 |
*/
|
31 |
|
32 |
#include "pci_bridge.h" |
33 |
#include "pci_internals.h" |
34 |
|
35 |
/* PCI bridge subsystem vendor ID helper functions */
|
36 |
#define PCI_SSVID_SIZEOF 8 |
37 |
#define PCI_SSVID_SVID 4 |
38 |
#define PCI_SSVID_SSID 6 |
39 |
|
40 |
int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
|
41 |
uint16_t svid, uint16_t ssid) |
42 |
{ |
43 |
int pos;
|
44 |
pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SIZEOF); |
45 |
if (pos < 0) { |
46 |
return pos;
|
47 |
} |
48 |
|
49 |
pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid); |
50 |
pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid); |
51 |
return pos;
|
52 |
} |
53 |
|
54 |
/* Accessor function to get parent bridge device from pci bus. */
|
55 |
PCIDevice *pci_bridge_get_device(PCIBus *bus) |
56 |
{ |
57 |
return bus->parent_dev;
|
58 |
} |
59 |
|
60 |
/* Accessor function to get secondary bus from pci-to-pci bridge device */
|
61 |
PCIBus *pci_bridge_get_sec_bus(PCIBridge *br) |
62 |
{ |
63 |
return &br->sec_bus;
|
64 |
} |
65 |
|
66 |
static uint32_t pci_config_get_io_base(const PCIDevice *d, |
67 |
uint32_t base, uint32_t base_upper16) |
68 |
{ |
69 |
uint32_t val; |
70 |
|
71 |
val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
|
72 |
if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
|
73 |
val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
|
74 |
} |
75 |
return val;
|
76 |
} |
77 |
|
78 |
static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base) |
79 |
{ |
80 |
return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
|
81 |
<< 16;
|
82 |
} |
83 |
|
84 |
static pcibus_t pci_config_get_pref_base(const PCIDevice *d, |
85 |
uint32_t base, uint32_t upper) |
86 |
{ |
87 |
pcibus_t tmp; |
88 |
pcibus_t val; |
89 |
|
90 |
tmp = (pcibus_t)pci_get_word(d->config + base); |
91 |
val = (tmp & PCI_PREF_RANGE_MASK) << 16;
|
92 |
if (tmp & PCI_PREF_RANGE_TYPE_64) {
|
93 |
val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
|
94 |
} |
95 |
return val;
|
96 |
} |
97 |
|
98 |
/* accessor function to get bridge filtering base address */
|
99 |
pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type)
|
100 |
{ |
101 |
pcibus_t base; |
102 |
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
103 |
base = pci_config_get_io_base(bridge, |
104 |
PCI_IO_BASE, PCI_IO_BASE_UPPER16); |
105 |
} else {
|
106 |
if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
|
107 |
base = pci_config_get_pref_base( |
108 |
bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32); |
109 |
} else {
|
110 |
base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE); |
111 |
} |
112 |
} |
113 |
|
114 |
return base;
|
115 |
} |
116 |
|
117 |
/* accessor funciton to get bridge filtering limit */
|
118 |
pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type)
|
119 |
{ |
120 |
pcibus_t limit; |
121 |
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
122 |
limit = pci_config_get_io_base(bridge, |
123 |
PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16); |
124 |
limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */ |
125 |
} else {
|
126 |
if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
|
127 |
limit = pci_config_get_pref_base( |
128 |
bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32); |
129 |
} else {
|
130 |
limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT); |
131 |
} |
132 |
limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */ |
133 |
} |
134 |
return limit;
|
135 |
} |
136 |
|
137 |
/* default write_config function for PCI-to-PCI bridge */
|
138 |
void pci_bridge_write_config(PCIDevice *d,
|
139 |
uint32_t address, uint32_t val, int len)
|
140 |
{ |
141 |
pci_default_write_config(d, address, val, len); |
142 |
|
143 |
if (/* io base/limit */ |
144 |
ranges_overlap(address, len, PCI_IO_BASE, 2) ||
|
145 |
|
146 |
/* memory base/limit, prefetchable base/limit and
|
147 |
io base/limit upper 16 */
|
148 |
ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
|
149 |
PCIBridge *s = container_of(d, PCIBridge, dev); |
150 |
pci_bridge_update_mappings(&s->sec_bus); |
151 |
} |
152 |
} |
153 |
|
154 |
/* reset bridge specific configuration registers */
|
155 |
void pci_bridge_reset_reg(PCIDevice *dev)
|
156 |
{ |
157 |
uint8_t *conf = dev->config; |
158 |
|
159 |
conf[PCI_PRIMARY_BUS] = 0;
|
160 |
conf[PCI_SECONDARY_BUS] = 0;
|
161 |
conf[PCI_SUBORDINATE_BUS] = 0;
|
162 |
conf[PCI_SEC_LATENCY_TIMER] = 0;
|
163 |
|
164 |
conf[PCI_IO_BASE] = 0;
|
165 |
conf[PCI_IO_LIMIT] = 0;
|
166 |
pci_set_word(conf + PCI_MEMORY_BASE, 0);
|
167 |
pci_set_word(conf + PCI_MEMORY_LIMIT, 0);
|
168 |
pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0);
|
169 |
pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0);
|
170 |
pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0);
|
171 |
pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0);
|
172 |
|
173 |
pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
|
174 |
} |
175 |
|
176 |
/* default reset function for PCI-to-PCI bridge */
|
177 |
void pci_bridge_reset(DeviceState *qdev)
|
178 |
{ |
179 |
PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev); |
180 |
pci_bridge_reset_reg(dev); |
181 |
} |
182 |
|
183 |
/* default qdev initialization function for PCI-to-PCI bridge */
|
184 |
int pci_bridge_initfn(PCIDevice *dev)
|
185 |
{ |
186 |
PCIBus *parent = dev->bus; |
187 |
PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev); |
188 |
PCIBus *sec_bus = &br->sec_bus; |
189 |
|
190 |
pci_set_word(dev->config + PCI_STATUS, |
191 |
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); |
192 |
pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI); |
193 |
dev->config[PCI_HEADER_TYPE] = |
194 |
(dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) | |
195 |
PCI_HEADER_TYPE_BRIDGE; |
196 |
pci_set_word(dev->config + PCI_SEC_STATUS, |
197 |
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); |
198 |
|
199 |
qbus_create_inplace(&sec_bus->qbus, &pci_bus_info, &dev->qdev, |
200 |
br->bus_name); |
201 |
sec_bus->parent_dev = dev; |
202 |
sec_bus->map_irq = br->map_irq; |
203 |
|
204 |
QLIST_INIT(&sec_bus->child); |
205 |
QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling); |
206 |
return 0; |
207 |
} |
208 |
|
209 |
/* default qdev clean up function for PCI-to-PCI bridge */
|
210 |
int pci_bridge_exitfn(PCIDevice *pci_dev)
|
211 |
{ |
212 |
PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev); |
213 |
assert(QLIST_EMPTY(&s->sec_bus.child)); |
214 |
QLIST_REMOVE(&s->sec_bus, sibling); |
215 |
/* qbus_free() is called automatically by qdev_free() */
|
216 |
return 0; |
217 |
} |
218 |
|
219 |
/*
|
220 |
* before qdev initialization(qdev_init()), this function sets bus_name and
|
221 |
* map_irq callback which are necessry for pci_bridge_initfn() to
|
222 |
* initialize bus.
|
223 |
*/
|
224 |
void pci_bridge_map_irq(PCIBridge *br, const char* bus_name, |
225 |
pci_map_irq_fn map_irq) |
226 |
{ |
227 |
br->map_irq = map_irq; |
228 |
br->bus_name = bus_name; |
229 |
} |