root / tcg / sparc / tcg-target.c @ f54b3f92
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1 | 8289b279 | blueswir1 | /*
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2 | 8289b279 | blueswir1 | * Tiny Code Generator for QEMU
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3 | 8289b279 | blueswir1 | *
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4 | 8289b279 | blueswir1 | * Copyright (c) 2008 Fabrice Bellard
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5 | 8289b279 | blueswir1 | *
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6 | 8289b279 | blueswir1 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 8289b279 | blueswir1 | * of this software and associated documentation files (the "Software"), to deal
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8 | 8289b279 | blueswir1 | * in the Software without restriction, including without limitation the rights
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9 | 8289b279 | blueswir1 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 8289b279 | blueswir1 | * copies of the Software, and to permit persons to whom the Software is
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11 | 8289b279 | blueswir1 | * furnished to do so, subject to the following conditions:
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12 | 8289b279 | blueswir1 | *
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13 | 8289b279 | blueswir1 | * The above copyright notice and this permission notice shall be included in
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14 | 8289b279 | blueswir1 | * all copies or substantial portions of the Software.
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15 | 8289b279 | blueswir1 | *
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16 | 8289b279 | blueswir1 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 8289b279 | blueswir1 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 8289b279 | blueswir1 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 8289b279 | blueswir1 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 8289b279 | blueswir1 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 8289b279 | blueswir1 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 8289b279 | blueswir1 | * THE SOFTWARE.
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23 | 8289b279 | blueswir1 | */
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24 | 8289b279 | blueswir1 | |
25 | 8289b279 | blueswir1 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
26 | 8289b279 | blueswir1 | "%g0",
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27 | 8289b279 | blueswir1 | "%g1",
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28 | 8289b279 | blueswir1 | "%g2",
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29 | 8289b279 | blueswir1 | "%g3",
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30 | 8289b279 | blueswir1 | "%g4",
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31 | 8289b279 | blueswir1 | "%g5",
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32 | 8289b279 | blueswir1 | "%g6",
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33 | 8289b279 | blueswir1 | "%g7",
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34 | 8289b279 | blueswir1 | "%o0",
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35 | 8289b279 | blueswir1 | "%o1",
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36 | 8289b279 | blueswir1 | "%o2",
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37 | 8289b279 | blueswir1 | "%o3",
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38 | 8289b279 | blueswir1 | "%o4",
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39 | 8289b279 | blueswir1 | "%o5",
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40 | 8289b279 | blueswir1 | "%o6",
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41 | 8289b279 | blueswir1 | "%o7",
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42 | 8289b279 | blueswir1 | "%l0",
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43 | 8289b279 | blueswir1 | "%l1",
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44 | 8289b279 | blueswir1 | "%l2",
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45 | 8289b279 | blueswir1 | "%l3",
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46 | 8289b279 | blueswir1 | "%l4",
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47 | 8289b279 | blueswir1 | "%l5",
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48 | 8289b279 | blueswir1 | "%l6",
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49 | 8289b279 | blueswir1 | "%l7",
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50 | 8289b279 | blueswir1 | "%i0",
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51 | 8289b279 | blueswir1 | "%i1",
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52 | 8289b279 | blueswir1 | "%i2",
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53 | 8289b279 | blueswir1 | "%i3",
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54 | 8289b279 | blueswir1 | "%i4",
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55 | 8289b279 | blueswir1 | "%i5",
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56 | 8289b279 | blueswir1 | "%i6",
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57 | 8289b279 | blueswir1 | "%i7",
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58 | 8289b279 | blueswir1 | }; |
59 | 8289b279 | blueswir1 | |
60 | 0954d0d9 | blueswir1 | static const int tcg_target_reg_alloc_order[] = { |
61 | 8289b279 | blueswir1 | TCG_REG_L0, |
62 | 8289b279 | blueswir1 | TCG_REG_L1, |
63 | 8289b279 | blueswir1 | TCG_REG_L2, |
64 | 8289b279 | blueswir1 | TCG_REG_L3, |
65 | 8289b279 | blueswir1 | TCG_REG_L4, |
66 | 8289b279 | blueswir1 | TCG_REG_L5, |
67 | 8289b279 | blueswir1 | TCG_REG_L6, |
68 | 8289b279 | blueswir1 | TCG_REG_L7, |
69 | 8289b279 | blueswir1 | TCG_REG_I0, |
70 | 8289b279 | blueswir1 | TCG_REG_I1, |
71 | 8289b279 | blueswir1 | TCG_REG_I2, |
72 | 8289b279 | blueswir1 | TCG_REG_I3, |
73 | 8289b279 | blueswir1 | TCG_REG_I4, |
74 | 8289b279 | blueswir1 | }; |
75 | 8289b279 | blueswir1 | |
76 | 8289b279 | blueswir1 | static const int tcg_target_call_iarg_regs[6] = { |
77 | 8289b279 | blueswir1 | TCG_REG_O0, |
78 | 8289b279 | blueswir1 | TCG_REG_O1, |
79 | 8289b279 | blueswir1 | TCG_REG_O2, |
80 | 8289b279 | blueswir1 | TCG_REG_O3, |
81 | 8289b279 | blueswir1 | TCG_REG_O4, |
82 | 8289b279 | blueswir1 | TCG_REG_O5, |
83 | 8289b279 | blueswir1 | }; |
84 | 8289b279 | blueswir1 | |
85 | 8289b279 | blueswir1 | static const int tcg_target_call_oarg_regs[2] = { |
86 | 8289b279 | blueswir1 | TCG_REG_O0, |
87 | 8289b279 | blueswir1 | TCG_REG_O1, |
88 | 8289b279 | blueswir1 | }; |
89 | 8289b279 | blueswir1 | |
90 | 8289b279 | blueswir1 | static void patch_reloc(uint8_t *code_ptr, int type, |
91 | f54b3f92 | aurel32 | tcg_target_long value, tcg_target_long addend) |
92 | 8289b279 | blueswir1 | { |
93 | f54b3f92 | aurel32 | value += addend; |
94 | 8289b279 | blueswir1 | switch (type) {
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95 | 8289b279 | blueswir1 | case R_SPARC_32:
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96 | 8289b279 | blueswir1 | if (value != (uint32_t)value)
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97 | 8289b279 | blueswir1 | tcg_abort(); |
98 | 8289b279 | blueswir1 | *(uint32_t *)code_ptr = value; |
99 | 8289b279 | blueswir1 | break;
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100 | 8289b279 | blueswir1 | default:
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101 | 8289b279 | blueswir1 | tcg_abort(); |
102 | 8289b279 | blueswir1 | } |
103 | 8289b279 | blueswir1 | } |
104 | 8289b279 | blueswir1 | |
105 | 8289b279 | blueswir1 | /* maximum number of register used for input function arguments */
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106 | 8289b279 | blueswir1 | static inline int tcg_target_get_call_iarg_regs_count(int flags) |
107 | 8289b279 | blueswir1 | { |
108 | 8289b279 | blueswir1 | return 6; |
109 | 8289b279 | blueswir1 | } |
110 | 8289b279 | blueswir1 | |
111 | 8289b279 | blueswir1 | /* parse target specific constraints */
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112 | 8289b279 | blueswir1 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
113 | 8289b279 | blueswir1 | { |
114 | 8289b279 | blueswir1 | const char *ct_str; |
115 | 8289b279 | blueswir1 | |
116 | 8289b279 | blueswir1 | ct_str = *pct_str; |
117 | 8289b279 | blueswir1 | switch (ct_str[0]) { |
118 | 8289b279 | blueswir1 | case 'r': |
119 | 8289b279 | blueswir1 | case 'L': /* qemu_ld/st constraint */ |
120 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_REG; |
121 | 8289b279 | blueswir1 | tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
122 | 8289b279 | blueswir1 | break;
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123 | 8289b279 | blueswir1 | case 'I': |
124 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_CONST_S11; |
125 | 8289b279 | blueswir1 | break;
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126 | 8289b279 | blueswir1 | case 'J': |
127 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_CONST_S13; |
128 | 8289b279 | blueswir1 | break;
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129 | 8289b279 | blueswir1 | default:
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130 | 8289b279 | blueswir1 | return -1; |
131 | 8289b279 | blueswir1 | } |
132 | 8289b279 | blueswir1 | ct_str++; |
133 | 8289b279 | blueswir1 | *pct_str = ct_str; |
134 | 8289b279 | blueswir1 | return 0; |
135 | 8289b279 | blueswir1 | } |
136 | 8289b279 | blueswir1 | |
137 | 8289b279 | blueswir1 | #define ABS(x) ((x) < 0? -(x) : (x)) |
138 | 8289b279 | blueswir1 | /* test if a constant matches the constraint */
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139 | 8289b279 | blueswir1 | static inline int tcg_target_const_match(tcg_target_long val, |
140 | 8289b279 | blueswir1 | const TCGArgConstraint *arg_ct)
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141 | 8289b279 | blueswir1 | { |
142 | 8289b279 | blueswir1 | int ct;
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143 | 8289b279 | blueswir1 | |
144 | 8289b279 | blueswir1 | ct = arg_ct->ct; |
145 | 8289b279 | blueswir1 | if (ct & TCG_CT_CONST)
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146 | 8289b279 | blueswir1 | return 1; |
147 | 8289b279 | blueswir1 | else if ((ct & TCG_CT_CONST_S11) && ABS(val) == (ABS(val) & 0x3ff)) |
148 | 8289b279 | blueswir1 | return 1; |
149 | 8289b279 | blueswir1 | else if ((ct & TCG_CT_CONST_S13) && ABS(val) == (ABS(val) & 0xfff)) |
150 | 8289b279 | blueswir1 | return 1; |
151 | 8289b279 | blueswir1 | else
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152 | 8289b279 | blueswir1 | return 0; |
153 | 8289b279 | blueswir1 | } |
154 | 8289b279 | blueswir1 | |
155 | 8289b279 | blueswir1 | #define INSN_OP(x) ((x) << 30) |
156 | 8289b279 | blueswir1 | #define INSN_OP2(x) ((x) << 22) |
157 | 8289b279 | blueswir1 | #define INSN_OP3(x) ((x) << 19) |
158 | 8289b279 | blueswir1 | #define INSN_OPF(x) ((x) << 5) |
159 | 8289b279 | blueswir1 | #define INSN_RD(x) ((x) << 25) |
160 | 8289b279 | blueswir1 | #define INSN_RS1(x) ((x) << 14) |
161 | 8289b279 | blueswir1 | #define INSN_RS2(x) (x)
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162 | 8289b279 | blueswir1 | |
163 | 8289b279 | blueswir1 | #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) |
164 | b3db8758 | blueswir1 | #define INSN_OFF22(x) (((x) >> 2) & 0x3fffff) |
165 | 8289b279 | blueswir1 | |
166 | b3db8758 | blueswir1 | #define INSN_COND(x, a) (((x) << 25) | ((a) << 29)) |
167 | b3db8758 | blueswir1 | #define COND_A 0x8 |
168 | b3db8758 | blueswir1 | #define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2)) |
169 | 8289b279 | blueswir1 | |
170 | 8289b279 | blueswir1 | #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) |
171 | 8289b279 | blueswir1 | #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) |
172 | 8289b279 | blueswir1 | #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) |
173 | 8289b279 | blueswir1 | #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) |
174 | 8289b279 | blueswir1 | #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x08)) |
175 | 8289b279 | blueswir1 | #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10)) |
176 | 8289b279 | blueswir1 | #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c)) |
177 | 8289b279 | blueswir1 | #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) |
178 | 8289b279 | blueswir1 | #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) |
179 | 8289b279 | blueswir1 | #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) |
180 | 8289b279 | blueswir1 | #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) |
181 | 8289b279 | blueswir1 | #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) |
182 | 8289b279 | blueswir1 | #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) |
183 | 8289b279 | blueswir1 | |
184 | 8289b279 | blueswir1 | #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) |
185 | 8289b279 | blueswir1 | #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) |
186 | 8289b279 | blueswir1 | #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) |
187 | 8289b279 | blueswir1 | |
188 | 8289b279 | blueswir1 | #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) |
189 | 8289b279 | blueswir1 | #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) |
190 | 8289b279 | blueswir1 | #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) |
191 | 8289b279 | blueswir1 | |
192 | 8289b279 | blueswir1 | #define WRY (INSN_OP(2) | INSN_OP3(0x30)) |
193 | 8289b279 | blueswir1 | #define JMPL (INSN_OP(2) | INSN_OP3(0x38)) |
194 | 8289b279 | blueswir1 | #define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) |
195 | 8289b279 | blueswir1 | #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) |
196 | 8289b279 | blueswir1 | #define SETHI (INSN_OP(0) | INSN_OP2(0x4)) |
197 | 8289b279 | blueswir1 | #define CALL INSN_OP(1) |
198 | 8289b279 | blueswir1 | #define LDUB (INSN_OP(3) | INSN_OP3(0x01)) |
199 | 8289b279 | blueswir1 | #define LDSB (INSN_OP(3) | INSN_OP3(0x09)) |
200 | 8289b279 | blueswir1 | #define LDUH (INSN_OP(3) | INSN_OP3(0x02)) |
201 | 8289b279 | blueswir1 | #define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) |
202 | 8289b279 | blueswir1 | #define LDUW (INSN_OP(3) | INSN_OP3(0x00)) |
203 | 8289b279 | blueswir1 | #define LDSW (INSN_OP(3) | INSN_OP3(0x08)) |
204 | 8289b279 | blueswir1 | #define LDX (INSN_OP(3) | INSN_OP3(0x0b)) |
205 | 8289b279 | blueswir1 | #define STB (INSN_OP(3) | INSN_OP3(0x05)) |
206 | 8289b279 | blueswir1 | #define STH (INSN_OP(3) | INSN_OP3(0x06)) |
207 | 8289b279 | blueswir1 | #define STW (INSN_OP(3) | INSN_OP3(0x04)) |
208 | 8289b279 | blueswir1 | #define STX (INSN_OP(3) | INSN_OP3(0x0e)) |
209 | 8289b279 | blueswir1 | |
210 | 8289b279 | blueswir1 | static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
211 | 8289b279 | blueswir1 | { |
212 | 8289b279 | blueswir1 | tcg_out32(s, ARITH_OR | INSN_RD(ret) | INSN_RS1(arg) | |
213 | 8289b279 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
214 | 8289b279 | blueswir1 | } |
215 | 8289b279 | blueswir1 | |
216 | 8289b279 | blueswir1 | static inline void tcg_out_movi(TCGContext *s, TCGType type, |
217 | 8289b279 | blueswir1 | int ret, tcg_target_long arg)
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218 | 8289b279 | blueswir1 | { |
219 | b3db8758 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
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220 | b3db8758 | blueswir1 | if (arg != (arg & 0xffffffff)) |
221 | b3db8758 | blueswir1 | fprintf(stderr, "unimplemented %s with constant %ld\n", __func__, arg);
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222 | b3db8758 | blueswir1 | #endif
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223 | 8289b279 | blueswir1 | if (arg == (arg & 0xfff)) |
224 | 2f0a5008 | blueswir1 | tcg_out32(s, ARITH_OR | INSN_RD(ret) | INSN_RS1(TCG_REG_G0) | |
225 | 8289b279 | blueswir1 | INSN_IMM13(arg)); |
226 | 8289b279 | blueswir1 | else {
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227 | 8289b279 | blueswir1 | tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); |
228 | 8289b279 | blueswir1 | if (arg & 0x3ff) |
229 | 8289b279 | blueswir1 | tcg_out32(s, ARITH_OR | INSN_RD(ret) | INSN_RS1(ret) | |
230 | 8289b279 | blueswir1 | INSN_IMM13(arg & 0x3ff));
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231 | 8289b279 | blueswir1 | } |
232 | 8289b279 | blueswir1 | } |
233 | 8289b279 | blueswir1 | |
234 | 8289b279 | blueswir1 | static inline void tcg_out_ld_raw(TCGContext *s, int ret, |
235 | 8289b279 | blueswir1 | tcg_target_long arg) |
236 | 8289b279 | blueswir1 | { |
237 | 8289b279 | blueswir1 | tcg_out32(s, SETHI | INSN_RD(ret) | (((uint32_t)arg & 0xfffffc00) >> 10)); |
238 | 8289b279 | blueswir1 | tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | |
239 | 8289b279 | blueswir1 | INSN_IMM13(arg & 0x3ff));
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240 | 8289b279 | blueswir1 | } |
241 | 8289b279 | blueswir1 | |
242 | b3db8758 | blueswir1 | static inline void tcg_out_ld_ptr(TCGContext *s, int ret, |
243 | b3db8758 | blueswir1 | tcg_target_long arg) |
244 | b3db8758 | blueswir1 | { |
245 | b3db8758 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
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246 | b3db8758 | blueswir1 | if (arg != (arg & 0xffffffff)) |
247 | b3db8758 | blueswir1 | fprintf(stderr, "unimplemented %s with offset %ld\n", __func__, arg);
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248 | b3db8758 | blueswir1 | if (arg != (arg & 0xfff)) |
249 | b3db8758 | blueswir1 | tcg_out32(s, SETHI | INSN_RD(ret) | (((uint32_t)arg & 0xfffffc00) >> 10)); |
250 | b3db8758 | blueswir1 | tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) | |
251 | b3db8758 | blueswir1 | INSN_IMM13(arg & 0x3ff));
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252 | b3db8758 | blueswir1 | #else
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253 | b3db8758 | blueswir1 | tcg_out_ld_raw(s, ret, arg); |
254 | b3db8758 | blueswir1 | #endif
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255 | b3db8758 | blueswir1 | } |
256 | b3db8758 | blueswir1 | |
257 | 8289b279 | blueswir1 | static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op) |
258 | 8289b279 | blueswir1 | { |
259 | 8289b279 | blueswir1 | if (offset == (offset & 0xfff)) |
260 | 8289b279 | blueswir1 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | |
261 | 8289b279 | blueswir1 | INSN_IMM13(offset)); |
262 | 8289b279 | blueswir1 | else
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263 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented %s with offset %d\n", __func__, offset);
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264 | 8289b279 | blueswir1 | } |
265 | 8289b279 | blueswir1 | |
266 | e4d5434c | blueswir1 | static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, |
267 | 8289b279 | blueswir1 | int arg1, tcg_target_long arg2)
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268 | 8289b279 | blueswir1 | { |
269 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented %s\n", __func__);
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270 | 8289b279 | blueswir1 | } |
271 | 8289b279 | blueswir1 | |
272 | e4d5434c | blueswir1 | static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, |
273 | 8289b279 | blueswir1 | int arg1, tcg_target_long arg2)
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274 | 8289b279 | blueswir1 | { |
275 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented %s\n", __func__);
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276 | 8289b279 | blueswir1 | } |
277 | 8289b279 | blueswir1 | |
278 | 8289b279 | blueswir1 | static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2, |
279 | 8289b279 | blueswir1 | int op)
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280 | 8289b279 | blueswir1 | { |
281 | 8289b279 | blueswir1 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
282 | 8289b279 | blueswir1 | INSN_RS2(rs2)); |
283 | 8289b279 | blueswir1 | } |
284 | 8289b279 | blueswir1 | |
285 | 8289b279 | blueswir1 | static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1, int offset, |
286 | 8289b279 | blueswir1 | int op)
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287 | 8289b279 | blueswir1 | { |
288 | 8289b279 | blueswir1 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
289 | 8289b279 | blueswir1 | INSN_IMM13(offset)); |
290 | 8289b279 | blueswir1 | } |
291 | 8289b279 | blueswir1 | |
292 | 8289b279 | blueswir1 | static inline void tcg_out_sety(TCGContext *s, tcg_target_long val) |
293 | 8289b279 | blueswir1 | { |
294 | 8289b279 | blueswir1 | if (val == 0 || val == -1) |
295 | 8289b279 | blueswir1 | tcg_out32(s, WRY | INSN_IMM13(val)); |
296 | 8289b279 | blueswir1 | else
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297 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented sety %ld\n", (long)val); |
298 | 8289b279 | blueswir1 | } |
299 | 8289b279 | blueswir1 | |
300 | 8289b279 | blueswir1 | static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
301 | 8289b279 | blueswir1 | { |
302 | 8289b279 | blueswir1 | if (val != 0) { |
303 | 8289b279 | blueswir1 | if (val == (val & 0xfff)) |
304 | 8289b279 | blueswir1 | tcg_out_arithi(s, reg, reg, val, ARITH_ADD); |
305 | 8289b279 | blueswir1 | else
|
306 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented addi %ld\n", (long)val); |
307 | 8289b279 | blueswir1 | } |
308 | 8289b279 | blueswir1 | } |
309 | 8289b279 | blueswir1 | |
310 | 8289b279 | blueswir1 | static inline void tcg_out_nop(TCGContext *s) |
311 | 8289b279 | blueswir1 | { |
312 | 8289b279 | blueswir1 | tcg_out32(s, SETHI | INSN_RD(TCG_REG_G0) | 0);
|
313 | 8289b279 | blueswir1 | } |
314 | 8289b279 | blueswir1 | |
315 | b3db8758 | blueswir1 | static inline void tcg_target_prologue(TCGContext *s) |
316 | b3db8758 | blueswir1 | { |
317 | b3db8758 | blueswir1 | tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | |
318 | b3db8758 | blueswir1 | INSN_IMM13(-TCG_TARGET_STACK_MINFRAME)); |
319 | b3db8758 | blueswir1 | } |
320 | b3db8758 | blueswir1 | |
321 | 8289b279 | blueswir1 | static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, |
322 | 8289b279 | blueswir1 | const int *const_args) |
323 | 8289b279 | blueswir1 | { |
324 | 8289b279 | blueswir1 | int c;
|
325 | 8289b279 | blueswir1 | |
326 | 8289b279 | blueswir1 | switch (opc) {
|
327 | 8289b279 | blueswir1 | case INDEX_op_exit_tb:
|
328 | b3db8758 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
|
329 | b3db8758 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) | |
330 | 8289b279 | blueswir1 | INSN_IMM13(8));
|
331 | b3db8758 | blueswir1 | tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) | |
332 | b3db8758 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
333 | 8289b279 | blueswir1 | break;
|
334 | 8289b279 | blueswir1 | case INDEX_op_goto_tb:
|
335 | 8289b279 | blueswir1 | if (s->tb_jmp_offset) {
|
336 | 8289b279 | blueswir1 | /* direct jump method */
|
337 | b3db8758 | blueswir1 | if (ABS(args[0] - (unsigned long)s->code_ptr) == |
338 | b3db8758 | blueswir1 | (ABS(args[0] - (unsigned long)s->code_ptr) & 0x1fffff)) { |
339 | b3db8758 | blueswir1 | tcg_out32(s, BA | |
340 | b3db8758 | blueswir1 | INSN_OFF22(args[0] - (unsigned long)s->code_ptr)); |
341 | b3db8758 | blueswir1 | } else {
|
342 | b3db8758 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, args[0]);
|
343 | b3db8758 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) | |
344 | b3db8758 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
345 | b3db8758 | blueswir1 | } |
346 | 8289b279 | blueswir1 | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
347 | 8289b279 | blueswir1 | } else {
|
348 | 8289b279 | blueswir1 | /* indirect jump method */
|
349 | b3db8758 | blueswir1 | tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
|
350 | b3db8758 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) | |
351 | b3db8758 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
352 | 8289b279 | blueswir1 | } |
353 | 53cd9273 | blueswir1 | tcg_out_nop(s); |
354 | 8289b279 | blueswir1 | s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
355 | 8289b279 | blueswir1 | break;
|
356 | 8289b279 | blueswir1 | case INDEX_op_call:
|
357 | 8289b279 | blueswir1 | if (const_args[0]) { |
358 | 8289b279 | blueswir1 | tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
|
359 | 8289b279 | blueswir1 | - (tcg_target_ulong)s->code_ptr) >> 2)
|
360 | 8289b279 | blueswir1 | & 0x3fffffff));
|
361 | 8289b279 | blueswir1 | tcg_out_nop(s); |
362 | 8289b279 | blueswir1 | } else {
|
363 | b3db8758 | blueswir1 | tcg_out_ld_ptr(s, TCG_REG_O7, (tcg_target_long)(s->tb_next + args[0]));
|
364 | 8289b279 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_O7) | |
365 | 2f0a5008 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
366 | 8289b279 | blueswir1 | tcg_out_nop(s); |
367 | 8289b279 | blueswir1 | } |
368 | 8289b279 | blueswir1 | break;
|
369 | 8289b279 | blueswir1 | case INDEX_op_jmp:
|
370 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented jmp\n");
|
371 | 8289b279 | blueswir1 | break;
|
372 | 8289b279 | blueswir1 | case INDEX_op_br:
|
373 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented br\n");
|
374 | 8289b279 | blueswir1 | break;
|
375 | 8289b279 | blueswir1 | case INDEX_op_movi_i32:
|
376 | 8289b279 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); |
377 | 8289b279 | blueswir1 | break;
|
378 | 8289b279 | blueswir1 | |
379 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
380 | 8289b279 | blueswir1 | #define OP_32_64(x) \
|
381 | 8289b279 | blueswir1 | glue(glue(case INDEX_op_, x), _i32:) \
|
382 | 8289b279 | blueswir1 | glue(glue(case INDEX_op_, x), _i64:)
|
383 | 8289b279 | blueswir1 | #else
|
384 | 8289b279 | blueswir1 | #define OP_32_64(x) \
|
385 | 8289b279 | blueswir1 | glue(glue(case INDEX_op_, x), _i32:)
|
386 | 8289b279 | blueswir1 | #endif
|
387 | 8289b279 | blueswir1 | OP_32_64(ld8u); |
388 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUB); |
389 | 8289b279 | blueswir1 | break;
|
390 | 8289b279 | blueswir1 | OP_32_64(ld8s); |
391 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSB); |
392 | 8289b279 | blueswir1 | break;
|
393 | 8289b279 | blueswir1 | OP_32_64(ld16u); |
394 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUH); |
395 | 8289b279 | blueswir1 | break;
|
396 | 8289b279 | blueswir1 | OP_32_64(ld16s); |
397 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSH); |
398 | 8289b279 | blueswir1 | break;
|
399 | 8289b279 | blueswir1 | case INDEX_op_ld_i32:
|
400 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
401 | 53cd9273 | blueswir1 | case INDEX_op_ld32u_i64:
|
402 | 8289b279 | blueswir1 | #endif
|
403 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUW); |
404 | 8289b279 | blueswir1 | break;
|
405 | 8289b279 | blueswir1 | OP_32_64(st8); |
406 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STB); |
407 | 8289b279 | blueswir1 | break;
|
408 | 8289b279 | blueswir1 | OP_32_64(st16); |
409 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STH); |
410 | 8289b279 | blueswir1 | break;
|
411 | 8289b279 | blueswir1 | case INDEX_op_st_i32:
|
412 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
413 | 53cd9273 | blueswir1 | case INDEX_op_st32_i64:
|
414 | 8289b279 | blueswir1 | #endif
|
415 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STW); |
416 | 8289b279 | blueswir1 | break;
|
417 | 53cd9273 | blueswir1 | OP_32_64(add); |
418 | 53cd9273 | blueswir1 | c = ARITH_ADD; |
419 | 53cd9273 | blueswir1 | goto gen_arith32;
|
420 | 8289b279 | blueswir1 | OP_32_64(sub); |
421 | 8289b279 | blueswir1 | c = ARITH_SUB; |
422 | 8289b279 | blueswir1 | goto gen_arith32;
|
423 | 8289b279 | blueswir1 | OP_32_64(and); |
424 | 8289b279 | blueswir1 | c = ARITH_AND; |
425 | 8289b279 | blueswir1 | goto gen_arith32;
|
426 | 8289b279 | blueswir1 | OP_32_64(or); |
427 | 8289b279 | blueswir1 | c = ARITH_OR; |
428 | 8289b279 | blueswir1 | goto gen_arith32;
|
429 | 8289b279 | blueswir1 | OP_32_64(xor); |
430 | 8289b279 | blueswir1 | c = ARITH_XOR; |
431 | 8289b279 | blueswir1 | goto gen_arith32;
|
432 | 8289b279 | blueswir1 | case INDEX_op_shl_i32:
|
433 | 8289b279 | blueswir1 | c = SHIFT_SLL; |
434 | 8289b279 | blueswir1 | goto gen_arith32;
|
435 | 8289b279 | blueswir1 | case INDEX_op_shr_i32:
|
436 | 8289b279 | blueswir1 | c = SHIFT_SRL; |
437 | 8289b279 | blueswir1 | goto gen_arith32;
|
438 | 8289b279 | blueswir1 | case INDEX_op_sar_i32:
|
439 | 8289b279 | blueswir1 | c = SHIFT_SRA; |
440 | 8289b279 | blueswir1 | goto gen_arith32;
|
441 | 8289b279 | blueswir1 | case INDEX_op_mul_i32:
|
442 | 8289b279 | blueswir1 | c = ARITH_UMUL; |
443 | 8289b279 | blueswir1 | goto gen_arith32;
|
444 | 8289b279 | blueswir1 | case INDEX_op_div2_i32:
|
445 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
|
446 | 8289b279 | blueswir1 | c = ARITH_SDIVX; |
447 | 8289b279 | blueswir1 | goto gen_arith32;
|
448 | 8289b279 | blueswir1 | #else
|
449 | 8289b279 | blueswir1 | tcg_out_sety(s, 0);
|
450 | 8289b279 | blueswir1 | c = ARITH_SDIV; |
451 | 8289b279 | blueswir1 | goto gen_arith32;
|
452 | 8289b279 | blueswir1 | #endif
|
453 | 8289b279 | blueswir1 | case INDEX_op_divu2_i32:
|
454 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
|
455 | 8289b279 | blueswir1 | c = ARITH_UDIVX; |
456 | 8289b279 | blueswir1 | goto gen_arith32;
|
457 | 8289b279 | blueswir1 | #else
|
458 | 8289b279 | blueswir1 | tcg_out_sety(s, 0);
|
459 | 8289b279 | blueswir1 | c = ARITH_UDIV; |
460 | 8289b279 | blueswir1 | goto gen_arith32;
|
461 | 8289b279 | blueswir1 | #endif
|
462 | 8289b279 | blueswir1 | |
463 | 8289b279 | blueswir1 | case INDEX_op_brcond_i32:
|
464 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented brcond\n");
|
465 | 8289b279 | blueswir1 | break;
|
466 | 8289b279 | blueswir1 | |
467 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld8u:
|
468 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented qld\n");
|
469 | 8289b279 | blueswir1 | break;
|
470 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld8s:
|
471 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented qld\n");
|
472 | 8289b279 | blueswir1 | break;
|
473 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld16u:
|
474 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented qld\n");
|
475 | 8289b279 | blueswir1 | break;
|
476 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld16s:
|
477 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented qld\n");
|
478 | 8289b279 | blueswir1 | break;
|
479 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld32u:
|
480 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented qld\n");
|
481 | 8289b279 | blueswir1 | break;
|
482 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld32s:
|
483 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented qld\n");
|
484 | 8289b279 | blueswir1 | break;
|
485 | 8289b279 | blueswir1 | case INDEX_op_qemu_st8:
|
486 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented qst\n");
|
487 | 8289b279 | blueswir1 | break;
|
488 | 8289b279 | blueswir1 | case INDEX_op_qemu_st16:
|
489 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented qst\n");
|
490 | 8289b279 | blueswir1 | break;
|
491 | 8289b279 | blueswir1 | case INDEX_op_qemu_st32:
|
492 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented qst\n");
|
493 | 8289b279 | blueswir1 | break;
|
494 | 8289b279 | blueswir1 | |
495 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
496 | 8289b279 | blueswir1 | case INDEX_op_movi_i64:
|
497 | 8289b279 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
498 | 8289b279 | blueswir1 | break;
|
499 | 53cd9273 | blueswir1 | case INDEX_op_ld32s_i64:
|
500 | 53cd9273 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSW); |
501 | 53cd9273 | blueswir1 | break;
|
502 | 8289b279 | blueswir1 | case INDEX_op_ld_i64:
|
503 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDX); |
504 | 8289b279 | blueswir1 | break;
|
505 | 8289b279 | blueswir1 | case INDEX_op_st_i64:
|
506 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STX); |
507 | 8289b279 | blueswir1 | break;
|
508 | 8289b279 | blueswir1 | case INDEX_op_shl_i64:
|
509 | 8289b279 | blueswir1 | c = SHIFT_SLLX; |
510 | 8289b279 | blueswir1 | goto gen_arith32;
|
511 | 8289b279 | blueswir1 | case INDEX_op_shr_i64:
|
512 | 8289b279 | blueswir1 | c = SHIFT_SRLX; |
513 | 8289b279 | blueswir1 | goto gen_arith32;
|
514 | 8289b279 | blueswir1 | case INDEX_op_sar_i64:
|
515 | 8289b279 | blueswir1 | c = SHIFT_SRAX; |
516 | 8289b279 | blueswir1 | goto gen_arith32;
|
517 | 8289b279 | blueswir1 | case INDEX_op_mul_i64:
|
518 | 8289b279 | blueswir1 | c = ARITH_MULX; |
519 | 8289b279 | blueswir1 | goto gen_arith32;
|
520 | 8289b279 | blueswir1 | case INDEX_op_div2_i64:
|
521 | 53cd9273 | blueswir1 | c = ARITH_SDIVX; |
522 | 8289b279 | blueswir1 | goto gen_arith32;
|
523 | 8289b279 | blueswir1 | case INDEX_op_divu2_i64:
|
524 | 8289b279 | blueswir1 | c = ARITH_UDIVX; |
525 | 8289b279 | blueswir1 | goto gen_arith32;
|
526 | 8289b279 | blueswir1 | |
527 | 8289b279 | blueswir1 | case INDEX_op_brcond_i64:
|
528 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented brcond\n");
|
529 | 8289b279 | blueswir1 | break;
|
530 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld64:
|
531 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented qld\n");
|
532 | 8289b279 | blueswir1 | break;
|
533 | 8289b279 | blueswir1 | case INDEX_op_qemu_st64:
|
534 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented qst\n");
|
535 | 8289b279 | blueswir1 | break;
|
536 | 8289b279 | blueswir1 | |
537 | 8289b279 | blueswir1 | #endif
|
538 | 53cd9273 | blueswir1 | gen_arith32:
|
539 | 53cd9273 | blueswir1 | if (const_args[2]) { |
540 | 53cd9273 | blueswir1 | tcg_out_arithi(s, args[0], args[1], args[2], c); |
541 | 53cd9273 | blueswir1 | } else {
|
542 | 53cd9273 | blueswir1 | tcg_out_arith(s, args[0], args[1], args[2], c); |
543 | 53cd9273 | blueswir1 | } |
544 | 53cd9273 | blueswir1 | break;
|
545 | 53cd9273 | blueswir1 | |
546 | 8289b279 | blueswir1 | default:
|
547 | 8289b279 | blueswir1 | fprintf(stderr, "unknown opcode 0x%x\n", opc);
|
548 | 8289b279 | blueswir1 | tcg_abort(); |
549 | 8289b279 | blueswir1 | } |
550 | 8289b279 | blueswir1 | } |
551 | 8289b279 | blueswir1 | |
552 | 8289b279 | blueswir1 | static const TCGTargetOpDef sparc_op_defs[] = { |
553 | 8289b279 | blueswir1 | { INDEX_op_exit_tb, { } }, |
554 | b3db8758 | blueswir1 | { INDEX_op_goto_tb, { } }, |
555 | 8289b279 | blueswir1 | { INDEX_op_call, { "ri" } },
|
556 | 8289b279 | blueswir1 | { INDEX_op_jmp, { "ri" } },
|
557 | 8289b279 | blueswir1 | { INDEX_op_br, { } }, |
558 | 8289b279 | blueswir1 | |
559 | 8289b279 | blueswir1 | { INDEX_op_mov_i32, { "r", "r" } }, |
560 | 8289b279 | blueswir1 | { INDEX_op_movi_i32, { "r" } },
|
561 | 8289b279 | blueswir1 | { INDEX_op_ld8u_i32, { "r", "r" } }, |
562 | 8289b279 | blueswir1 | { INDEX_op_ld8s_i32, { "r", "r" } }, |
563 | 8289b279 | blueswir1 | { INDEX_op_ld16u_i32, { "r", "r" } }, |
564 | 8289b279 | blueswir1 | { INDEX_op_ld16s_i32, { "r", "r" } }, |
565 | 8289b279 | blueswir1 | { INDEX_op_ld_i32, { "r", "r" } }, |
566 | 8289b279 | blueswir1 | { INDEX_op_st8_i32, { "r", "r" } }, |
567 | 8289b279 | blueswir1 | { INDEX_op_st16_i32, { "r", "r" } }, |
568 | 8289b279 | blueswir1 | { INDEX_op_st_i32, { "r", "r" } }, |
569 | 8289b279 | blueswir1 | |
570 | 53cd9273 | blueswir1 | { INDEX_op_add_i32, { "r", "r", "rJ" } }, |
571 | 53cd9273 | blueswir1 | { INDEX_op_mul_i32, { "r", "r", "rJ" } }, |
572 | 8289b279 | blueswir1 | { INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } }, |
573 | 8289b279 | blueswir1 | { INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } }, |
574 | 53cd9273 | blueswir1 | { INDEX_op_sub_i32, { "r", "r", "rJ" } }, |
575 | 53cd9273 | blueswir1 | { INDEX_op_and_i32, { "r", "r", "rJ" } }, |
576 | 53cd9273 | blueswir1 | { INDEX_op_or_i32, { "r", "r", "rJ" } }, |
577 | 53cd9273 | blueswir1 | { INDEX_op_xor_i32, { "r", "r", "rJ" } }, |
578 | 8289b279 | blueswir1 | |
579 | 53cd9273 | blueswir1 | { INDEX_op_shl_i32, { "r", "r", "rJ" } }, |
580 | 53cd9273 | blueswir1 | { INDEX_op_shr_i32, { "r", "r", "rJ" } }, |
581 | 53cd9273 | blueswir1 | { INDEX_op_sar_i32, { "r", "r", "rJ" } }, |
582 | 8289b279 | blueswir1 | |
583 | 8289b279 | blueswir1 | { INDEX_op_brcond_i32, { "r", "ri" } }, |
584 | 8289b279 | blueswir1 | |
585 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld8u, { "r", "L" } }, |
586 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld8s, { "r", "L" } }, |
587 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld16u, { "r", "L" } }, |
588 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld16s, { "r", "L" } }, |
589 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld32u, { "r", "L" } }, |
590 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld32s, { "r", "L" } }, |
591 | 8289b279 | blueswir1 | |
592 | 8289b279 | blueswir1 | { INDEX_op_qemu_st8, { "L", "L" } }, |
593 | 8289b279 | blueswir1 | { INDEX_op_qemu_st16, { "L", "L" } }, |
594 | 8289b279 | blueswir1 | { INDEX_op_qemu_st32, { "L", "L" } }, |
595 | 8289b279 | blueswir1 | |
596 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
597 | 8289b279 | blueswir1 | { INDEX_op_mov_i64, { "r", "r" } }, |
598 | 8289b279 | blueswir1 | { INDEX_op_movi_i64, { "r" } },
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599 | 8289b279 | blueswir1 | { INDEX_op_ld8u_i64, { "r", "r" } }, |
600 | 8289b279 | blueswir1 | { INDEX_op_ld8s_i64, { "r", "r" } }, |
601 | 8289b279 | blueswir1 | { INDEX_op_ld16u_i64, { "r", "r" } }, |
602 | 8289b279 | blueswir1 | { INDEX_op_ld16s_i64, { "r", "r" } }, |
603 | 8289b279 | blueswir1 | { INDEX_op_ld32u_i64, { "r", "r" } }, |
604 | 8289b279 | blueswir1 | { INDEX_op_ld32s_i64, { "r", "r" } }, |
605 | 8289b279 | blueswir1 | { INDEX_op_ld_i64, { "r", "r" } }, |
606 | 8289b279 | blueswir1 | { INDEX_op_st8_i64, { "r", "r" } }, |
607 | 8289b279 | blueswir1 | { INDEX_op_st16_i64, { "r", "r" } }, |
608 | 8289b279 | blueswir1 | { INDEX_op_st32_i64, { "r", "r" } }, |
609 | 8289b279 | blueswir1 | { INDEX_op_st_i64, { "r", "r" } }, |
610 | 8289b279 | blueswir1 | |
611 | 53cd9273 | blueswir1 | { INDEX_op_add_i64, { "r", "r", "rJ" } }, |
612 | 53cd9273 | blueswir1 | { INDEX_op_mul_i64, { "r", "r", "rJ" } }, |
613 | 8289b279 | blueswir1 | { INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } }, |
614 | 8289b279 | blueswir1 | { INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } }, |
615 | 53cd9273 | blueswir1 | { INDEX_op_sub_i64, { "r", "r", "rJ" } }, |
616 | 53cd9273 | blueswir1 | { INDEX_op_and_i64, { "r", "r", "rJ" } }, |
617 | 53cd9273 | blueswir1 | { INDEX_op_or_i64, { "r", "r", "rJ" } }, |
618 | 53cd9273 | blueswir1 | { INDEX_op_xor_i64, { "r", "r", "rJ" } }, |
619 | 8289b279 | blueswir1 | |
620 | 53cd9273 | blueswir1 | { INDEX_op_shl_i64, { "r", "r", "rJ" } }, |
621 | 53cd9273 | blueswir1 | { INDEX_op_shr_i64, { "r", "r", "rJ" } }, |
622 | 53cd9273 | blueswir1 | { INDEX_op_sar_i64, { "r", "r", "rJ" } }, |
623 | 8289b279 | blueswir1 | |
624 | 8289b279 | blueswir1 | { INDEX_op_brcond_i64, { "r", "ri" } }, |
625 | 8289b279 | blueswir1 | #endif
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626 | 8289b279 | blueswir1 | { -1 },
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627 | 8289b279 | blueswir1 | }; |
628 | 8289b279 | blueswir1 | |
629 | 8289b279 | blueswir1 | void tcg_target_init(TCGContext *s)
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630 | 8289b279 | blueswir1 | { |
631 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
632 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
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633 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); |
634 | 8289b279 | blueswir1 | #endif
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635 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_call_clobber_regs, 0,
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636 | b3db8758 | blueswir1 | (1 << TCG_REG_G1) |
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637 | b3db8758 | blueswir1 | (1 << TCG_REG_G2) |
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638 | b3db8758 | blueswir1 | (1 << TCG_REG_G3) |
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639 | b3db8758 | blueswir1 | (1 << TCG_REG_G4) |
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640 | b3db8758 | blueswir1 | (1 << TCG_REG_G5) |
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641 | b3db8758 | blueswir1 | (1 << TCG_REG_G6) |
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642 | b3db8758 | blueswir1 | (1 << TCG_REG_G7) |
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643 | 8289b279 | blueswir1 | (1 << TCG_REG_O0) |
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644 | 8289b279 | blueswir1 | (1 << TCG_REG_O1) |
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645 | 8289b279 | blueswir1 | (1 << TCG_REG_O2) |
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646 | 8289b279 | blueswir1 | (1 << TCG_REG_O3) |
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647 | 8289b279 | blueswir1 | (1 << TCG_REG_O4) |
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648 | 8289b279 | blueswir1 | (1 << TCG_REG_O5) |
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649 | 8289b279 | blueswir1 | (1 << TCG_REG_O7));
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650 | 8289b279 | blueswir1 | |
651 | 8289b279 | blueswir1 | tcg_regset_clear(s->reserved_regs); |
652 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); |
653 | 53cd9273 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
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654 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); |
655 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); |
656 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); |
657 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7); |
658 | 8289b279 | blueswir1 | tcg_add_target_add_op_defs(sparc_op_defs); |
659 | 8289b279 | blueswir1 | } |