root / tcg / x86_64 / tcg-target.c @ f54b3f92
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1 | c896fe29 | bellard | /*
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2 | c896fe29 | bellard | * Tiny Code Generator for QEMU
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3 | c896fe29 | bellard | *
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4 | c896fe29 | bellard | * Copyright (c) 2008 Fabrice Bellard
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5 | c896fe29 | bellard | *
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6 | c896fe29 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | c896fe29 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | c896fe29 | bellard | * in the Software without restriction, including without limitation the rights
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9 | c896fe29 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | c896fe29 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | c896fe29 | bellard | * furnished to do so, subject to the following conditions:
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12 | c896fe29 | bellard | *
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13 | c896fe29 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | c896fe29 | bellard | * all copies or substantial portions of the Software.
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15 | c896fe29 | bellard | *
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16 | c896fe29 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | c896fe29 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | c896fe29 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | c896fe29 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | c896fe29 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | c896fe29 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | c896fe29 | bellard | * THE SOFTWARE.
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23 | c896fe29 | bellard | */
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24 | c896fe29 | bellard | const char *tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
25 | c896fe29 | bellard | "%rax",
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26 | c896fe29 | bellard | "%rcx",
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27 | c896fe29 | bellard | "%rdx",
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28 | c896fe29 | bellard | "%rbx",
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29 | c896fe29 | bellard | "%rsp",
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30 | c896fe29 | bellard | "%rbp",
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31 | c896fe29 | bellard | "%rsi",
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32 | c896fe29 | bellard | "%rdi",
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33 | c896fe29 | bellard | "%r8",
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34 | c896fe29 | bellard | "%r9",
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35 | c896fe29 | bellard | "%r10",
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36 | c896fe29 | bellard | "%r11",
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37 | c896fe29 | bellard | "%r12",
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38 | c896fe29 | bellard | "%r13",
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39 | c896fe29 | bellard | "%r14",
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40 | c896fe29 | bellard | "%r15",
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41 | c896fe29 | bellard | }; |
42 | c896fe29 | bellard | |
43 | 0954d0d9 | blueswir1 | int tcg_target_reg_alloc_order[] = {
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44 | c896fe29 | bellard | TCG_REG_RDI, |
45 | c896fe29 | bellard | TCG_REG_RSI, |
46 | c896fe29 | bellard | TCG_REG_RDX, |
47 | c896fe29 | bellard | TCG_REG_RCX, |
48 | c896fe29 | bellard | TCG_REG_R8, |
49 | c896fe29 | bellard | TCG_REG_R9, |
50 | c896fe29 | bellard | TCG_REG_RAX, |
51 | c896fe29 | bellard | TCG_REG_R10, |
52 | c896fe29 | bellard | TCG_REG_R11, |
53 | c896fe29 | bellard | |
54 | c896fe29 | bellard | TCG_REG_RBP, |
55 | c896fe29 | bellard | TCG_REG_RBX, |
56 | c896fe29 | bellard | TCG_REG_R12, |
57 | c896fe29 | bellard | TCG_REG_R13, |
58 | c896fe29 | bellard | TCG_REG_R14, |
59 | c896fe29 | bellard | TCG_REG_R15, |
60 | c896fe29 | bellard | }; |
61 | c896fe29 | bellard | |
62 | c896fe29 | bellard | const int tcg_target_call_iarg_regs[6] = { |
63 | c896fe29 | bellard | TCG_REG_RDI, |
64 | c896fe29 | bellard | TCG_REG_RSI, |
65 | c896fe29 | bellard | TCG_REG_RDX, |
66 | c896fe29 | bellard | TCG_REG_RCX, |
67 | c896fe29 | bellard | TCG_REG_R8, |
68 | c896fe29 | bellard | TCG_REG_R9, |
69 | c896fe29 | bellard | }; |
70 | c896fe29 | bellard | |
71 | c896fe29 | bellard | const int tcg_target_call_oarg_regs[2] = { |
72 | c896fe29 | bellard | TCG_REG_RAX, |
73 | c896fe29 | bellard | TCG_REG_RDX |
74 | c896fe29 | bellard | }; |
75 | c896fe29 | bellard | |
76 | c896fe29 | bellard | static void patch_reloc(uint8_t *code_ptr, int type, |
77 | f54b3f92 | aurel32 | tcg_target_long value, tcg_target_long addend) |
78 | c896fe29 | bellard | { |
79 | f54b3f92 | aurel32 | value += addend; |
80 | c896fe29 | bellard | switch(type) {
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81 | c896fe29 | bellard | case R_X86_64_32:
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82 | c896fe29 | bellard | if (value != (uint32_t)value)
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83 | c896fe29 | bellard | tcg_abort(); |
84 | c896fe29 | bellard | *(uint32_t *)code_ptr = value; |
85 | c896fe29 | bellard | break;
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86 | c896fe29 | bellard | case R_X86_64_32S:
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87 | c896fe29 | bellard | if (value != (int32_t)value)
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88 | c896fe29 | bellard | tcg_abort(); |
89 | c896fe29 | bellard | *(uint32_t *)code_ptr = value; |
90 | c896fe29 | bellard | break;
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91 | c896fe29 | bellard | case R_386_PC32:
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92 | c896fe29 | bellard | value -= (long)code_ptr;
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93 | c896fe29 | bellard | if (value != (int32_t)value)
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94 | c896fe29 | bellard | tcg_abort(); |
95 | c896fe29 | bellard | *(uint32_t *)code_ptr = value; |
96 | c896fe29 | bellard | break;
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97 | c896fe29 | bellard | default:
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98 | c896fe29 | bellard | tcg_abort(); |
99 | c896fe29 | bellard | } |
100 | c896fe29 | bellard | } |
101 | c896fe29 | bellard | |
102 | c896fe29 | bellard | /* maximum number of register used for input function arguments */
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103 | c896fe29 | bellard | static inline int tcg_target_get_call_iarg_regs_count(int flags) |
104 | c896fe29 | bellard | { |
105 | c896fe29 | bellard | return 6; |
106 | c896fe29 | bellard | } |
107 | c896fe29 | bellard | |
108 | c896fe29 | bellard | /* parse target specific constraints */
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109 | c896fe29 | bellard | int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
110 | c896fe29 | bellard | { |
111 | c896fe29 | bellard | const char *ct_str; |
112 | c896fe29 | bellard | |
113 | c896fe29 | bellard | ct_str = *pct_str; |
114 | c896fe29 | bellard | switch(ct_str[0]) { |
115 | c896fe29 | bellard | case 'a': |
116 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
117 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX); |
118 | c896fe29 | bellard | break;
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119 | c896fe29 | bellard | case 'b': |
120 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
121 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX); |
122 | c896fe29 | bellard | break;
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123 | c896fe29 | bellard | case 'c': |
124 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
125 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX); |
126 | c896fe29 | bellard | break;
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127 | c896fe29 | bellard | case 'd': |
128 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
129 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX); |
130 | c896fe29 | bellard | break;
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131 | c896fe29 | bellard | case 'S': |
132 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
133 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI); |
134 | c896fe29 | bellard | break;
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135 | c896fe29 | bellard | case 'D': |
136 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
137 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI); |
138 | c896fe29 | bellard | break;
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139 | c896fe29 | bellard | case 'q': |
140 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
141 | c896fe29 | bellard | tcg_regset_set32(ct->u.regs, 0, 0xf); |
142 | c896fe29 | bellard | break;
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143 | c896fe29 | bellard | case 'r': |
144 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
145 | c896fe29 | bellard | tcg_regset_set32(ct->u.regs, 0, 0xffff); |
146 | c896fe29 | bellard | break;
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147 | c896fe29 | bellard | case 'L': /* qemu_ld/st constraint */ |
148 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
149 | c896fe29 | bellard | tcg_regset_set32(ct->u.regs, 0, 0xffff); |
150 | c896fe29 | bellard | tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI); |
151 | c896fe29 | bellard | tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI); |
152 | c896fe29 | bellard | break;
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153 | c896fe29 | bellard | case 'e': |
154 | c896fe29 | bellard | ct->ct |= TCG_CT_CONST_S32; |
155 | c896fe29 | bellard | break;
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156 | c896fe29 | bellard | case 'Z': |
157 | c896fe29 | bellard | ct->ct |= TCG_CT_CONST_U32; |
158 | c896fe29 | bellard | break;
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159 | c896fe29 | bellard | default:
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160 | c896fe29 | bellard | return -1; |
161 | c896fe29 | bellard | } |
162 | c896fe29 | bellard | ct_str++; |
163 | c896fe29 | bellard | *pct_str = ct_str; |
164 | c896fe29 | bellard | return 0; |
165 | c896fe29 | bellard | } |
166 | c896fe29 | bellard | |
167 | c896fe29 | bellard | /* test if a constant matches the constraint */
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168 | c896fe29 | bellard | static inline int tcg_target_const_match(tcg_target_long val, |
169 | c896fe29 | bellard | const TCGArgConstraint *arg_ct)
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170 | c896fe29 | bellard | { |
171 | c896fe29 | bellard | int ct;
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172 | c896fe29 | bellard | ct = arg_ct->ct; |
173 | c896fe29 | bellard | if (ct & TCG_CT_CONST)
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174 | c896fe29 | bellard | return 1; |
175 | c896fe29 | bellard | else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) |
176 | c896fe29 | bellard | return 1; |
177 | c896fe29 | bellard | else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) |
178 | c896fe29 | bellard | return 1; |
179 | c896fe29 | bellard | else
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180 | c896fe29 | bellard | return 0; |
181 | c896fe29 | bellard | } |
182 | c896fe29 | bellard | |
183 | c896fe29 | bellard | #define ARITH_ADD 0 |
184 | c896fe29 | bellard | #define ARITH_OR 1 |
185 | c896fe29 | bellard | #define ARITH_ADC 2 |
186 | c896fe29 | bellard | #define ARITH_SBB 3 |
187 | c896fe29 | bellard | #define ARITH_AND 4 |
188 | c896fe29 | bellard | #define ARITH_SUB 5 |
189 | c896fe29 | bellard | #define ARITH_XOR 6 |
190 | c896fe29 | bellard | #define ARITH_CMP 7 |
191 | c896fe29 | bellard | |
192 | c896fe29 | bellard | #define SHIFT_SHL 4 |
193 | c896fe29 | bellard | #define SHIFT_SHR 5 |
194 | c896fe29 | bellard | #define SHIFT_SAR 7 |
195 | c896fe29 | bellard | |
196 | c896fe29 | bellard | #define JCC_JMP (-1) |
197 | c896fe29 | bellard | #define JCC_JO 0x0 |
198 | c896fe29 | bellard | #define JCC_JNO 0x1 |
199 | c896fe29 | bellard | #define JCC_JB 0x2 |
200 | c896fe29 | bellard | #define JCC_JAE 0x3 |
201 | c896fe29 | bellard | #define JCC_JE 0x4 |
202 | c896fe29 | bellard | #define JCC_JNE 0x5 |
203 | c896fe29 | bellard | #define JCC_JBE 0x6 |
204 | c896fe29 | bellard | #define JCC_JA 0x7 |
205 | c896fe29 | bellard | #define JCC_JS 0x8 |
206 | c896fe29 | bellard | #define JCC_JNS 0x9 |
207 | c896fe29 | bellard | #define JCC_JP 0xa |
208 | c896fe29 | bellard | #define JCC_JNP 0xb |
209 | c896fe29 | bellard | #define JCC_JL 0xc |
210 | c896fe29 | bellard | #define JCC_JGE 0xd |
211 | c896fe29 | bellard | #define JCC_JLE 0xe |
212 | c896fe29 | bellard | #define JCC_JG 0xf |
213 | c896fe29 | bellard | |
214 | c896fe29 | bellard | #define P_EXT 0x100 /* 0x0f opcode prefix */ |
215 | c896fe29 | bellard | #define P_REXW 0x200 /* set rex.w = 1 */ |
216 | c896fe29 | bellard | #define P_REX 0x400 /* force rex usage */ |
217 | c896fe29 | bellard | |
218 | c896fe29 | bellard | static const uint8_t tcg_cond_to_jcc[10] = { |
219 | c896fe29 | bellard | [TCG_COND_EQ] = JCC_JE, |
220 | c896fe29 | bellard | [TCG_COND_NE] = JCC_JNE, |
221 | c896fe29 | bellard | [TCG_COND_LT] = JCC_JL, |
222 | c896fe29 | bellard | [TCG_COND_GE] = JCC_JGE, |
223 | c896fe29 | bellard | [TCG_COND_LE] = JCC_JLE, |
224 | c896fe29 | bellard | [TCG_COND_GT] = JCC_JG, |
225 | c896fe29 | bellard | [TCG_COND_LTU] = JCC_JB, |
226 | c896fe29 | bellard | [TCG_COND_GEU] = JCC_JAE, |
227 | c896fe29 | bellard | [TCG_COND_LEU] = JCC_JBE, |
228 | c896fe29 | bellard | [TCG_COND_GTU] = JCC_JA, |
229 | c896fe29 | bellard | }; |
230 | c896fe29 | bellard | |
231 | c896fe29 | bellard | static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) |
232 | c896fe29 | bellard | { |
233 | c896fe29 | bellard | int rex;
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234 | c896fe29 | bellard | rex = ((opc >> 6) & 0x8) | ((r >> 1) & 0x4) | |
235 | c896fe29 | bellard | ((x >> 2) & 2) | ((rm >> 3) & 1); |
236 | c896fe29 | bellard | if (rex || (opc & P_REX)) {
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237 | c896fe29 | bellard | tcg_out8(s, rex | 0x40);
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238 | c896fe29 | bellard | } |
239 | c896fe29 | bellard | if (opc & P_EXT)
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240 | c896fe29 | bellard | tcg_out8(s, 0x0f);
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241 | c896fe29 | bellard | tcg_out8(s, opc); |
242 | c896fe29 | bellard | } |
243 | c896fe29 | bellard | |
244 | c896fe29 | bellard | static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) |
245 | c896fe29 | bellard | { |
246 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, 0);
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247 | c896fe29 | bellard | tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7)); |
248 | c896fe29 | bellard | } |
249 | c896fe29 | bellard | |
250 | c896fe29 | bellard | /* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
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251 | c896fe29 | bellard | static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, |
252 | c896fe29 | bellard | tcg_target_long offset) |
253 | c896fe29 | bellard | { |
254 | c896fe29 | bellard | if (rm < 0) { |
255 | c896fe29 | bellard | tcg_target_long val; |
256 | c896fe29 | bellard | tcg_out_opc(s, opc, r, 0, 0); |
257 | c896fe29 | bellard | val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1)); |
258 | c896fe29 | bellard | if (val == (int32_t)val) {
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259 | c896fe29 | bellard | /* eip relative */
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260 | c896fe29 | bellard | tcg_out8(s, 0x05 | ((r & 7) << 3)); |
261 | c896fe29 | bellard | tcg_out32(s, val); |
262 | c896fe29 | bellard | } else if (offset == (int32_t)offset) { |
263 | c896fe29 | bellard | tcg_out8(s, 0x04 | ((r & 7) << 3)); |
264 | c896fe29 | bellard | tcg_out8(s, 0x25); /* sib */ |
265 | c896fe29 | bellard | tcg_out32(s, offset); |
266 | c896fe29 | bellard | } else {
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267 | c896fe29 | bellard | tcg_abort(); |
268 | c896fe29 | bellard | } |
269 | c896fe29 | bellard | } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) { |
270 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, 0);
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271 | c896fe29 | bellard | if ((rm & 7) == TCG_REG_RSP) { |
272 | c896fe29 | bellard | tcg_out8(s, 0x04 | ((r & 7) << 3)); |
273 | c896fe29 | bellard | tcg_out8(s, 0x24);
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274 | c896fe29 | bellard | } else {
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275 | c896fe29 | bellard | tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7)); |
276 | c896fe29 | bellard | } |
277 | c896fe29 | bellard | } else if ((int8_t)offset == offset) { |
278 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, 0);
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279 | c896fe29 | bellard | if ((rm & 7) == TCG_REG_RSP) { |
280 | c896fe29 | bellard | tcg_out8(s, 0x44 | ((r & 7) << 3)); |
281 | c896fe29 | bellard | tcg_out8(s, 0x24);
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282 | c896fe29 | bellard | } else {
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283 | c896fe29 | bellard | tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7)); |
284 | c896fe29 | bellard | } |
285 | c896fe29 | bellard | tcg_out8(s, offset); |
286 | c896fe29 | bellard | } else {
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287 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, 0);
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288 | c896fe29 | bellard | if ((rm & 7) == TCG_REG_RSP) { |
289 | c896fe29 | bellard | tcg_out8(s, 0x84 | ((r & 7) << 3)); |
290 | c896fe29 | bellard | tcg_out8(s, 0x24);
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291 | c896fe29 | bellard | } else {
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292 | c896fe29 | bellard | tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7)); |
293 | c896fe29 | bellard | } |
294 | c896fe29 | bellard | tcg_out32(s, offset); |
295 | c896fe29 | bellard | } |
296 | c896fe29 | bellard | } |
297 | c896fe29 | bellard | |
298 | bffd92fe | blueswir1 | #if defined(CONFIG_SOFTMMU)
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299 | c896fe29 | bellard | /* XXX: incomplete. index must be different from ESP */
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300 | c896fe29 | bellard | static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm, |
301 | c896fe29 | bellard | int index, int shift, |
302 | c896fe29 | bellard | tcg_target_long offset) |
303 | c896fe29 | bellard | { |
304 | c896fe29 | bellard | int mod;
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305 | c896fe29 | bellard | if (rm == -1) |
306 | c896fe29 | bellard | tcg_abort(); |
307 | c896fe29 | bellard | if (offset == 0 && (rm & 7) != TCG_REG_RBP) { |
308 | c896fe29 | bellard | mod = 0;
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309 | c896fe29 | bellard | } else if (offset == (int8_t)offset) { |
310 | c896fe29 | bellard | mod = 0x40;
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311 | c896fe29 | bellard | } else if (offset == (int32_t)offset) { |
312 | c896fe29 | bellard | mod = 0x80;
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313 | c896fe29 | bellard | } else {
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314 | c896fe29 | bellard | tcg_abort(); |
315 | c896fe29 | bellard | } |
316 | c896fe29 | bellard | if (index == -1) { |
317 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, 0);
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318 | c896fe29 | bellard | if ((rm & 7) == TCG_REG_RSP) { |
319 | c896fe29 | bellard | tcg_out8(s, mod | ((r & 7) << 3) | 0x04); |
320 | c896fe29 | bellard | tcg_out8(s, 0x04 | (rm & 7)); |
321 | c896fe29 | bellard | } else {
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322 | c896fe29 | bellard | tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7)); |
323 | c896fe29 | bellard | } |
324 | c896fe29 | bellard | } else {
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325 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, index); |
326 | c896fe29 | bellard | tcg_out8(s, mod | ((r & 7) << 3) | 0x04); |
327 | c896fe29 | bellard | tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7)); |
328 | c896fe29 | bellard | } |
329 | c896fe29 | bellard | if (mod == 0x40) { |
330 | c896fe29 | bellard | tcg_out8(s, offset); |
331 | c896fe29 | bellard | } else if (mod == 0x80) { |
332 | c896fe29 | bellard | tcg_out32(s, offset); |
333 | c896fe29 | bellard | } |
334 | c896fe29 | bellard | } |
335 | bffd92fe | blueswir1 | #endif
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336 | c896fe29 | bellard | |
337 | c896fe29 | bellard | static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
338 | c896fe29 | bellard | { |
339 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | P_REXW, ret, arg);
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340 | c896fe29 | bellard | } |
341 | c896fe29 | bellard | |
342 | c896fe29 | bellard | static inline void tcg_out_movi(TCGContext *s, TCGType type, |
343 | c896fe29 | bellard | int ret, tcg_target_long arg)
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344 | c896fe29 | bellard | { |
345 | c896fe29 | bellard | if (arg == 0) { |
346 | c896fe29 | bellard | tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */ |
347 | c896fe29 | bellard | } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) { |
348 | c896fe29 | bellard | tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0); |
349 | c896fe29 | bellard | tcg_out32(s, arg); |
350 | c896fe29 | bellard | } else if (arg == (int32_t)arg) { |
351 | c896fe29 | bellard | tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret); |
352 | c896fe29 | bellard | tcg_out32(s, arg); |
353 | c896fe29 | bellard | } else {
|
354 | c896fe29 | bellard | tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0); |
355 | c896fe29 | bellard | tcg_out32(s, arg); |
356 | c896fe29 | bellard | tcg_out32(s, arg >> 32);
|
357 | c896fe29 | bellard | } |
358 | c896fe29 | bellard | } |
359 | c896fe29 | bellard | |
360 | e4d5434c | blueswir1 | static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, |
361 | c896fe29 | bellard | int arg1, tcg_target_long arg2)
|
362 | c896fe29 | bellard | { |
363 | e4d5434c | blueswir1 | if (type == TCG_TYPE_I32)
|
364 | e4d5434c | blueswir1 | tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */ |
365 | e4d5434c | blueswir1 | else
|
366 | e4d5434c | blueswir1 | tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */ |
367 | c896fe29 | bellard | } |
368 | c896fe29 | bellard | |
369 | e4d5434c | blueswir1 | static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, |
370 | c896fe29 | bellard | int arg1, tcg_target_long arg2)
|
371 | c896fe29 | bellard | { |
372 | e4d5434c | blueswir1 | if (type == TCG_TYPE_I32)
|
373 | e4d5434c | blueswir1 | tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */ |
374 | e4d5434c | blueswir1 | else
|
375 | e4d5434c | blueswir1 | tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */ |
376 | c896fe29 | bellard | } |
377 | c896fe29 | bellard | |
378 | c896fe29 | bellard | static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val) |
379 | c896fe29 | bellard | { |
380 | c896fe29 | bellard | if (val == (int8_t)val) {
|
381 | c896fe29 | bellard | tcg_out_modrm(s, 0x83, c, r0);
|
382 | c896fe29 | bellard | tcg_out8(s, val); |
383 | c896fe29 | bellard | } else {
|
384 | c896fe29 | bellard | tcg_out_modrm(s, 0x81, c, r0);
|
385 | c896fe29 | bellard | tcg_out32(s, val); |
386 | c896fe29 | bellard | } |
387 | c896fe29 | bellard | } |
388 | c896fe29 | bellard | |
389 | c896fe29 | bellard | static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val) |
390 | c896fe29 | bellard | { |
391 | c896fe29 | bellard | if (val == (int8_t)val) {
|
392 | c896fe29 | bellard | tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
|
393 | c896fe29 | bellard | tcg_out8(s, val); |
394 | c896fe29 | bellard | } else if (val == (int32_t)val) { |
395 | c896fe29 | bellard | tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
|
396 | c896fe29 | bellard | tcg_out32(s, val); |
397 | c896fe29 | bellard | } else if (c == ARITH_AND && val == (uint32_t)val) { |
398 | c896fe29 | bellard | tcg_out_modrm(s, 0x81, c, r0);
|
399 | c896fe29 | bellard | tcg_out32(s, val); |
400 | c896fe29 | bellard | } else {
|
401 | c896fe29 | bellard | tcg_abort(); |
402 | c896fe29 | bellard | } |
403 | c896fe29 | bellard | } |
404 | c896fe29 | bellard | |
405 | c896fe29 | bellard | void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
406 | c896fe29 | bellard | { |
407 | c896fe29 | bellard | if (val != 0) |
408 | c896fe29 | bellard | tgen_arithi64(s, ARITH_ADD, reg, val); |
409 | c896fe29 | bellard | } |
410 | c896fe29 | bellard | |
411 | c896fe29 | bellard | static void tcg_out_jxx(TCGContext *s, int opc, int label_index) |
412 | c896fe29 | bellard | { |
413 | c896fe29 | bellard | int32_t val, val1; |
414 | c896fe29 | bellard | TCGLabel *l = &s->labels[label_index]; |
415 | c896fe29 | bellard | |
416 | c896fe29 | bellard | if (l->has_value) {
|
417 | c896fe29 | bellard | val = l->u.value - (tcg_target_long)s->code_ptr; |
418 | c896fe29 | bellard | val1 = val - 2;
|
419 | c896fe29 | bellard | if ((int8_t)val1 == val1) {
|
420 | c896fe29 | bellard | if (opc == -1) |
421 | c896fe29 | bellard | tcg_out8(s, 0xeb);
|
422 | c896fe29 | bellard | else
|
423 | c896fe29 | bellard | tcg_out8(s, 0x70 + opc);
|
424 | c896fe29 | bellard | tcg_out8(s, val1); |
425 | c896fe29 | bellard | } else {
|
426 | c896fe29 | bellard | if (opc == -1) { |
427 | c896fe29 | bellard | tcg_out8(s, 0xe9);
|
428 | c896fe29 | bellard | tcg_out32(s, val - 5);
|
429 | c896fe29 | bellard | } else {
|
430 | c896fe29 | bellard | tcg_out8(s, 0x0f);
|
431 | c896fe29 | bellard | tcg_out8(s, 0x80 + opc);
|
432 | c896fe29 | bellard | tcg_out32(s, val - 6);
|
433 | c896fe29 | bellard | } |
434 | c896fe29 | bellard | } |
435 | c896fe29 | bellard | } else {
|
436 | c896fe29 | bellard | if (opc == -1) { |
437 | c896fe29 | bellard | tcg_out8(s, 0xe9);
|
438 | c896fe29 | bellard | } else {
|
439 | c896fe29 | bellard | tcg_out8(s, 0x0f);
|
440 | c896fe29 | bellard | tcg_out8(s, 0x80 + opc);
|
441 | c896fe29 | bellard | } |
442 | c896fe29 | bellard | tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
|
443 | 623e265c | pbrook | s->code_ptr += 4;
|
444 | c896fe29 | bellard | } |
445 | c896fe29 | bellard | } |
446 | c896fe29 | bellard | |
447 | c896fe29 | bellard | static void tcg_out_brcond(TCGContext *s, int cond, |
448 | c896fe29 | bellard | TCGArg arg1, TCGArg arg2, int const_arg2,
|
449 | c896fe29 | bellard | int label_index, int rexw) |
450 | c896fe29 | bellard | { |
451 | c896fe29 | bellard | int c;
|
452 | c896fe29 | bellard | if (const_arg2) {
|
453 | c896fe29 | bellard | if (arg2 == 0) { |
454 | c896fe29 | bellard | /* use test */
|
455 | c896fe29 | bellard | switch(cond) {
|
456 | c896fe29 | bellard | case TCG_COND_EQ:
|
457 | bb210e78 | bellard | c = JCC_JE; |
458 | c896fe29 | bellard | break;
|
459 | c896fe29 | bellard | case TCG_COND_NE:
|
460 | c896fe29 | bellard | c = JCC_JNE; |
461 | c896fe29 | bellard | break;
|
462 | c896fe29 | bellard | case TCG_COND_LT:
|
463 | c896fe29 | bellard | c = JCC_JS; |
464 | c896fe29 | bellard | break;
|
465 | c896fe29 | bellard | case TCG_COND_GE:
|
466 | c896fe29 | bellard | c = JCC_JNS; |
467 | c896fe29 | bellard | break;
|
468 | c896fe29 | bellard | default:
|
469 | c896fe29 | bellard | goto do_cmpi;
|
470 | c896fe29 | bellard | } |
471 | c896fe29 | bellard | /* test r, r */
|
472 | c896fe29 | bellard | tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
|
473 | c896fe29 | bellard | tcg_out_jxx(s, c, label_index); |
474 | c896fe29 | bellard | } else {
|
475 | c896fe29 | bellard | do_cmpi:
|
476 | c896fe29 | bellard | if (rexw)
|
477 | c896fe29 | bellard | tgen_arithi64(s, ARITH_CMP, arg1, arg2); |
478 | c896fe29 | bellard | else
|
479 | c896fe29 | bellard | tgen_arithi32(s, ARITH_CMP, arg1, arg2); |
480 | c896fe29 | bellard | tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index); |
481 | c896fe29 | bellard | } |
482 | c896fe29 | bellard | } else {
|
483 | bb210e78 | bellard | tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1); |
484 | c896fe29 | bellard | tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index); |
485 | c896fe29 | bellard | } |
486 | c896fe29 | bellard | } |
487 | c896fe29 | bellard | |
488 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
489 | c896fe29 | bellard | extern void __ldb_mmu(void); |
490 | c896fe29 | bellard | extern void __ldw_mmu(void); |
491 | c896fe29 | bellard | extern void __ldl_mmu(void); |
492 | c896fe29 | bellard | extern void __ldq_mmu(void); |
493 | c896fe29 | bellard | |
494 | c896fe29 | bellard | extern void __stb_mmu(void); |
495 | c896fe29 | bellard | extern void __stw_mmu(void); |
496 | c896fe29 | bellard | extern void __stl_mmu(void); |
497 | c896fe29 | bellard | extern void __stq_mmu(void); |
498 | c896fe29 | bellard | |
499 | c896fe29 | bellard | |
500 | c896fe29 | bellard | static void *qemu_ld_helpers[4] = { |
501 | c896fe29 | bellard | __ldb_mmu, |
502 | c896fe29 | bellard | __ldw_mmu, |
503 | c896fe29 | bellard | __ldl_mmu, |
504 | c896fe29 | bellard | __ldq_mmu, |
505 | c896fe29 | bellard | }; |
506 | c896fe29 | bellard | |
507 | c896fe29 | bellard | static void *qemu_st_helpers[4] = { |
508 | c896fe29 | bellard | __stb_mmu, |
509 | c896fe29 | bellard | __stw_mmu, |
510 | c896fe29 | bellard | __stl_mmu, |
511 | c896fe29 | bellard | __stq_mmu, |
512 | c896fe29 | bellard | }; |
513 | c896fe29 | bellard | #endif
|
514 | c896fe29 | bellard | |
515 | c896fe29 | bellard | static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
516 | c896fe29 | bellard | int opc)
|
517 | c896fe29 | bellard | { |
518 | c896fe29 | bellard | int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
|
519 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
520 | c896fe29 | bellard | uint8_t *label1_ptr, *label2_ptr; |
521 | c896fe29 | bellard | #endif
|
522 | c896fe29 | bellard | |
523 | c896fe29 | bellard | data_reg = *args++; |
524 | c896fe29 | bellard | addr_reg = *args++; |
525 | c896fe29 | bellard | mem_index = *args; |
526 | c896fe29 | bellard | s_bits = opc & 3;
|
527 | c896fe29 | bellard | |
528 | c896fe29 | bellard | r0 = TCG_REG_RDI; |
529 | c896fe29 | bellard | r1 = TCG_REG_RSI; |
530 | c896fe29 | bellard | |
531 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
532 | c896fe29 | bellard | rexw = 0;
|
533 | c896fe29 | bellard | #else
|
534 | c896fe29 | bellard | rexw = P_REXW; |
535 | c896fe29 | bellard | #endif
|
536 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
537 | c896fe29 | bellard | /* mov */
|
538 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
|
539 | c896fe29 | bellard | |
540 | c896fe29 | bellard | /* mov */
|
541 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
542 | c896fe29 | bellard | |
543 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */ |
544 | c896fe29 | bellard | tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |
545 | c896fe29 | bellard | |
546 | c896fe29 | bellard | tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */ |
547 | c896fe29 | bellard | tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
548 | c896fe29 | bellard | |
549 | c896fe29 | bellard | tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */ |
550 | c896fe29 | bellard | tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
551 | c896fe29 | bellard | |
552 | c896fe29 | bellard | /* lea offset(r1, env), r1 */
|
553 | c896fe29 | bellard | tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0, |
554 | c896fe29 | bellard | offsetof(CPUState, tlb_table[mem_index][0].addr_read));
|
555 | c896fe29 | bellard | |
556 | c896fe29 | bellard | /* cmp 0(r1), r0 */
|
557 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0); |
558 | c896fe29 | bellard | |
559 | c896fe29 | bellard | /* mov */
|
560 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
561 | c896fe29 | bellard | |
562 | c896fe29 | bellard | /* je label1 */
|
563 | c896fe29 | bellard | tcg_out8(s, 0x70 + JCC_JE);
|
564 | c896fe29 | bellard | label1_ptr = s->code_ptr; |
565 | c896fe29 | bellard | s->code_ptr++; |
566 | c896fe29 | bellard | |
567 | c896fe29 | bellard | /* XXX: move that code at the end of the TB */
|
568 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index); |
569 | c896fe29 | bellard | tcg_out8(s, 0xe8);
|
570 | c896fe29 | bellard | tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] - |
571 | c896fe29 | bellard | (tcg_target_long)s->code_ptr - 4);
|
572 | c896fe29 | bellard | |
573 | c896fe29 | bellard | switch(opc) {
|
574 | c896fe29 | bellard | case 0 | 4: |
575 | c896fe29 | bellard | /* movsbq */
|
576 | c896fe29 | bellard | tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
577 | c896fe29 | bellard | break;
|
578 | c896fe29 | bellard | case 1 | 4: |
579 | c896fe29 | bellard | /* movswq */
|
580 | c896fe29 | bellard | tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
581 | c896fe29 | bellard | break;
|
582 | c896fe29 | bellard | case 2 | 4: |
583 | c896fe29 | bellard | /* movslq */
|
584 | c896fe29 | bellard | tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
|
585 | c896fe29 | bellard | break;
|
586 | c896fe29 | bellard | case 0: |
587 | c896fe29 | bellard | case 1: |
588 | c896fe29 | bellard | case 2: |
589 | c896fe29 | bellard | default:
|
590 | c896fe29 | bellard | /* movl */
|
591 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
|
592 | c896fe29 | bellard | break;
|
593 | c896fe29 | bellard | case 3: |
594 | c896fe29 | bellard | tcg_out_mov(s, data_reg, TCG_REG_RAX); |
595 | c896fe29 | bellard | break;
|
596 | c896fe29 | bellard | } |
597 | c896fe29 | bellard | |
598 | c896fe29 | bellard | /* jmp label2 */
|
599 | c896fe29 | bellard | tcg_out8(s, 0xeb);
|
600 | c896fe29 | bellard | label2_ptr = s->code_ptr; |
601 | c896fe29 | bellard | s->code_ptr++; |
602 | c896fe29 | bellard | |
603 | c896fe29 | bellard | /* label1: */
|
604 | c896fe29 | bellard | *label1_ptr = s->code_ptr - label1_ptr - 1;
|
605 | c896fe29 | bellard | |
606 | c896fe29 | bellard | /* add x(r1), r0 */
|
607 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
|
608 | c896fe29 | bellard | offsetof(CPUTLBEntry, addr_read)); |
609 | c896fe29 | bellard | #else
|
610 | c896fe29 | bellard | r0 = addr_reg; |
611 | c896fe29 | bellard | #endif
|
612 | c896fe29 | bellard | |
613 | c896fe29 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
614 | c896fe29 | bellard | bswap = 1;
|
615 | c896fe29 | bellard | #else
|
616 | c896fe29 | bellard | bswap = 0;
|
617 | c896fe29 | bellard | #endif
|
618 | c896fe29 | bellard | switch(opc) {
|
619 | c896fe29 | bellard | case 0: |
620 | c896fe29 | bellard | /* movzbl */
|
621 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, 0); |
622 | c896fe29 | bellard | break;
|
623 | c896fe29 | bellard | case 0 | 4: |
624 | c896fe29 | bellard | /* movsbX */
|
625 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, 0); |
626 | c896fe29 | bellard | break;
|
627 | c896fe29 | bellard | case 1: |
628 | c896fe29 | bellard | /* movzwl */
|
629 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0); |
630 | c896fe29 | bellard | if (bswap) {
|
631 | c896fe29 | bellard | /* rolw $8, data_reg */
|
632 | c896fe29 | bellard | tcg_out8(s, 0x66);
|
633 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, 0, data_reg); |
634 | c896fe29 | bellard | tcg_out8(s, 8);
|
635 | c896fe29 | bellard | } |
636 | c896fe29 | bellard | break;
|
637 | c896fe29 | bellard | case 1 | 4: |
638 | c896fe29 | bellard | if (bswap) {
|
639 | c896fe29 | bellard | /* movzwl */
|
640 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, 0); |
641 | c896fe29 | bellard | /* rolw $8, data_reg */
|
642 | c896fe29 | bellard | tcg_out8(s, 0x66);
|
643 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, 0, data_reg); |
644 | c896fe29 | bellard | tcg_out8(s, 8);
|
645 | c896fe29 | bellard | |
646 | c896fe29 | bellard | /* movswX data_reg, data_reg */
|
647 | c896fe29 | bellard | tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
|
648 | c896fe29 | bellard | } else {
|
649 | c896fe29 | bellard | /* movswX */
|
650 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, 0); |
651 | c896fe29 | bellard | } |
652 | c896fe29 | bellard | break;
|
653 | c896fe29 | bellard | case 2: |
654 | c896fe29 | bellard | /* movl (r0), data_reg */
|
655 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0); |
656 | c896fe29 | bellard | if (bswap) {
|
657 | c896fe29 | bellard | /* bswap */
|
658 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0); |
659 | c896fe29 | bellard | } |
660 | c896fe29 | bellard | break;
|
661 | c896fe29 | bellard | case 2 | 4: |
662 | c896fe29 | bellard | if (bswap) {
|
663 | c896fe29 | bellard | /* movl (r0), data_reg */
|
664 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x8b, data_reg, r0, 0); |
665 | c896fe29 | bellard | /* bswap */
|
666 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0); |
667 | c896fe29 | bellard | /* movslq */
|
668 | c896fe29 | bellard | tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
|
669 | c896fe29 | bellard | } else {
|
670 | c896fe29 | bellard | /* movslq */
|
671 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, 0); |
672 | c896fe29 | bellard | } |
673 | c896fe29 | bellard | break;
|
674 | c896fe29 | bellard | case 3: |
675 | c896fe29 | bellard | /* movq (r0), data_reg */
|
676 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, 0); |
677 | c896fe29 | bellard | if (bswap) {
|
678 | c896fe29 | bellard | /* bswap */
|
679 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0); |
680 | c896fe29 | bellard | } |
681 | c896fe29 | bellard | break;
|
682 | c896fe29 | bellard | default:
|
683 | c896fe29 | bellard | tcg_abort(); |
684 | c896fe29 | bellard | } |
685 | c896fe29 | bellard | |
686 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
687 | c896fe29 | bellard | /* label2: */
|
688 | c896fe29 | bellard | *label2_ptr = s->code_ptr - label2_ptr - 1;
|
689 | c896fe29 | bellard | #endif
|
690 | c896fe29 | bellard | } |
691 | c896fe29 | bellard | |
692 | c896fe29 | bellard | static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
693 | c896fe29 | bellard | int opc)
|
694 | c896fe29 | bellard | { |
695 | c896fe29 | bellard | int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
|
696 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
697 | c896fe29 | bellard | uint8_t *label1_ptr, *label2_ptr; |
698 | c896fe29 | bellard | #endif
|
699 | c896fe29 | bellard | |
700 | c896fe29 | bellard | data_reg = *args++; |
701 | c896fe29 | bellard | addr_reg = *args++; |
702 | c896fe29 | bellard | mem_index = *args; |
703 | c896fe29 | bellard | |
704 | c896fe29 | bellard | s_bits = opc; |
705 | c896fe29 | bellard | |
706 | c896fe29 | bellard | r0 = TCG_REG_RDI; |
707 | c896fe29 | bellard | r1 = TCG_REG_RSI; |
708 | c896fe29 | bellard | |
709 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
710 | c896fe29 | bellard | rexw = 0;
|
711 | c896fe29 | bellard | #else
|
712 | c896fe29 | bellard | rexw = P_REXW; |
713 | c896fe29 | bellard | #endif
|
714 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
715 | c896fe29 | bellard | /* mov */
|
716 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
|
717 | c896fe29 | bellard | |
718 | c896fe29 | bellard | /* mov */
|
719 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
720 | c896fe29 | bellard | |
721 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */ |
722 | c896fe29 | bellard | tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |
723 | c896fe29 | bellard | |
724 | c896fe29 | bellard | tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */ |
725 | c896fe29 | bellard | tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
726 | c896fe29 | bellard | |
727 | c896fe29 | bellard | tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */ |
728 | c896fe29 | bellard | tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
729 | c896fe29 | bellard | |
730 | c896fe29 | bellard | /* lea offset(r1, env), r1 */
|
731 | c896fe29 | bellard | tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0, |
732 | c896fe29 | bellard | offsetof(CPUState, tlb_table[mem_index][0].addr_write));
|
733 | c896fe29 | bellard | |
734 | c896fe29 | bellard | /* cmp 0(r1), r0 */
|
735 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0); |
736 | c896fe29 | bellard | |
737 | c896fe29 | bellard | /* mov */
|
738 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
739 | c896fe29 | bellard | |
740 | c896fe29 | bellard | /* je label1 */
|
741 | c896fe29 | bellard | tcg_out8(s, 0x70 + JCC_JE);
|
742 | c896fe29 | bellard | label1_ptr = s->code_ptr; |
743 | c896fe29 | bellard | s->code_ptr++; |
744 | c896fe29 | bellard | |
745 | c896fe29 | bellard | /* XXX: move that code at the end of the TB */
|
746 | c896fe29 | bellard | switch(opc) {
|
747 | c896fe29 | bellard | case 0: |
748 | c896fe29 | bellard | /* movzbl */
|
749 | c896fe29 | bellard | tcg_out_modrm(s, 0xb6 | P_EXT, TCG_REG_RSI, data_reg);
|
750 | c896fe29 | bellard | break;
|
751 | c896fe29 | bellard | case 1: |
752 | c896fe29 | bellard | /* movzwl */
|
753 | c896fe29 | bellard | tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
|
754 | c896fe29 | bellard | break;
|
755 | c896fe29 | bellard | case 2: |
756 | c896fe29 | bellard | /* movl */
|
757 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
|
758 | c896fe29 | bellard | break;
|
759 | c896fe29 | bellard | default:
|
760 | c896fe29 | bellard | case 3: |
761 | c896fe29 | bellard | tcg_out_mov(s, TCG_REG_RSI, data_reg); |
762 | c896fe29 | bellard | break;
|
763 | c896fe29 | bellard | } |
764 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index); |
765 | c896fe29 | bellard | tcg_out8(s, 0xe8);
|
766 | c896fe29 | bellard | tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - |
767 | c896fe29 | bellard | (tcg_target_long)s->code_ptr - 4);
|
768 | c896fe29 | bellard | |
769 | c896fe29 | bellard | /* jmp label2 */
|
770 | c896fe29 | bellard | tcg_out8(s, 0xeb);
|
771 | c896fe29 | bellard | label2_ptr = s->code_ptr; |
772 | c896fe29 | bellard | s->code_ptr++; |
773 | c896fe29 | bellard | |
774 | c896fe29 | bellard | /* label1: */
|
775 | c896fe29 | bellard | *label1_ptr = s->code_ptr - label1_ptr - 1;
|
776 | c896fe29 | bellard | |
777 | c896fe29 | bellard | /* add x(r1), r0 */
|
778 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
|
779 | c896fe29 | bellard | offsetof(CPUTLBEntry, addr_write)); |
780 | c896fe29 | bellard | #else
|
781 | c896fe29 | bellard | r0 = addr_reg; |
782 | c896fe29 | bellard | #endif
|
783 | c896fe29 | bellard | |
784 | c896fe29 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
785 | c896fe29 | bellard | bswap = 1;
|
786 | c896fe29 | bellard | #else
|
787 | c896fe29 | bellard | bswap = 0;
|
788 | c896fe29 | bellard | #endif
|
789 | c896fe29 | bellard | switch(opc) {
|
790 | c896fe29 | bellard | case 0: |
791 | c896fe29 | bellard | /* movb */
|
792 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x88 | P_REX, data_reg, r0, 0); |
793 | c896fe29 | bellard | break;
|
794 | c896fe29 | bellard | case 1: |
795 | c896fe29 | bellard | if (bswap) {
|
796 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */ |
797 | c896fe29 | bellard | tcg_out8(s, 0x66); /* rolw $8, %ecx */ |
798 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, 0, r1); |
799 | c896fe29 | bellard | tcg_out8(s, 8);
|
800 | c896fe29 | bellard | data_reg = r1; |
801 | c896fe29 | bellard | } |
802 | c896fe29 | bellard | /* movw */
|
803 | c896fe29 | bellard | tcg_out8(s, 0x66);
|
804 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0); |
805 | c896fe29 | bellard | break;
|
806 | c896fe29 | bellard | case 2: |
807 | c896fe29 | bellard | if (bswap) {
|
808 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */ |
809 | c896fe29 | bellard | /* bswap data_reg */
|
810 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0); |
811 | c896fe29 | bellard | data_reg = r1; |
812 | c896fe29 | bellard | } |
813 | c896fe29 | bellard | /* movl */
|
814 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x89, data_reg, r0, 0); |
815 | c896fe29 | bellard | break;
|
816 | c896fe29 | bellard | case 3: |
817 | c896fe29 | bellard | if (bswap) {
|
818 | c896fe29 | bellard | tcg_out_mov(s, r1, data_reg); |
819 | c896fe29 | bellard | /* bswap data_reg */
|
820 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0); |
821 | c896fe29 | bellard | data_reg = r1; |
822 | c896fe29 | bellard | } |
823 | c896fe29 | bellard | /* movq */
|
824 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, 0); |
825 | c896fe29 | bellard | break;
|
826 | c896fe29 | bellard | default:
|
827 | c896fe29 | bellard | tcg_abort(); |
828 | c896fe29 | bellard | } |
829 | c896fe29 | bellard | |
830 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
831 | c896fe29 | bellard | /* label2: */
|
832 | c896fe29 | bellard | *label2_ptr = s->code_ptr - label2_ptr - 1;
|
833 | c896fe29 | bellard | #endif
|
834 | c896fe29 | bellard | } |
835 | c896fe29 | bellard | |
836 | c896fe29 | bellard | static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, |
837 | c896fe29 | bellard | const int *const_args) |
838 | c896fe29 | bellard | { |
839 | c896fe29 | bellard | int c;
|
840 | c896fe29 | bellard | |
841 | c896fe29 | bellard | switch(opc) {
|
842 | c896fe29 | bellard | case INDEX_op_exit_tb:
|
843 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
|
844 | c896fe29 | bellard | tcg_out8(s, 0xc3); /* ret */ |
845 | c896fe29 | bellard | break;
|
846 | c896fe29 | bellard | case INDEX_op_goto_tb:
|
847 | c896fe29 | bellard | if (s->tb_jmp_offset) {
|
848 | c896fe29 | bellard | /* direct jump method */
|
849 | c896fe29 | bellard | tcg_out8(s, 0xe9); /* jmp im */ |
850 | c896fe29 | bellard | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
851 | c896fe29 | bellard | tcg_out32(s, 0);
|
852 | c896fe29 | bellard | } else {
|
853 | c896fe29 | bellard | /* indirect jump method */
|
854 | c896fe29 | bellard | /* jmp Ev */
|
855 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xff, 4, -1, |
856 | c896fe29 | bellard | (tcg_target_long)(s->tb_next + |
857 | c896fe29 | bellard | args[0]));
|
858 | c896fe29 | bellard | } |
859 | c896fe29 | bellard | s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
860 | c896fe29 | bellard | break;
|
861 | c896fe29 | bellard | case INDEX_op_call:
|
862 | c896fe29 | bellard | if (const_args[0]) { |
863 | c896fe29 | bellard | tcg_out8(s, 0xe8);
|
864 | c896fe29 | bellard | tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4); |
865 | c896fe29 | bellard | } else {
|
866 | c896fe29 | bellard | tcg_out_modrm(s, 0xff, 2, args[0]); |
867 | c896fe29 | bellard | } |
868 | c896fe29 | bellard | break;
|
869 | c896fe29 | bellard | case INDEX_op_jmp:
|
870 | c896fe29 | bellard | if (const_args[0]) { |
871 | c896fe29 | bellard | tcg_out8(s, 0xe9);
|
872 | c896fe29 | bellard | tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4); |
873 | c896fe29 | bellard | } else {
|
874 | c896fe29 | bellard | tcg_out_modrm(s, 0xff, 4, args[0]); |
875 | c896fe29 | bellard | } |
876 | c896fe29 | bellard | break;
|
877 | c896fe29 | bellard | case INDEX_op_br:
|
878 | c896fe29 | bellard | tcg_out_jxx(s, JCC_JMP, args[0]);
|
879 | c896fe29 | bellard | break;
|
880 | c896fe29 | bellard | case INDEX_op_movi_i32:
|
881 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); |
882 | c896fe29 | bellard | break;
|
883 | c896fe29 | bellard | case INDEX_op_movi_i64:
|
884 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
885 | c896fe29 | bellard | break;
|
886 | c896fe29 | bellard | case INDEX_op_ld8u_i32:
|
887 | c896fe29 | bellard | case INDEX_op_ld8u_i64:
|
888 | c896fe29 | bellard | /* movzbl */
|
889 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]); |
890 | c896fe29 | bellard | break;
|
891 | c896fe29 | bellard | case INDEX_op_ld8s_i32:
|
892 | c896fe29 | bellard | /* movsbl */
|
893 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]); |
894 | c896fe29 | bellard | break;
|
895 | c896fe29 | bellard | case INDEX_op_ld8s_i64:
|
896 | c896fe29 | bellard | /* movsbq */
|
897 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]); |
898 | c896fe29 | bellard | break;
|
899 | c896fe29 | bellard | case INDEX_op_ld16u_i32:
|
900 | c896fe29 | bellard | case INDEX_op_ld16u_i64:
|
901 | c896fe29 | bellard | /* movzwl */
|
902 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]); |
903 | c896fe29 | bellard | break;
|
904 | c896fe29 | bellard | case INDEX_op_ld16s_i32:
|
905 | c896fe29 | bellard | /* movswl */
|
906 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]); |
907 | c896fe29 | bellard | break;
|
908 | c896fe29 | bellard | case INDEX_op_ld16s_i64:
|
909 | c896fe29 | bellard | /* movswq */
|
910 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]); |
911 | c896fe29 | bellard | break;
|
912 | c896fe29 | bellard | case INDEX_op_ld_i32:
|
913 | c896fe29 | bellard | case INDEX_op_ld32u_i64:
|
914 | c896fe29 | bellard | /* movl */
|
915 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]); |
916 | c896fe29 | bellard | break;
|
917 | c896fe29 | bellard | case INDEX_op_ld32s_i64:
|
918 | c896fe29 | bellard | /* movslq */
|
919 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]); |
920 | c896fe29 | bellard | break;
|
921 | c896fe29 | bellard | case INDEX_op_ld_i64:
|
922 | c896fe29 | bellard | /* movq */
|
923 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]); |
924 | c896fe29 | bellard | break;
|
925 | c896fe29 | bellard | |
926 | c896fe29 | bellard | case INDEX_op_st8_i32:
|
927 | c896fe29 | bellard | case INDEX_op_st8_i64:
|
928 | c896fe29 | bellard | /* movb */
|
929 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x88 | P_REX, args[0], args[1], args[2]); |
930 | c896fe29 | bellard | break;
|
931 | c896fe29 | bellard | case INDEX_op_st16_i32:
|
932 | c896fe29 | bellard | case INDEX_op_st16_i64:
|
933 | c896fe29 | bellard | /* movw */
|
934 | c896fe29 | bellard | tcg_out8(s, 0x66);
|
935 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]); |
936 | c896fe29 | bellard | break;
|
937 | c896fe29 | bellard | case INDEX_op_st_i32:
|
938 | c896fe29 | bellard | case INDEX_op_st32_i64:
|
939 | c896fe29 | bellard | /* movl */
|
940 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]); |
941 | c896fe29 | bellard | break;
|
942 | c896fe29 | bellard | case INDEX_op_st_i64:
|
943 | c896fe29 | bellard | /* movq */
|
944 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]); |
945 | c896fe29 | bellard | break;
|
946 | c896fe29 | bellard | |
947 | c896fe29 | bellard | case INDEX_op_sub_i32:
|
948 | c896fe29 | bellard | c = ARITH_SUB; |
949 | c896fe29 | bellard | goto gen_arith32;
|
950 | c896fe29 | bellard | case INDEX_op_and_i32:
|
951 | c896fe29 | bellard | c = ARITH_AND; |
952 | c896fe29 | bellard | goto gen_arith32;
|
953 | c896fe29 | bellard | case INDEX_op_or_i32:
|
954 | c896fe29 | bellard | c = ARITH_OR; |
955 | c896fe29 | bellard | goto gen_arith32;
|
956 | c896fe29 | bellard | case INDEX_op_xor_i32:
|
957 | c896fe29 | bellard | c = ARITH_XOR; |
958 | c896fe29 | bellard | goto gen_arith32;
|
959 | c896fe29 | bellard | case INDEX_op_add_i32:
|
960 | c896fe29 | bellard | c = ARITH_ADD; |
961 | c896fe29 | bellard | gen_arith32:
|
962 | c896fe29 | bellard | if (const_args[2]) { |
963 | c896fe29 | bellard | tgen_arithi32(s, c, args[0], args[2]); |
964 | c896fe29 | bellard | } else {
|
965 | c896fe29 | bellard | tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]); |
966 | c896fe29 | bellard | } |
967 | c896fe29 | bellard | break;
|
968 | c896fe29 | bellard | |
969 | c896fe29 | bellard | case INDEX_op_sub_i64:
|
970 | c896fe29 | bellard | c = ARITH_SUB; |
971 | c896fe29 | bellard | goto gen_arith64;
|
972 | c896fe29 | bellard | case INDEX_op_and_i64:
|
973 | c896fe29 | bellard | c = ARITH_AND; |
974 | c896fe29 | bellard | goto gen_arith64;
|
975 | c896fe29 | bellard | case INDEX_op_or_i64:
|
976 | c896fe29 | bellard | c = ARITH_OR; |
977 | c896fe29 | bellard | goto gen_arith64;
|
978 | c896fe29 | bellard | case INDEX_op_xor_i64:
|
979 | c896fe29 | bellard | c = ARITH_XOR; |
980 | c896fe29 | bellard | goto gen_arith64;
|
981 | c896fe29 | bellard | case INDEX_op_add_i64:
|
982 | c896fe29 | bellard | c = ARITH_ADD; |
983 | c896fe29 | bellard | gen_arith64:
|
984 | c896fe29 | bellard | if (const_args[2]) { |
985 | c896fe29 | bellard | tgen_arithi64(s, c, args[0], args[2]); |
986 | c896fe29 | bellard | } else {
|
987 | c896fe29 | bellard | tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]); |
988 | c896fe29 | bellard | } |
989 | c896fe29 | bellard | break;
|
990 | c896fe29 | bellard | |
991 | c896fe29 | bellard | case INDEX_op_mul_i32:
|
992 | c896fe29 | bellard | if (const_args[2]) { |
993 | c896fe29 | bellard | int32_t val; |
994 | c896fe29 | bellard | val = args[2];
|
995 | c896fe29 | bellard | if (val == (int8_t)val) {
|
996 | c896fe29 | bellard | tcg_out_modrm(s, 0x6b, args[0], args[0]); |
997 | c896fe29 | bellard | tcg_out8(s, val); |
998 | c896fe29 | bellard | } else {
|
999 | c896fe29 | bellard | tcg_out_modrm(s, 0x69, args[0], args[0]); |
1000 | c896fe29 | bellard | tcg_out32(s, val); |
1001 | c896fe29 | bellard | } |
1002 | c896fe29 | bellard | } else {
|
1003 | c896fe29 | bellard | tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]); |
1004 | c896fe29 | bellard | } |
1005 | c896fe29 | bellard | break;
|
1006 | c896fe29 | bellard | case INDEX_op_mul_i64:
|
1007 | c896fe29 | bellard | if (const_args[2]) { |
1008 | c896fe29 | bellard | int32_t val; |
1009 | c896fe29 | bellard | val = args[2];
|
1010 | c896fe29 | bellard | if (val == (int8_t)val) {
|
1011 | c896fe29 | bellard | tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]); |
1012 | c896fe29 | bellard | tcg_out8(s, val); |
1013 | c896fe29 | bellard | } else {
|
1014 | c896fe29 | bellard | tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]); |
1015 | c896fe29 | bellard | tcg_out32(s, val); |
1016 | c896fe29 | bellard | } |
1017 | c896fe29 | bellard | } else {
|
1018 | c896fe29 | bellard | tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]); |
1019 | c896fe29 | bellard | } |
1020 | c896fe29 | bellard | break;
|
1021 | c896fe29 | bellard | case INDEX_op_div2_i32:
|
1022 | c896fe29 | bellard | tcg_out_modrm(s, 0xf7, 7, args[4]); |
1023 | c896fe29 | bellard | break;
|
1024 | c896fe29 | bellard | case INDEX_op_divu2_i32:
|
1025 | c896fe29 | bellard | tcg_out_modrm(s, 0xf7, 6, args[4]); |
1026 | c896fe29 | bellard | break;
|
1027 | c896fe29 | bellard | case INDEX_op_div2_i64:
|
1028 | c896fe29 | bellard | tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]); |
1029 | c896fe29 | bellard | break;
|
1030 | c896fe29 | bellard | case INDEX_op_divu2_i64:
|
1031 | c896fe29 | bellard | tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]); |
1032 | c896fe29 | bellard | break;
|
1033 | c896fe29 | bellard | |
1034 | c896fe29 | bellard | case INDEX_op_shl_i32:
|
1035 | c896fe29 | bellard | c = SHIFT_SHL; |
1036 | c896fe29 | bellard | gen_shift32:
|
1037 | c896fe29 | bellard | if (const_args[2]) { |
1038 | c896fe29 | bellard | if (args[2] == 1) { |
1039 | c896fe29 | bellard | tcg_out_modrm(s, 0xd1, c, args[0]); |
1040 | c896fe29 | bellard | } else {
|
1041 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, c, args[0]); |
1042 | c896fe29 | bellard | tcg_out8(s, args[2]);
|
1043 | c896fe29 | bellard | } |
1044 | c896fe29 | bellard | } else {
|
1045 | c896fe29 | bellard | tcg_out_modrm(s, 0xd3, c, args[0]); |
1046 | c896fe29 | bellard | } |
1047 | c896fe29 | bellard | break;
|
1048 | c896fe29 | bellard | case INDEX_op_shr_i32:
|
1049 | c896fe29 | bellard | c = SHIFT_SHR; |
1050 | c896fe29 | bellard | goto gen_shift32;
|
1051 | c896fe29 | bellard | case INDEX_op_sar_i32:
|
1052 | c896fe29 | bellard | c = SHIFT_SAR; |
1053 | c896fe29 | bellard | goto gen_shift32;
|
1054 | c896fe29 | bellard | |
1055 | c896fe29 | bellard | case INDEX_op_shl_i64:
|
1056 | c896fe29 | bellard | c = SHIFT_SHL; |
1057 | c896fe29 | bellard | gen_shift64:
|
1058 | c896fe29 | bellard | if (const_args[2]) { |
1059 | c896fe29 | bellard | if (args[2] == 1) { |
1060 | c896fe29 | bellard | tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]); |
1061 | c896fe29 | bellard | } else {
|
1062 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]); |
1063 | c896fe29 | bellard | tcg_out8(s, args[2]);
|
1064 | c896fe29 | bellard | } |
1065 | c896fe29 | bellard | } else {
|
1066 | c896fe29 | bellard | tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]); |
1067 | c896fe29 | bellard | } |
1068 | c896fe29 | bellard | break;
|
1069 | c896fe29 | bellard | case INDEX_op_shr_i64:
|
1070 | c896fe29 | bellard | c = SHIFT_SHR; |
1071 | c896fe29 | bellard | goto gen_shift64;
|
1072 | c896fe29 | bellard | case INDEX_op_sar_i64:
|
1073 | c896fe29 | bellard | c = SHIFT_SAR; |
1074 | c896fe29 | bellard | goto gen_shift64;
|
1075 | c896fe29 | bellard | |
1076 | c896fe29 | bellard | case INDEX_op_brcond_i32:
|
1077 | c896fe29 | bellard | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
1078 | c896fe29 | bellard | args[3], 0); |
1079 | c896fe29 | bellard | break;
|
1080 | c896fe29 | bellard | case INDEX_op_brcond_i64:
|
1081 | c896fe29 | bellard | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
1082 | c896fe29 | bellard | args[3], P_REXW);
|
1083 | c896fe29 | bellard | break;
|
1084 | c896fe29 | bellard | |
1085 | c896fe29 | bellard | case INDEX_op_bswap_i32:
|
1086 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0); |
1087 | c896fe29 | bellard | break;
|
1088 | c896fe29 | bellard | case INDEX_op_bswap_i64:
|
1089 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0); |
1090 | c896fe29 | bellard | break;
|
1091 | c896fe29 | bellard | |
1092 | c896fe29 | bellard | case INDEX_op_qemu_ld8u:
|
1093 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 0);
|
1094 | c896fe29 | bellard | break;
|
1095 | c896fe29 | bellard | case INDEX_op_qemu_ld8s:
|
1096 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 0 | 4); |
1097 | c896fe29 | bellard | break;
|
1098 | c896fe29 | bellard | case INDEX_op_qemu_ld16u:
|
1099 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 1);
|
1100 | c896fe29 | bellard | break;
|
1101 | c896fe29 | bellard | case INDEX_op_qemu_ld16s:
|
1102 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 1 | 4); |
1103 | c896fe29 | bellard | break;
|
1104 | c896fe29 | bellard | case INDEX_op_qemu_ld32u:
|
1105 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 2);
|
1106 | c896fe29 | bellard | break;
|
1107 | c896fe29 | bellard | case INDEX_op_qemu_ld32s:
|
1108 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 2 | 4); |
1109 | c896fe29 | bellard | break;
|
1110 | c896fe29 | bellard | case INDEX_op_qemu_ld64:
|
1111 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 3);
|
1112 | c896fe29 | bellard | break;
|
1113 | c896fe29 | bellard | |
1114 | c896fe29 | bellard | case INDEX_op_qemu_st8:
|
1115 | c896fe29 | bellard | tcg_out_qemu_st(s, args, 0);
|
1116 | c896fe29 | bellard | break;
|
1117 | c896fe29 | bellard | case INDEX_op_qemu_st16:
|
1118 | c896fe29 | bellard | tcg_out_qemu_st(s, args, 1);
|
1119 | c896fe29 | bellard | break;
|
1120 | c896fe29 | bellard | case INDEX_op_qemu_st32:
|
1121 | c896fe29 | bellard | tcg_out_qemu_st(s, args, 2);
|
1122 | c896fe29 | bellard | break;
|
1123 | c896fe29 | bellard | case INDEX_op_qemu_st64:
|
1124 | c896fe29 | bellard | tcg_out_qemu_st(s, args, 3);
|
1125 | c896fe29 | bellard | break;
|
1126 | c896fe29 | bellard | |
1127 | c896fe29 | bellard | default:
|
1128 | c896fe29 | bellard | tcg_abort(); |
1129 | c896fe29 | bellard | } |
1130 | c896fe29 | bellard | } |
1131 | c896fe29 | bellard | |
1132 | c896fe29 | bellard | static const TCGTargetOpDef x86_64_op_defs[] = { |
1133 | c896fe29 | bellard | { INDEX_op_exit_tb, { } }, |
1134 | c896fe29 | bellard | { INDEX_op_goto_tb, { } }, |
1135 | c896fe29 | bellard | { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */ |
1136 | c896fe29 | bellard | { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */ |
1137 | c896fe29 | bellard | { INDEX_op_br, { } }, |
1138 | c896fe29 | bellard | |
1139 | c896fe29 | bellard | { INDEX_op_mov_i32, { "r", "r" } }, |
1140 | c896fe29 | bellard | { INDEX_op_movi_i32, { "r" } },
|
1141 | c896fe29 | bellard | { INDEX_op_ld8u_i32, { "r", "r" } }, |
1142 | c896fe29 | bellard | { INDEX_op_ld8s_i32, { "r", "r" } }, |
1143 | c896fe29 | bellard | { INDEX_op_ld16u_i32, { "r", "r" } }, |
1144 | c896fe29 | bellard | { INDEX_op_ld16s_i32, { "r", "r" } }, |
1145 | c896fe29 | bellard | { INDEX_op_ld_i32, { "r", "r" } }, |
1146 | c896fe29 | bellard | { INDEX_op_st8_i32, { "r", "r" } }, |
1147 | c896fe29 | bellard | { INDEX_op_st16_i32, { "r", "r" } }, |
1148 | c896fe29 | bellard | { INDEX_op_st_i32, { "r", "r" } }, |
1149 | c896fe29 | bellard | |
1150 | c896fe29 | bellard | { INDEX_op_add_i32, { "r", "0", "ri" } }, |
1151 | c896fe29 | bellard | { INDEX_op_mul_i32, { "r", "0", "ri" } }, |
1152 | c896fe29 | bellard | { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } }, |
1153 | c896fe29 | bellard | { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } }, |
1154 | c896fe29 | bellard | { INDEX_op_sub_i32, { "r", "0", "ri" } }, |
1155 | c896fe29 | bellard | { INDEX_op_and_i32, { "r", "0", "ri" } }, |
1156 | c896fe29 | bellard | { INDEX_op_or_i32, { "r", "0", "ri" } }, |
1157 | c896fe29 | bellard | { INDEX_op_xor_i32, { "r", "0", "ri" } }, |
1158 | c896fe29 | bellard | |
1159 | c896fe29 | bellard | { INDEX_op_shl_i32, { "r", "0", "ci" } }, |
1160 | c896fe29 | bellard | { INDEX_op_shr_i32, { "r", "0", "ci" } }, |
1161 | c896fe29 | bellard | { INDEX_op_sar_i32, { "r", "0", "ci" } }, |
1162 | c896fe29 | bellard | |
1163 | c896fe29 | bellard | { INDEX_op_brcond_i32, { "r", "ri" } }, |
1164 | c896fe29 | bellard | |
1165 | c896fe29 | bellard | { INDEX_op_mov_i64, { "r", "r" } }, |
1166 | c896fe29 | bellard | { INDEX_op_movi_i64, { "r" } },
|
1167 | c896fe29 | bellard | { INDEX_op_ld8u_i64, { "r", "r" } }, |
1168 | c896fe29 | bellard | { INDEX_op_ld8s_i64, { "r", "r" } }, |
1169 | c896fe29 | bellard | { INDEX_op_ld16u_i64, { "r", "r" } }, |
1170 | c896fe29 | bellard | { INDEX_op_ld16s_i64, { "r", "r" } }, |
1171 | c896fe29 | bellard | { INDEX_op_ld32u_i64, { "r", "r" } }, |
1172 | c896fe29 | bellard | { INDEX_op_ld32s_i64, { "r", "r" } }, |
1173 | c896fe29 | bellard | { INDEX_op_ld_i64, { "r", "r" } }, |
1174 | c896fe29 | bellard | { INDEX_op_st8_i64, { "r", "r" } }, |
1175 | c896fe29 | bellard | { INDEX_op_st16_i64, { "r", "r" } }, |
1176 | c896fe29 | bellard | { INDEX_op_st32_i64, { "r", "r" } }, |
1177 | c896fe29 | bellard | { INDEX_op_st_i64, { "r", "r" } }, |
1178 | c896fe29 | bellard | |
1179 | c896fe29 | bellard | { INDEX_op_add_i64, { "r", "0", "re" } }, |
1180 | c896fe29 | bellard | { INDEX_op_mul_i64, { "r", "0", "re" } }, |
1181 | c896fe29 | bellard | { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } }, |
1182 | c896fe29 | bellard | { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } }, |
1183 | c896fe29 | bellard | { INDEX_op_sub_i64, { "r", "0", "re" } }, |
1184 | c896fe29 | bellard | { INDEX_op_and_i64, { "r", "0", "reZ" } }, |
1185 | c896fe29 | bellard | { INDEX_op_or_i64, { "r", "0", "re" } }, |
1186 | c896fe29 | bellard | { INDEX_op_xor_i64, { "r", "0", "re" } }, |
1187 | c896fe29 | bellard | |
1188 | c896fe29 | bellard | { INDEX_op_shl_i64, { "r", "0", "ci" } }, |
1189 | c896fe29 | bellard | { INDEX_op_shr_i64, { "r", "0", "ci" } }, |
1190 | c896fe29 | bellard | { INDEX_op_sar_i64, { "r", "0", "ci" } }, |
1191 | c896fe29 | bellard | |
1192 | c896fe29 | bellard | { INDEX_op_brcond_i64, { "r", "re" } }, |
1193 | c896fe29 | bellard | |
1194 | c896fe29 | bellard | { INDEX_op_bswap_i32, { "r", "0" } }, |
1195 | c896fe29 | bellard | { INDEX_op_bswap_i64, { "r", "0" } }, |
1196 | c896fe29 | bellard | |
1197 | c896fe29 | bellard | { INDEX_op_qemu_ld8u, { "r", "L" } }, |
1198 | c896fe29 | bellard | { INDEX_op_qemu_ld8s, { "r", "L" } }, |
1199 | c896fe29 | bellard | { INDEX_op_qemu_ld16u, { "r", "L" } }, |
1200 | c896fe29 | bellard | { INDEX_op_qemu_ld16s, { "r", "L" } }, |
1201 | c896fe29 | bellard | { INDEX_op_qemu_ld32u, { "r", "L" } }, |
1202 | c896fe29 | bellard | { INDEX_op_qemu_ld32s, { "r", "L" } }, |
1203 | c896fe29 | bellard | { INDEX_op_qemu_ld64, { "r", "L" } }, |
1204 | c896fe29 | bellard | |
1205 | c896fe29 | bellard | { INDEX_op_qemu_st8, { "L", "L" } }, |
1206 | c896fe29 | bellard | { INDEX_op_qemu_st16, { "L", "L" } }, |
1207 | c896fe29 | bellard | { INDEX_op_qemu_st32, { "L", "L" } }, |
1208 | c896fe29 | bellard | { INDEX_op_qemu_st64, { "L", "L", "L" } }, |
1209 | c896fe29 | bellard | |
1210 | c896fe29 | bellard | { -1 },
|
1211 | c896fe29 | bellard | }; |
1212 | c896fe29 | bellard | |
1213 | c896fe29 | bellard | void tcg_target_init(TCGContext *s)
|
1214 | c896fe29 | bellard | { |
1215 | c896fe29 | bellard | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); |
1216 | c896fe29 | bellard | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff); |
1217 | c896fe29 | bellard | tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
1218 | c896fe29 | bellard | (1 << TCG_REG_RDI) |
|
1219 | c896fe29 | bellard | (1 << TCG_REG_RSI) |
|
1220 | c896fe29 | bellard | (1 << TCG_REG_RDX) |
|
1221 | c896fe29 | bellard | (1 << TCG_REG_RCX) |
|
1222 | c896fe29 | bellard | (1 << TCG_REG_R8) |
|
1223 | c896fe29 | bellard | (1 << TCG_REG_R9) |
|
1224 | c896fe29 | bellard | (1 << TCG_REG_RAX) |
|
1225 | c896fe29 | bellard | (1 << TCG_REG_R10) |
|
1226 | c896fe29 | bellard | (1 << TCG_REG_R11));
|
1227 | c896fe29 | bellard | |
1228 | c896fe29 | bellard | tcg_regset_clear(s->reserved_regs); |
1229 | c896fe29 | bellard | tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP); |
1230 | c896fe29 | bellard | /* XXX: will be suppresed when proper global TB entry code will be
|
1231 | c896fe29 | bellard | generated */
|
1232 | c896fe29 | bellard | tcg_regset_set_reg(s->reserved_regs, TCG_REG_RBX); |
1233 | c896fe29 | bellard | tcg_regset_set_reg(s->reserved_regs, TCG_REG_RBP); |
1234 | c896fe29 | bellard | |
1235 | c896fe29 | bellard | tcg_add_target_add_op_defs(x86_64_op_defs); |
1236 | c896fe29 | bellard | } |