Revision f54b3f92

b/Makefile.target
128 128
CFLAGS+=-msmall-data
129 129
endif
130 130

  
131
ifeq ($(ARCH),hppa)
132
OP_CFLAGS=-O1 -fno-delayed-branch
133
BASE_LDFLAGS+=-Wl,-T,$(SRC_PATH)/$(ARCH).ld
134
endif
135

  
131 136
ifeq ($(ARCH),ia64)
132 137
CFLAGS+=-mno-sdata
133 138
OP_CFLAGS+=-mno-sdata
......
267 272
ifeq ($(findstring sh4, $(TARGET_ARCH) $(ARCH)),sh4)
268 273
LIBOBJS+=sh4-dis.o
269 274
endif
275
ifeq ($(findstring hppa, $(TARGET_BASE_ARCH) $(ARCH)),hppa)
276
LIBOBJS+=hppa-dis.o
277
endif
270 278
ifeq ($(findstring s390, $(TARGET_ARCH) $(ARCH)),s390)
271 279
LIBOBJS+=s390-dis.o
272 280
endif
b/configure
50 50
  cris)
51 51
    cpu="cris"
52 52
  ;;
53
  parisc|parisc64)
54
    cpu="hppa"
55
  ;;
53 56
  ia64)
54 57
    cpu="ia64"
55 58
  ;;
......
576 579

  
577 580
# if cross compiling, cannot launch a program, so make a static guess
578 581
if test "$cpu" = "armv4b" \
582
     -o "$cpu" = "hppa" \
579 583
     -o "$cpu" = "m68k" \
580 584
     -o "$cpu" = "mips" \
581 585
     -o "$cpu" = "mips64" \
......
865 869
elif test "$cpu" = "cris" ; then
866 870
  echo "ARCH=cris" >> $config_mak
867 871
  echo "#define HOST_CRIS 1" >> $config_h
872
elif test "$cpu" = "hppa" ; then
873
  echo "ARCH=hppa" >> $config_mak
874
  echo "#define HOST_HPPA 1" >> $config_h
868 875
elif test "$cpu" = "ia64" ; then
869 876
  echo "ARCH=ia64" >> $config_mak
870 877
  echo "#define HOST_IA64 1" >> $config_h
b/cpu-all.h
20 20
#ifndef CPU_ALL_H
21 21
#define CPU_ALL_H
22 22

  
23
#if defined(__arm__) || defined(__sparc__) || defined(__mips__)
23
#if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__)
24 24
#define WORDS_ALIGNED
25 25
#endif
26 26

  
......
952 952
    return val;
953 953
}
954 954

  
955
#elif defined(__hppa__)
956

  
957
static inline int64_t cpu_get_real_ticks(void)
958
{
959
    int val;
960
    asm volatile ("mfctl %%cr16, %0" : "=r"(val));
961
    return val;
962
}
963

  
955 964
#elif defined(__ia64)
956 965

  
957 966
static inline int64_t cpu_get_real_ticks(void)
b/cpu-exec.c
657 657
                                       "o0", "o1", "o2", "o3", "o4", "o5",
658 658
                                       "l0", "l1", "l2", "l3", "l4", "l5",
659 659
                                       "l6", "l7");
660
#elif defined(__hppa__)
661
                asm volatile ("ble  0(%%sr4,%1)\n"
662
                              "copy %%r31,%%r18\n"
663
                              "copy %%r28,%0\n"
664
                              : "=r" (T0)
665
                              : "r" (gen_func)
666
                              : "r1", "r2", "r3", "r4", "r5", "r6", "r7",
667
                                "r8", "r9", "r10", "r11", "r12", "r13",
668
                                "r18", "r19", "r20", "r21", "r22", "r23",
669
                                "r24", "r25", "r26", "r27", "r28", "r29",
670
                                "r30", "r31");
660 671
#elif defined(__arm__)
661 672
                asm volatile ("mov pc, %0\n\t"
662 673
                              ".global exec_loop\n\t"
......
1488 1499
                             is_write, &uc->uc_sigmask, puc);
1489 1500
}
1490 1501

  
1502
#elif defined(__hppa__)
1503

  
1504
int cpu_signal_handler(int host_signum, void *pinfo,
1505
                       void *puc)
1506
{
1507
    struct siginfo *info = pinfo;
1508
    struct ucontext *uc = puc;
1509
    unsigned long pc;
1510
    int is_write;
1511

  
1512
    pc = uc->uc_mcontext.sc_iaoq[0];
1513
    /* FIXME: compute is_write */
1514
    is_write = 0;
1515
    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
1516
                             is_write,
1517
                             &uc->uc_sigmask, puc);
1518
}
1519

  
1491 1520
#else
1492 1521

  
1493 1522
#error host CPU specific signal handler needed
b/dis-asm.h
157 157
#define bfd_mach_ppc_7400      7400
158 158
  bfd_arch_rs6000,     /* IBM RS/6000 */
159 159
  bfd_arch_hppa,       /* HP PA RISC */
160
#define bfd_mach_hppa10        10
161
#define bfd_mach_hppa11        11
162
#define bfd_mach_hppa20        20
163
#define bfd_mach_hppa20w       25
160 164
  bfd_arch_d10v,       /* Mitsubishi D10V */
161 165
  bfd_arch_z8k,        /* Zilog Z8000 */
162 166
#define bfd_mach_z8001         1
b/disas.c
279 279
    print_insn = print_insn_m68k;
280 280
#elif defined(__s390__)
281 281
    print_insn = print_insn_s390;
282
#elif defined(__hppa__)
283
    print_insn = print_insn_hppa;
282 284
#else
283 285
    fprintf(out, "0x%lx: Asm output not supported on this arch\n",
284 286
	    (long) code);
b/dyngen-exec.h
124 124
#define AREG1 "r4"
125 125
#define AREG2 "r5"
126 126
#define AREG3 "r6"
127
#elif defined(__hppa__)
128
#define AREG0 "r17"
129
#define AREG1 "r14"
130
#define AREG2 "r15"
131
#define AREG3 "r16"
127 132
#elif defined(__mips__)
128 133
#define AREG0 "fp"
129 134
#define AREG1 "s0"
......
279 284
#elif defined(__mips__)
280 285
#define EXIT_TB() asm volatile ("jr $ra")
281 286
#define GOTO_LABEL_PARAM(n) asm volatile (".set noat; la $1, " ASM_NAME(__op_gen_label) #n "; jr $1; .set at")
287
#elif defined(__hppa__)
288
#define GOTO_LABEL_PARAM(n) asm volatile ("b,n " ASM_NAME(__op_gen_label) #n)
282 289
#else
283 290
#error unsupported CPU
284 291
#endif
b/dyngen.c
117 117
#define elf_check_arch(x) ((x) == EM_68K)
118 118
#define ELF_USES_RELOCA
119 119

  
120
#elif defined(HOST_HPPA)
121

  
122
#define ELF_CLASS   ELFCLASS32
123
#define ELF_ARCH    EM_PARISC
124
#define elf_check_arch(x) ((x) == EM_PARISC)
125
#define ELF_USES_RELOCA
126

  
120 127
#elif defined(HOST_MIPS)
121 128

  
122 129
#define ELF_CLASS	ELFCLASS32
......
1223 1230
        snprintf(name, name_size, "param%s", p);
1224 1231
        return 1;
1225 1232
    } else {
1226
#ifdef HOST_SPARC
1233
#if defined(HOST_SPARC) || defined(HOST_HPPA)
1227 1234
        if (sym_name[0] == '.')
1228 1235
            snprintf(name, name_size,
1229 1236
                     "(long)(&__dot_%s)",
......
1661 1668
            error("rts expected at the end of %s", name);
1662 1669
        copy_size = p - p_start;
1663 1670
    }
1671
#elif defined(HOST_HPPA)
1672
    {
1673
        uint8_t *p;
1674
        p = p_start;
1675
        while (p < p_end) {
1676
            uint32_t insn = get32((uint32_t *)p);
1677
            if (insn == 0x6bc23fd9 ||                /* stw rp,-14(sp) */
1678
                insn == 0x08030241 ||                /* copy r3,r1 */
1679
                insn == 0x081e0243 ||                /* copy sp,r3 */
1680
                (insn & 0xffffc000) == 0x37de0000 || /* ldo x(sp),sp */
1681
                (insn & 0xffffc000) == 0x6fc10000)   /* stwm r1,x(sp) */
1682
                p += 4;
1683
            else
1684
                break;
1685
        }
1686
        start_offset += p - p_start;
1687
        p_start = p;
1688
        p = p_end - 4;
1689

  
1690
        while (p > p_start) {
1691
            uint32_t insn = get32((uint32_t *)p);
1692
            if ((insn & 0xffffc000) == 0x347e0000 || /* ldo x(r3),sp */
1693
                (insn & 0xffe0c000) == 0x4fc00000 || /* ldwm x(sp),rx */
1694
                (insn & 0xffffc000) == 0x37de0000 || /* ldo x(sp),sp */
1695
                insn == 0x48623fd9 ||                /* ldw -14(r3),rp */
1696
                insn == 0xe840c000 ||                /* bv r0(rp) */
1697
                insn == 0xe840c002)                  /* bv,n r0(rp) */
1698
                p -= 4;
1699
            else
1700
                break;
1701
        }
1702
        p += 4;
1703
        if (p <= p_start)
1704
            error("empty code for %s", name);
1705

  
1706
        copy_size = p - p_start;
1707
    }
1664 1708
#elif defined(HOST_MIPS) || defined(HOST_MIPS64)
1665 1709
    {
1666 1710
#define INSN_RETURN     0x03e00008
......
1746 1790
                    !strstart(sym_name, "__op_param", NULL) &&
1747 1791
                    !strstart(sym_name, "__op_jmp", NULL) &&
1748 1792
                    !strstart(sym_name, "__op_gen_label", NULL)) {
1749
#if defined(HOST_SPARC)
1793
#if defined(HOST_SPARC) || defined(HOST_HPPA)
1750 1794
		    if (sym_name[0] == '.') {
1751 1795
			fprintf(outfile,
1752 1796
				"extern char __dot_%s __asm__(\"%s\");\n",
......
1774 1818
            }
1775 1819
        }
1776 1820

  
1821
#ifdef __hppa__
1822
        fprintf(outfile, "    memcpy(gen_code_ptr, (void *)((char *)__canonicalize_funcptr_for_compare(%s)+%d), %d);\n",
1823
					name, (int)(start_offset - offset), copy_size);
1824
#else
1777 1825
        fprintf(outfile, "    memcpy(gen_code_ptr, (void *)((char *)&%s+%d), %d);\n",
1778 1826
					name, (int)(start_offset - offset), copy_size);
1827
#endif
1779 1828

  
1780 1829
        /* emit code offset information */
1781 1830
        {
......
2581 2630
                }
2582 2631
                }
2583 2632
            }
2633
#elif defined(HOST_HPPA)
2634
            {
2635
                char relname[256];
2636
                int type, is_label;
2637
                int addend;
2638
                int reloc_offset;
2639
                for (i = 0, rel = relocs; i < nb_relocs; i++, rel++) {
2640
                if (rel->r_offset >= start_offset &&
2641
                    rel->r_offset < start_offset + copy_size) {
2642
                    sym_name = get_rel_sym_name(rel);
2643
                    sym_name = strtab + symtab[ELF32_R_SYM(rel->r_info)].st_name;
2644
                    is_label = get_reloc_expr(relname, sizeof(relname), sym_name);
2645
                    type = ELF32_R_TYPE(rel->r_info);
2646
                    addend = rel->r_addend;
2647
                    reloc_offset = rel->r_offset - start_offset;
2648

  
2649
                    if (is_label) {
2650
                        switch (type) {
2651
                        case R_PARISC_PCREL17F:
2652
                            fprintf(outfile,
2653
"    tcg_out_reloc(s, gen_code_ptr + %d, %d, %s, %d);\n",
2654
                                    reloc_offset, type, relname, addend);
2655
                            break;
2656
                        default:
2657
                            error("unsupported hppa label relocation (%d)", type);
2658
                        }
2659
                    } else {
2660
                        switch (type) {
2661
                        case R_PARISC_DIR21L:
2662
                            fprintf(outfile,
2663
"    hppa_patch21l((uint32_t *)(gen_code_ptr + %d), %s, %d);\n",
2664
                                    reloc_offset, relname, addend);
2665
                            break;
2666
                        case R_PARISC_DIR14R:
2667
                            fprintf(outfile,
2668
"    hppa_patch14r((uint32_t *)(gen_code_ptr + %d), %s, %d);\n",
2669
                                    reloc_offset, relname, addend);
2670
                            break;
2671
                        case R_PARISC_PCREL17F:
2672
                            if (strstart(sym_name, "__op_gen_label", NULL)) {
2673
                                fprintf(outfile,
2674
"    hppa_patch17f((uint32_t *)(gen_code_ptr + %d), %s, %d);\n",
2675
                                        reloc_offset, relname, addend);
2676
                            } else {
2677
                                fprintf(outfile,
2678
"    HPPA_RECORD_BRANCH(hppa_stubs, (uint32_t *)(gen_code_ptr + %d), %s);\n",
2679
                                        reloc_offset, relname);
2680
                            }
2681
                            break;
2682
                        case R_PARISC_DPREL21L:
2683
                            if (strstart(sym_name, "__op_param", &p))
2684
                                fprintf(outfile,
2685
"    hppa_load_imm21l((uint32_t *)(gen_code_ptr + %d), param%s, %d);\n",
2686
                                        reloc_offset, p, addend);
2687
                            else
2688
                                fprintf(outfile,
2689
"    hppa_patch21l_dprel((uint32_t *)(gen_code_ptr + %d), %s, %d);\n",
2690
                                        reloc_offset, relname, addend);
2691
                            break;
2692
                        case R_PARISC_DPREL14R:
2693
                            if (strstart(sym_name, "__op_param", &p))
2694
                                fprintf(outfile,
2695
"    hppa_load_imm14r((uint32_t *)(gen_code_ptr + %d), param%s, %d);\n",
2696
                                        reloc_offset, p, addend);
2697
                            else
2698
                                fprintf(outfile,
2699
"    hppa_patch14r_dprel((uint32_t *)(gen_code_ptr + %d), %s, %d);\n",
2700
                                        reloc_offset, relname, addend);
2701
                            break;
2702
                        default:
2703
                            error("unsupported hppa relocation (%d)", type);
2704
                        }
2705
                    }
2706
                }
2707
                }
2708
            }
2584 2709
#elif defined(HOST_MIPS) || defined(HOST_MIPS64)
2585 2710
            {
2586 2711
                for (i = 0, rel = relocs; i < nb_relocs; i++, rel++) {
b/hppa-dis.c
1
/* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c.
2
   Copyright 1989, 1990, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2003,
3
   2005 Free Software Foundation, Inc.
4

  
5
   Contributed by the Center for Software Science at the
6
   University of Utah (pa-gdb-bugs@cs.utah.edu).
7

  
8
   This program is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 2 of the License, or
11
   (at your option) any later version.
12

  
13
   This program is distributed in the hope that it will be useful,
14
   but WITHOUT ANY WARRANTY; without even the implied warranty of
15
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
   GNU General Public License for more details.
17

  
18
   You should have received a copy of the GNU General Public License
19
   along with this program; if not, write to the Free Software
20
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21
   MA 02110-1301, USA.  */
22

  
23
#include "dis-asm.h"
24

  
25
/* HP PA-RISC SOM object file format:  definitions internal to BFD.
26
   Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,
27
   2003 Free Software Foundation, Inc.
28

  
29
   Contributed by the Center for Software Science at the
30
   University of Utah (pa-gdb-bugs@cs.utah.edu).
31

  
32
   This file is part of BFD, the Binary File Descriptor library.
33

  
34
   This program is free software; you can redistribute it and/or modify
35
   it under the terms of the GNU General Public License as published by
36
   the Free Software Foundation; either version 2 of the License, or
37
   (at your option) any later version.
38

  
39
   This program is distributed in the hope that it will be useful,
40
   but WITHOUT ANY WARRANTY; without even the implied warranty of
41
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
42
   GNU General Public License for more details.
43

  
44
   You should have received a copy of the GNU General Public License
45
   along with this program; if not, write to the Free Software
46
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
47

  
48
#ifndef _LIBHPPA_H
49
#define _LIBHPPA_H
50

  
51
#define BYTES_IN_WORD 4
52
#define PA_PAGESIZE 0x1000
53

  
54
/* The PA instruction set variants.  */
55
enum pa_arch {pa10 = 10, pa11 = 11, pa20 = 20, pa20w = 25};
56

  
57
/* HP PA-RISC relocation types */
58

  
59
enum hppa_reloc_field_selector_type
60
  {
61
    R_HPPA_FSEL = 0x0,
62
    R_HPPA_LSSEL = 0x1,
63
    R_HPPA_RSSEL = 0x2,
64
    R_HPPA_LSEL = 0x3,
65
    R_HPPA_RSEL = 0x4,
66
    R_HPPA_LDSEL = 0x5,
67
    R_HPPA_RDSEL = 0x6,
68
    R_HPPA_LRSEL = 0x7,
69
    R_HPPA_RRSEL = 0x8,
70
    R_HPPA_NSEL  = 0x9,
71
    R_HPPA_NLSEL  = 0xa,
72
    R_HPPA_NLRSEL  = 0xb,
73
    R_HPPA_PSEL = 0xc,
74
    R_HPPA_LPSEL = 0xd,
75
    R_HPPA_RPSEL = 0xe,
76
    R_HPPA_TSEL = 0xf,
77
    R_HPPA_LTSEL = 0x10,
78
    R_HPPA_RTSEL = 0x11,
79
    R_HPPA_LTPSEL = 0x12,
80
    R_HPPA_RTPSEL = 0x13
81
  };
82

  
83
/* /usr/include/reloc.h defines these to constants.  We want to use
84
   them in enums, so #undef them before we start using them.  We might
85
   be able to fix this another way by simply managing not to include
86
   /usr/include/reloc.h, but currently GDB picks up these defines
87
   somewhere.  */
88
#undef e_fsel
89
#undef e_lssel
90
#undef e_rssel
91
#undef e_lsel
92
#undef e_rsel
93
#undef e_ldsel
94
#undef e_rdsel
95
#undef e_lrsel
96
#undef e_rrsel
97
#undef e_nsel
98
#undef e_nlsel
99
#undef e_nlrsel
100
#undef e_psel
101
#undef e_lpsel
102
#undef e_rpsel
103
#undef e_tsel
104
#undef e_ltsel
105
#undef e_rtsel
106
#undef e_one
107
#undef e_two
108
#undef e_pcrel
109
#undef e_con
110
#undef e_plabel
111
#undef e_abs
112

  
113
/* for compatibility */
114
enum hppa_reloc_field_selector_type_alt
115
  {
116
    e_fsel = R_HPPA_FSEL,
117
    e_lssel = R_HPPA_LSSEL,
118
    e_rssel = R_HPPA_RSSEL,
119
    e_lsel = R_HPPA_LSEL,
120
    e_rsel = R_HPPA_RSEL,
121
    e_ldsel = R_HPPA_LDSEL,
122
    e_rdsel = R_HPPA_RDSEL,
123
    e_lrsel = R_HPPA_LRSEL,
124
    e_rrsel = R_HPPA_RRSEL,
125
    e_nsel = R_HPPA_NSEL,
126
    e_nlsel = R_HPPA_NLSEL,
127
    e_nlrsel = R_HPPA_NLRSEL,
128
    e_psel = R_HPPA_PSEL,
129
    e_lpsel = R_HPPA_LPSEL,
130
    e_rpsel = R_HPPA_RPSEL,
131
    e_tsel = R_HPPA_TSEL,
132
    e_ltsel = R_HPPA_LTSEL,
133
    e_rtsel = R_HPPA_RTSEL,
134
    e_ltpsel = R_HPPA_LTPSEL,
135
    e_rtpsel = R_HPPA_RTPSEL
136
  };
137

  
138
enum hppa_reloc_expr_type
139
  {
140
    R_HPPA_E_ONE = 0,
141
    R_HPPA_E_TWO = 1,
142
    R_HPPA_E_PCREL = 2,
143
    R_HPPA_E_CON = 3,
144
    R_HPPA_E_PLABEL = 7,
145
    R_HPPA_E_ABS = 18
146
  };
147

  
148
/* for compatibility */
149
enum hppa_reloc_expr_type_alt
150
  {
151
    e_one = R_HPPA_E_ONE,
152
    e_two = R_HPPA_E_TWO,
153
    e_pcrel = R_HPPA_E_PCREL,
154
    e_con = R_HPPA_E_CON,
155
    e_plabel = R_HPPA_E_PLABEL,
156
    e_abs = R_HPPA_E_ABS
157
  };
158

  
159

  
160
/* Relocations for function calls must be accompanied by parameter
161
   relocation bits.  These bits describe exactly where the caller has
162
   placed the function's arguments and where it expects to find a return
163
   value.
164

  
165
   Both ELF and SOM encode this information within the addend field
166
   of the call relocation.  (Note this could break very badly if one
167
   was to make a call like bl foo + 0x12345678).
168

  
169
   The high order 10 bits contain parameter relocation information,
170
   the low order 22 bits contain the constant offset.  */
171

  
172
#define HPPA_R_ARG_RELOC(a)	\
173
  (((a) >> 22) & 0x3ff)
174
#define HPPA_R_CONSTANT(a)	\
175
  ((((bfd_signed_vma)(a)) << (BFD_ARCH_SIZE-22)) >> (BFD_ARCH_SIZE-22))
176
#define HPPA_R_ADDEND(r, c)	\
177
  (((r) << 22) + ((c) & 0x3fffff))
178

  
179

  
180
/* Some functions to manipulate PA instructions.  */
181

  
182
/* Declare the functions with the unused attribute to avoid warnings.  */
183
static inline int sign_extend (int, int) ATTRIBUTE_UNUSED;
184
static inline int low_sign_extend (int, int) ATTRIBUTE_UNUSED;
185
static inline int sign_unext (int, int) ATTRIBUTE_UNUSED;
186
static inline int low_sign_unext (int, int) ATTRIBUTE_UNUSED;
187
static inline int re_assemble_3 (int) ATTRIBUTE_UNUSED;
188
static inline int re_assemble_12 (int) ATTRIBUTE_UNUSED;
189
static inline int re_assemble_14 (int) ATTRIBUTE_UNUSED;
190
static inline int re_assemble_16 (int) ATTRIBUTE_UNUSED;
191
static inline int re_assemble_17 (int) ATTRIBUTE_UNUSED;
192
static inline int re_assemble_21 (int) ATTRIBUTE_UNUSED;
193
static inline int re_assemble_22 (int) ATTRIBUTE_UNUSED;
194
static inline bfd_signed_vma hppa_field_adjust
195
  (bfd_vma, bfd_signed_vma, enum hppa_reloc_field_selector_type_alt)
196
  ATTRIBUTE_UNUSED;
197
static inline int hppa_rebuild_insn (int, int, int) ATTRIBUTE_UNUSED;
198

  
199

  
200
/* The *sign_extend functions are used to assemble various bitfields
201
   taken from an instruction and return the resulting immediate
202
   value.  */
203

  
204
static inline int
205
sign_extend (int x, int len)
206
{
207
  int signbit = (1 << (len - 1));
208
  int mask = (signbit << 1) - 1;
209
  return ((x & mask) ^ signbit) - signbit;
210
}
211

  
212
static inline int
213
low_sign_extend (int x, int len)
214
{
215
  return (x >> 1) - ((x & 1) << (len - 1));
216
}
217

  
218

  
219
/* The re_assemble_* functions prepare an immediate value for
220
   insertion into an opcode. pa-risc uses all sorts of weird bitfields
221
   in the instruction to hold the value.  */
222

  
223
static inline int
224
sign_unext (int x, int len)
225
{
226
  int len_ones;
227

  
228
  len_ones = (1 << len) - 1;
229

  
230
  return x & len_ones;
231
}
232

  
233
static inline int
234
low_sign_unext (int x, int len)
235
{
236
  int temp;
237
  int sign;
238

  
239
  sign = (x >> (len-1)) & 1;
240

  
241
  temp = sign_unext (x, len-1);
242

  
243
  return (temp << 1) | sign;
244
}
245

  
246
static inline int
247
re_assemble_3 (int as3)
248
{
249
  return ((  (as3 & 4) << (13-2))
250
	  | ((as3 & 3) << (13+1)));
251
}
252

  
253
static inline int
254
re_assemble_12 (int as12)
255
{
256
  return ((  (as12 & 0x800) >> 11)
257
	  | ((as12 & 0x400) >> (10 - 2))
258
	  | ((as12 & 0x3ff) << (1 + 2)));
259
}
260

  
261
static inline int
262
re_assemble_14 (int as14)
263
{
264
  return ((  (as14 & 0x1fff) << 1)
265
	  | ((as14 & 0x2000) >> 13));
266
}
267

  
268
static inline int
269
re_assemble_16 (int as16)
270
{
271
  int s, t;
272

  
273
  /* Unusual 16-bit encoding, for wide mode only.  */
274
  t = (as16 << 1) & 0xffff;
275
  s = (as16 & 0x8000);
276
  return (t ^ s ^ (s >> 1)) | (s >> 15);
277
}
278

  
279
static inline int
280
re_assemble_17 (int as17)
281
{
282
  return ((  (as17 & 0x10000) >> 16)
283
	  | ((as17 & 0x0f800) << (16 - 11))
284
	  | ((as17 & 0x00400) >> (10 - 2))
285
	  | ((as17 & 0x003ff) << (1 + 2)));
286
}
287

  
288
static inline int
289
re_assemble_21 (int as21)
290
{
291
  return ((  (as21 & 0x100000) >> 20)
292
	  | ((as21 & 0x0ffe00) >> 8)
293
	  | ((as21 & 0x000180) << 7)
294
	  | ((as21 & 0x00007c) << 14)
295
	  | ((as21 & 0x000003) << 12));
296
}
297

  
298
static inline int
299
re_assemble_22 (int as22)
300
{
301
  return ((  (as22 & 0x200000) >> 21)
302
	  | ((as22 & 0x1f0000) << (21 - 16))
303
	  | ((as22 & 0x00f800) << (16 - 11))
304
	  | ((as22 & 0x000400) >> (10 - 2))
305
	  | ((as22 & 0x0003ff) << (1 + 2)));
306
}
307

  
308

  
309
/* Handle field selectors for PA instructions.
310
   The L and R (and LS, RS etc.) selectors are used in pairs to form a
311
   full 32 bit address.  eg.
312

  
313
   LDIL	L'start,%r1		; put left part into r1
314
   LDW	R'start(%r1),%r2	; add r1 and right part to form address
315

  
316
   This function returns sign extended values in all cases.
317
*/
318

  
319
static inline bfd_signed_vma
320
hppa_field_adjust (bfd_vma sym_val,
321
		   bfd_signed_vma addend,
322
		   enum hppa_reloc_field_selector_type_alt r_field)
323
{
324
  bfd_signed_vma value;
325

  
326
  value = sym_val + addend;
327
  switch (r_field)
328
    {
329
    case e_fsel:
330
      /* F: No change.  */
331
      break;
332

  
333
    case e_nsel:
334
      /* N: null selector.  I don't really understand what this is all
335
	 about, but HP's documentation says "this indicates that zero
336
	 bits are to be used for the displacement on the instruction.
337
	 This fixup is used to identify three-instruction sequences to
338
	 access data (for importing shared library data)."  */
339
      value = 0;
340
      break;
341

  
342
    case e_lsel:
343
    case e_nlsel:
344
      /* L:  Select top 21 bits.  */
345
      value = value >> 11;
346
      break;
347

  
348
    case e_rsel:
349
      /* R:  Select bottom 11 bits.  */
350
      value = value & 0x7ff;
351
      break;
352

  
353
    case e_lssel:
354
      /* LS:  Round to nearest multiple of 2048 then select top 21 bits.  */
355
      value = value + 0x400;
356
      value = value >> 11;
357
      break;
358

  
359
    case e_rssel:
360
      /* RS:  Select bottom 11 bits for LS.
361
	 We need to return a value such that 2048 * LS'x + RS'x == x.
362
	 ie. RS'x = x - ((x + 0x400) & -0x800)
363
	 this is just a sign extension from bit 21.  */
364
      value = ((value & 0x7ff) ^ 0x400) - 0x400;
365
      break;
366

  
367
    case e_ldsel:
368
      /* LD:  Round to next multiple of 2048 then select top 21 bits.
369
	 Yes, if we are already on a multiple of 2048, we go up to the
370
	 next one.  RD in this case will be -2048.  */
371
      value = value + 0x800;
372
      value = value >> 11;
373
      break;
374

  
375
    case e_rdsel:
376
      /* RD:  Set bits 0-20 to one.  */
377
      value = value | -0x800;
378
      break;
379

  
380
    case e_lrsel:
381
    case e_nlrsel:
382
      /* LR:  L with rounding of the addend to nearest 8k.  */
383
      value = sym_val + ((addend + 0x1000) & -0x2000);
384
      value = value >> 11;
385
      break;
386

  
387
    case e_rrsel:
388
      /* RR:  R with rounding of the addend to nearest 8k.
389
	 We need to return a value such that 2048 * LR'x + RR'x == x
390
	 ie. RR'x = s+a - (s + (((a + 0x1000) & -0x2000) & -0x800))
391
	 .	  = s+a - ((s & -0x800) + ((a + 0x1000) & -0x2000))
392
	 .	  = (s & 0x7ff) + a - ((a + 0x1000) & -0x2000)  */
393
      value = (sym_val & 0x7ff) + (((addend & 0x1fff) ^ 0x1000) - 0x1000);
394
      break;
395

  
396
    default:
397
      abort ();
398
    }
399
  return value;
400
}
401

  
402
/* PA-RISC OPCODES */
403
#define get_opcode(insn)	(((insn) >> 26) & 0x3f)
404

  
405
enum hppa_opcode_type
406
{
407
  /* None of the opcodes in the first group generate relocs, so we
408
     aren't too concerned about them.  */
409
  OP_SYSOP   = 0x00,
410
  OP_MEMMNG  = 0x01,
411
  OP_ALU     = 0x02,
412
  OP_NDXMEM  = 0x03,
413
  OP_SPOP    = 0x04,
414
  OP_DIAG    = 0x05,
415
  OP_FMPYADD = 0x06,
416
  OP_UNDEF07 = 0x07,
417
  OP_COPRW   = 0x09,
418
  OP_COPRDW  = 0x0b,
419
  OP_COPR    = 0x0c,
420
  OP_FLOAT   = 0x0e,
421
  OP_PRDSPEC = 0x0f,
422
  OP_UNDEF15 = 0x15,
423
  OP_UNDEF1d = 0x1d,
424
  OP_FMPYSUB = 0x26,
425
  OP_FPFUSED = 0x2e,
426
  OP_SHEXDP0 = 0x34,
427
  OP_SHEXDP1 = 0x35,
428
  OP_SHEXDP2 = 0x36,
429
  OP_UNDEF37 = 0x37,
430
  OP_SHEXDP3 = 0x3c,
431
  OP_SHEXDP4 = 0x3d,
432
  OP_MULTMED = 0x3e,
433
  OP_UNDEF3f = 0x3f,
434

  
435
  OP_LDIL    = 0x08,
436
  OP_ADDIL   = 0x0a,
437

  
438
  OP_LDO     = 0x0d,
439
  OP_LDB     = 0x10,
440
  OP_LDH     = 0x11,
441
  OP_LDW     = 0x12,
442
  OP_LDWM    = 0x13,
443
  OP_STB     = 0x18,
444
  OP_STH     = 0x19,
445
  OP_STW     = 0x1a,
446
  OP_STWM    = 0x1b,
447

  
448
  OP_LDD     = 0x14,
449
  OP_STD     = 0x1c,
450

  
451
  OP_FLDW    = 0x16,
452
  OP_LDWL    = 0x17,
453
  OP_FSTW    = 0x1e,
454
  OP_STWL    = 0x1f,
455

  
456
  OP_COMBT   = 0x20,
457
  OP_COMIBT  = 0x21,
458
  OP_COMBF   = 0x22,
459
  OP_COMIBF  = 0x23,
460
  OP_CMPBDT  = 0x27,
461
  OP_ADDBT   = 0x28,
462
  OP_ADDIBT  = 0x29,
463
  OP_ADDBF   = 0x2a,
464
  OP_ADDIBF  = 0x2b,
465
  OP_CMPBDF  = 0x2f,
466
  OP_BVB     = 0x30,
467
  OP_BB      = 0x31,
468
  OP_MOVB    = 0x32,
469
  OP_MOVIB   = 0x33,
470
  OP_CMPIBD  = 0x3b,
471

  
472
  OP_COMICLR = 0x24,
473
  OP_SUBI    = 0x25,
474
  OP_ADDIT   = 0x2c,
475
  OP_ADDI    = 0x2d,
476

  
477
  OP_BE      = 0x38,
478
  OP_BLE     = 0x39,
479
  OP_BL      = 0x3a
480
};
481

  
482

  
483
/* Insert VALUE into INSN using R_FORMAT to determine exactly what
484
   bits to change.  */
485

  
486
static inline int
487
hppa_rebuild_insn (int insn, int value, int r_format)
488
{
489
  switch (r_format)
490
    {
491
    case 11:
492
      return (insn & ~ 0x7ff) | low_sign_unext (value, 11);
493

  
494
    case 12:
495
      return (insn & ~ 0x1ffd) | re_assemble_12 (value);
496

  
497

  
498
    case 10:
499
      return (insn & ~ 0x3ff1) | re_assemble_14 (value & -8);
500

  
501
    case -11:
502
      return (insn & ~ 0x3ff9) | re_assemble_14 (value & -4);
503

  
504
    case 14:
505
      return (insn & ~ 0x3fff) | re_assemble_14 (value);
506

  
507

  
508
    case -10:
509
      return (insn & ~ 0xfff1) | re_assemble_16 (value & -8);
510

  
511
    case -16:
512
      return (insn & ~ 0xfff9) | re_assemble_16 (value & -4);
513

  
514
    case 16:
515
      return (insn & ~ 0xffff) | re_assemble_16 (value);
516

  
517

  
518
    case 17:
519
      return (insn & ~ 0x1f1ffd) | re_assemble_17 (value);
520

  
521
    case 21:
522
      return (insn & ~ 0x1fffff) | re_assemble_21 (value);
523

  
524
    case 22:
525
      return (insn & ~ 0x3ff1ffd) | re_assemble_22 (value);
526

  
527
    case 32:
528
      return value;
529

  
530
    default:
531
      abort ();
532
    }
533
  return insn;
534
}
535

  
536
#endif /* _LIBHPPA_H */
537
/* Table of opcodes for the PA-RISC.
538
   Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,
539
   2001, 2002, 2003, 2004, 2005
540
   Free Software Foundation, Inc.
541

  
542
   Contributed by the Center for Software Science at the
543
   University of Utah (pa-gdb-bugs@cs.utah.edu).
544

  
545
This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
546

  
547
GAS/GDB is free software; you can redistribute it and/or modify
548
it under the terms of the GNU General Public License as published by
549
the Free Software Foundation; either version 1, or (at your option)
550
any later version.
551

  
552
GAS/GDB is distributed in the hope that it will be useful,
553
but WITHOUT ANY WARRANTY; without even the implied warranty of
554
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
555
GNU General Public License for more details.
556

  
557
You should have received a copy of the GNU General Public License
558
along with GAS or GDB; see the file COPYING.  If not, write to
559
the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
560

  
561
#if !defined(__STDC__) && !defined(const)
562
#define const
563
#endif
564

  
565
/*
566
 * Structure of an opcode table entry.
567
 */
568

  
569
/* There are two kinds of delay slot nullification: normal which is
570
 * controled by the nullification bit, and conditional, which depends
571
 * on the direction of the branch and its success or failure.
572
 *
573
 * NONE is unfortunately #defined in the hiux system include files.
574
 * #undef it away.
575
 */
576
#undef NONE
577
struct pa_opcode
578
{
579
    const char *name;
580
    unsigned long int match;	/* Bits that must be set...  */
581
    unsigned long int mask;	/* ... in these bits. */
582
    char *args;
583
    enum pa_arch arch;
584
    char flags;
585
};
586

  
587
/* Enables strict matching.  Opcodes with match errors are skipped
588
   when this bit is set.  */
589
#define FLAG_STRICT 0x1
590

  
591
/*
592
   All hppa opcodes are 32 bits.
593

  
594
   The match component is a mask saying which bits must match a
595
   particular opcode in order for an instruction to be an instance
596
   of that opcode.
597

  
598
   The args component is a string containing one character for each operand of
599
   the instruction.  Characters used as a prefix allow any second character to
600
   be used without conflicting with the main operand characters.
601

  
602
   Bit positions in this description follow HP usage of lsb = 31,
603
   "at" is lsb of field.
604

  
605
   In the args field, the following characters must match exactly:
606

  
607
	'+,() '
608

  
609
   In the args field, the following characters are unused:
610

  
611
	'  "         -  /   34 6789:;    '
612
	'@  C         M             [\]  '
613
	'`    e g                     }  '
614

  
615
   Here are all the characters:
616

  
617
	' !"#$%&'()*+-,./0123456789:;<=>?'
618
	'@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'
619
	'`abcdefghijklmnopqrstuvwxyz{|}~ '
620

  
621
Kinds of operands:
622
   x    integer register field at 15.
623
   b    integer register field at 10.
624
   t    integer register field at 31.
625
   a	integer register field at 10 and 15 (for PERMH)
626
   5    5 bit immediate at 15.
627
   s    2 bit space specifier at 17.
628
   S    3 bit space specifier at 18.
629
   V    5 bit immediate value at 31
630
   i    11 bit immediate value at 31
631
   j    14 bit immediate value at 31
632
   k    21 bit immediate value at 31
633
   l    16 bit immediate value at 31 (wide mode only, unusual encoding).
634
   n	nullification for branch instructions
635
   N	nullification for spop and copr instructions
636
   w    12 bit branch displacement
637
   W    17 bit branch displacement (PC relative)
638
   X    22 bit branch displacement (PC relative)
639
   z    17 bit branch displacement (just a number, not an address)
640

  
641
Also these:
642

  
643
   .    2 bit shift amount at 25
644
   *    4 bit shift amount at 25
645
   p    5 bit shift count at 26 (to support the SHD instruction) encoded as
646
        31-p
647
   ~    6 bit shift count at 20,22:26 encoded as 63-~.
648
   P    5 bit bit position at 26
649
   q    6 bit bit position at 20,22:26
650
   T    5 bit field length at 31 (encoded as 32-T)
651
   %	6 bit field length at 23,27:31 (variable extract/deposit)
652
   |	6 bit field length at 19,27:31 (fixed extract/deposit)
653
   A    13 bit immediate at 18 (to support the BREAK instruction)
654
   ^	like b, but describes a control register
655
   !    sar (cr11) register
656
   D    26 bit immediate at 31 (to support the DIAG instruction)
657
   $    9 bit immediate at 28 (to support POPBTS)
658

  
659
   v    3 bit Special Function Unit identifier at 25
660
   O    20 bit Special Function Unit operation split between 15 bits at 20
661
        and 5 bits at 31
662
   o    15 bit Special Function Unit operation at 20
663
   2    22 bit Special Function Unit operation split between 17 bits at 20
664
        and 5 bits at 31
665
   1    15 bit Special Function Unit operation split between 10 bits at 20
666
        and 5 bits at 31
667
   0    10 bit Special Function Unit operation split between 5 bits at 20
668
        and 5 bits at 31
669
   u    3 bit coprocessor unit identifier at 25
670
   F    Source Floating Point Operand Format Completer encoded 2 bits at 20
671
   I    Source Floating Point Operand Format Completer encoded 1 bits at 20
672
	(for 0xe format FP instructions)
673
   G    Destination Floating Point Operand Format Completer encoded 2 bits at 18
674
   H    Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
675
        (very similar to 'F')
676

  
677
   r	5 bit immediate value at 31 (for the break instruction)
678
	(very similar to V above, except the value is unsigned instead of
679
	low_sign_ext)
680
   R	5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
681
	(same as r above, except the value is in a different location)
682
   U	10 bit immediate value at 15 (for SSM, RSM on pa2.0)
683
   Q	5 bit immediate value at 10 (a bit position specified in
684
	the bb instruction. It's the same as r above, except the
685
        value is in a different location)
686
   B	5 bit immediate value at 10 (a bit position specified in
687
	the bb instruction. Similar to Q, but 64 bit handling is
688
	different.
689
   Z    %r1 -- implicit target of addil instruction.
690
   L    ,%r2 completer for new syntax branch
691
   {    Source format completer for fcnv
692
   _    Destination format completer for fcnv
693
   h    cbit for fcmp
694
   =    gfx tests for ftest
695
   d    14 bit offset for single precision FP long load/store.
696
   #    14 bit offset for double precision FP load long/store.
697
   J    Yet another 14 bit offset for load/store with ma,mb completers.
698
   K    Yet another 14 bit offset for load/store with ma,mb completers.
699
   y    16 bit offset for word aligned load/store (PA2.0 wide).
700
   &    16 bit offset for dword aligned load/store (PA2.0 wide).
701
   <    16 bit offset for load/store with ma,mb completers (PA2.0 wide).
702
   >    16 bit offset for load/store with ma,mb completers (PA2.0 wide).
703
   Y    %sr0,%r31 -- implicit target of be,l instruction.
704
   @	implicit immediate value of 0
705

  
706
Completer operands all have 'c' as the prefix:
707

  
708
   cx   indexed load and store completer.
709
   cX   indexed load and store completer.  Like cx, but emits a space
710
	after in disassembler.
711
   cm   short load and store completer.
712
   cM   short load and store completer.  Like cm, but emits a space
713
        after in disassembler.
714
   cq   long load and store completer (like cm, but inserted into a
715
	different location in the target instruction).
716
   cs   store bytes short completer.
717
   cA   store bytes short completer.  Like cs, but emits a space
718
        after in disassembler.
719
   ce   long load/store completer for LDW/STW with a different encoding
720
	than the others
721
   cc   load cache control hint
722
   cd   load and clear cache control hint
723
   cC   store cache control hint
724
   co	ordered access
725

  
726
   cp	branch link and push completer
727
   cP	branch pop completer
728
   cl	branch link completer
729
   cg	branch gate completer
730

  
731
   cw	read/write completer for PROBE
732
   cW	wide completer for MFCTL
733
   cL	local processor completer for cache control
734
   cZ   System Control Completer (to support LPA, LHA, etc.)
735

  
736
   ci	correction completer for DCOR
737
   ca	add completer
738
   cy	32 bit add carry completer
739
   cY	64 bit add carry completer
740
   cv	signed overflow trap completer
741
   ct	trap on condition completer for ADDI, SUB
742
   cT	trap on condition completer for UADDCM
743
   cb	32 bit borrow completer for SUB
744
   cB	64 bit borrow completer for SUB
745

  
746
   ch	left/right half completer
747
   cH	signed/unsigned saturation completer
748
   cS	signed/unsigned completer at 21
749
   cz	zero/sign extension completer.
750
   c*	permutation completer
751

  
752
Condition operands all have '?' as the prefix:
753

  
754
   ?f   Floating point compare conditions (encoded as 5 bits at 31)
755

  
756
   ?a	add conditions
757
   ?A	64 bit add conditions
758
   ?@   add branch conditions followed by nullify
759
   ?d	non-negated add branch conditions
760
   ?D	negated add branch conditions
761
   ?w	wide mode non-negated add branch conditions
762
   ?W	wide mode negated add branch conditions
763

  
764
   ?s   compare/subtract conditions
765
   ?S	64 bit compare/subtract conditions
766
   ?t   non-negated compare and branch conditions
767
   ?n   32 bit compare and branch conditions followed by nullify
768
   ?N   64 bit compare and branch conditions followed by nullify
769
   ?Q	64 bit compare and branch conditions for CMPIB instruction
770

  
771
   ?l   logical conditions
772
   ?L	64 bit logical conditions
773

  
774
   ?b   branch on bit conditions
775
   ?B	64 bit branch on bit conditions
776

  
777
   ?x   shift/extract/deposit conditions
778
   ?X	64 bit shift/extract/deposit conditions
779
   ?y   shift/extract/deposit conditions followed by nullify for conditional
780
        branches
781

  
782
   ?u   unit conditions
783
   ?U   64 bit unit conditions
784

  
785
Floating point registers all have 'f' as a prefix:
786

  
787
   ft	target register at 31
788
   fT	target register with L/R halves at 31
789
   fa	operand 1 register at 10
790
   fA   operand 1 register with L/R halves at 10
791
   fX   Same as fA, except prints a space before register during disasm
792
   fb	operand 2 register at 15
793
   fB   operand 2 register with L/R halves at 15
794
   fC   operand 3 register with L/R halves at 16:18,21:23
795
   fe   Like fT, but encoding is different.
796
   fE   Same as fe, except prints a space before register during disasm.
797
   fx	target register at 15 (only for PA 2.0 long format FLDD/FSTD).
798

  
799
Float registers for fmpyadd and fmpysub:
800

  
801
   fi	mult operand 1 register at 10
802
   fj	mult operand 2 register at 15
803
   fk	mult target register at 20
804
   fl	add/sub operand register at 25
805
   fm	add/sub target register at 31
806

  
807
*/
808

  
809

  
810
#if 0
811
/* List of characters not to put a space after.  Note that
812
   "," is included, as the "spopN" operations use literal
813
   commas in their completer sections.  */
814
static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";
815
#endif
816

  
817
/* The order of the opcodes in this table is significant:
818

  
819
   * The assembler requires that all instances of the same mnemonic be
820
     consecutive.  If they aren't, the assembler will bomb at runtime.
821

  
822
   * Immediate fields use pa_get_absolute_expression to parse the
823
     string.  It will generate a "bad expression" error if passed
824
     a register name.  Thus, register index variants of an opcode
825
     need to precede immediate variants.
826

  
827
   * The disassembler does not care about the order of the opcodes
828
     except in cases where implicit addressing is used.
829

  
830
   Here are the rules for ordering the opcodes of a mnemonic:
831

  
832
   1) Opcodes with FLAG_STRICT should precede opcodes without
833
      FLAG_STRICT.
834

  
835
   2) Opcodes with FLAG_STRICT should be ordered as follows:
836
      register index opcodes, short immediate opcodes, and finally
837
      long immediate opcodes.  When both pa10 and pa11 variants
838
      of the same opcode are available, the pa10 opcode should
839
      come first for correct architectural promotion.
840

  
841
   3) When implicit addressing is available for an opcode, the
842
      implicit opcode should precede the explicit opcode.
843

  
844
   4) Opcodes without FLAG_STRICT should be ordered as follows:
845
      register index opcodes, long immediate opcodes, and finally
846
      short immediate opcodes.  */
847

  
848
static const struct pa_opcode pa_opcodes[] =
849
{
850

  
851
/* Pseudo-instructions.  */
852

  
853
{ "ldi",	0x34000000, 0xffe00000, "l,x", pa20w, 0},/* ldo val(r0),r */
854
{ "ldi",	0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */
855

  
856
{ "cmpib",	0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT},
857
{ "cmpib", 	0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT},
858
{ "comib", 	0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/
859
/* This entry is for the disassembler only.  It will never be used by
860
   assembler.  */
861
{ "comib", 	0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/
862
{ "cmpb",	0x9c000000, 0xdc000000, "?Nnx,b,w", pa20, FLAG_STRICT},
863
{ "cmpb",	0x80000000, 0xf4000000, "?nnx,b,w", pa10, FLAG_STRICT},
864
{ "comb",	0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */
865
/* This entry is for the disassembler only.  It will never be used by
866
   assembler.  */
867
{ "comb",	0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */
868
{ "addb",	0xa0000000, 0xf4000000, "?Wnx,b,w", pa20w, FLAG_STRICT},
869
{ "addb",	0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */
870
/* This entry is for the disassembler only.  It will never be used by
871
   assembler.  */
872
{ "addb",	0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0},
873
{ "addib",	0xa4000000, 0xf4000000, "?Wn5,b,w", pa20w, FLAG_STRICT},
874
{ "addib",	0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/
875
/* This entry is for the disassembler only.  It will never be used by
876
   assembler.  */
877
{ "addib",	0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/
878
{ "nop",	0x08000240, 0xffffffff, "", pa10, 0},      /* or 0,0,0 */
879
{ "copy",	0x08000240, 0xffe0ffe0, "x,t", pa10, 0},   /* or r,0,t */
880
{ "mtsar",	0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */
881

  
882
/* Loads and Stores for integer registers.  */
883

  
884
{ "ldd",	0x0c0000c0, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT},
885
{ "ldd",	0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT},
886
{ "ldd",	0x0c0010e0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
887
{ "ldd",	0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
888
{ "ldd",	0x0c0010c0, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT},
889
{ "ldd",	0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT},
890
{ "ldd",	0x50000000, 0xfc000002, "cq&(b),x", pa20w, FLAG_STRICT},
891
{ "ldd",	0x50000000, 0xfc00c002, "cq#(b),x", pa20, FLAG_STRICT},
892
{ "ldd",	0x50000000, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT},
893
{ "ldw",	0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
894
{ "ldw",	0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
895
{ "ldw",	0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
896
{ "ldw",	0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
897
{ "ldw",	0x0c0010a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
898
{ "ldw",	0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
899
{ "ldw",	0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
900
{ "ldw",	0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
901
{ "ldw",	0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
902
{ "ldw",	0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
903
{ "ldw",	0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT},
904
{ "ldw",	0x5c000004, 0xfc000006, "ce>(b),x", pa20w, FLAG_STRICT},
905
{ "ldw",	0x48000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
906
{ "ldw",	0x5c000004, 0xfc00c006, "ceK(b),x", pa20, FLAG_STRICT},
907
{ "ldw",	0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT},
908
{ "ldw",	0x4c000000, 0xfc00c000, "ceJ(b),x", pa10, FLAG_STRICT},
909
{ "ldw",	0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT},
910
{ "ldw",	0x48000000, 0xfc00c000, "j(b),x", pa10, 0},
911
{ "ldw",	0x48000000, 0xfc000000, "j(s,b),x", pa10, 0},
912
{ "ldh",	0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
913
{ "ldh",	0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
914
{ "ldh",	0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
915
{ "ldh",	0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
916
{ "ldh",	0x0c001060, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
917
{ "ldh",	0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
918
{ "ldh",	0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
919
{ "ldh",	0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
920
{ "ldh",	0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
921
{ "ldh",	0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
922
{ "ldh",	0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
923
{ "ldh",	0x44000000, 0xfc00c000, "j(b),x", pa10, 0},
924
{ "ldh",	0x44000000, 0xfc000000, "j(s,b),x", pa10, 0},
925
{ "ldb",	0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
926
{ "ldb",	0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
927
{ "ldb",	0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
928
{ "ldb",	0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
929
{ "ldb",	0x0c001020, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
930
{ "ldb",	0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
931
{ "ldb",	0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
932
{ "ldb",	0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
933
{ "ldb",	0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
934
{ "ldb",	0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
935
{ "ldb",	0x40000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
936
{ "ldb",	0x40000000, 0xfc00c000, "j(b),x", pa10, 0},
937
{ "ldb",	0x40000000, 0xfc000000, "j(s,b),x", pa10, 0},
938
{ "std",	0x0c0012e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
939
{ "std",	0x0c0012e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
940
{ "std",	0x0c0012c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT},
941
{ "std",	0x0c0012c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT},
942
{ "std",	0x70000000, 0xfc000002, "cqx,&(b)", pa20w, FLAG_STRICT},
943
{ "std",	0x70000000, 0xfc00c002, "cqx,#(b)", pa20, FLAG_STRICT},
944
{ "std",	0x70000000, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT},
945
{ "stw",	0x0c0012a0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
946
{ "stw",	0x0c0012a0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
947
{ "stw",	0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
948
{ "stw",	0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
949
{ "stw",	0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
950
{ "stw",	0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
951
{ "stw",	0x6c000000, 0xfc000000, "cex,<(b)", pa20w, FLAG_STRICT},
952
{ "stw",	0x7c000004, 0xfc000006, "cex,>(b)", pa20w, FLAG_STRICT},
953
{ "stw",	0x68000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
954
{ "stw",	0x7c000004, 0xfc00c006, "cex,K(b)", pa20, FLAG_STRICT},
955
{ "stw",	0x7c000004, 0xfc000006, "cex,K(s,b)", pa20, FLAG_STRICT},
956
{ "stw",	0x6c000000, 0xfc00c000, "cex,J(b)", pa10, FLAG_STRICT},
957
{ "stw",	0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT},
958
{ "stw",	0x68000000, 0xfc00c000, "x,j(b)", pa10, 0},
959
{ "stw",	0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0},
960
{ "sth",	0x0c001260, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
961
{ "sth",	0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
962
{ "sth",	0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
963
{ "sth",	0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
964
{ "sth",	0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
965
{ "sth",	0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
966
{ "sth",	0x64000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
967
{ "sth",	0x64000000, 0xfc00c000, "x,j(b)", pa10, 0},
968
{ "sth",	0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0},
969
{ "stb",	0x0c001220, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
970
{ "stb",	0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
971
{ "stb",	0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
972
{ "stb",	0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
973
{ "stb",	0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
974
{ "stb",	0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
975
{ "stb",	0x60000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
976
{ "stb",	0x60000000, 0xfc00c000, "x,j(b)", pa10, 0},
977
{ "stb",	0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0},
978
{ "ldwm",	0x4c000000, 0xfc00c000, "j(b),x", pa10, 0},
979
{ "ldwm",	0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0},
980
{ "stwm",	0x6c000000, 0xfc00c000, "x,j(b)", pa10, 0},
981
{ "stwm",	0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0},
982
{ "ldwx",	0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
983
{ "ldwx",	0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
984
{ "ldwx",	0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
985
{ "ldwx",	0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
986
{ "ldwx",	0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, 0},
987
{ "ldwx",	0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
988
{ "ldhx",	0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
989
{ "ldhx",	0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
990
{ "ldhx",	0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
991
{ "ldhx",	0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
992
{ "ldhx",	0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, 0},
993
{ "ldhx",	0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
994
{ "ldbx",	0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
995
{ "ldbx",	0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
996
{ "ldbx",	0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
997
{ "ldbx",	0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
998
{ "ldbx",	0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, 0},
999
{ "ldbx",	0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
1000
{ "ldwa",	0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
1001
{ "ldwa",	0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
1002
{ "ldwa",	0x0c0011a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
1003
{ "ldwa",	0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
1004
{ "ldwa",	0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
1005
{ "ldcw",	0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
1006
{ "ldcw",	0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
1007
{ "ldcw",	0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT},
1008
{ "ldcw",	0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT},
1009
{ "ldcw",	0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
1010
{ "ldcw",	0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
1011
{ "ldcw",	0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT},
1012
{ "ldcw",	0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT},
1013
{ "stwa",	0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
1014
{ "stwa",	0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
1015
{ "stwa",	0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
1016
{ "stby",	0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, FLAG_STRICT},
1017
{ "stby",	0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, FLAG_STRICT},
1018
{ "stby",	0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT},
1019
{ "stby",	0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT},
1020
{ "ldda",	0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT},
1021
{ "ldda",	0x0c001120, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
1022
{ "ldda",	0x0c001100, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT},
1023
{ "ldcd",	0x0c000140, 0xfc00d3c0, "cxcdx(b),t", pa20, FLAG_STRICT},
1024
{ "ldcd",	0x0c000140, 0xfc0013c0, "cxcdx(s,b),t", pa20, FLAG_STRICT},
1025
{ "ldcd",	0x0c001140, 0xfc00d3c0, "cmcd5(b),t", pa20, FLAG_STRICT},
1026
{ "ldcd",	0x0c001140, 0xfc0013c0, "cmcd5(s,b),t", pa20, FLAG_STRICT},
1027
{ "stda",	0x0c0013e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
1028
{ "stda",	0x0c0013c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT},
1029
{ "ldwax",	0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
1030
{ "ldwax",	0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
1031
{ "ldwax",	0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0},
1032
{ "ldcwx",	0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
1033
{ "ldcwx",	0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
1034
{ "ldcwx",	0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT},
1035
{ "ldcwx",	0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT},
1036
{ "ldcwx",	0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, 0},
1037
{ "ldcwx",	0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
1038
{ "ldws",	0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
1039
{ "ldws",	0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
1040
{ "ldws",	0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
1041
{ "ldws",	0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
1042
{ "ldws",	0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, 0},
1043
{ "ldws",	0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
1044
{ "ldhs",	0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
1045
{ "ldhs",	0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
1046
{ "ldhs",	0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
1047
{ "ldhs",	0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
1048
{ "ldhs",	0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, 0},
1049
{ "ldhs",	0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
1050
{ "ldbs",	0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
1051
{ "ldbs",	0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
1052
{ "ldbs",	0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
1053
{ "ldbs",	0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
1054
{ "ldbs",	0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, 0},
1055
{ "ldbs",	0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
1056
{ "ldwas",	0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
1057
{ "ldwas",	0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
1058
{ "ldwas",	0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, 0},
1059
{ "ldcws",	0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
1060
{ "ldcws",	0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
1061
{ "ldcws",	0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT},
1062
{ "ldcws",	0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT},
1063
{ "ldcws",	0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, 0},
1064
{ "ldcws",	0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
1065
{ "stws",	0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
1066
{ "stws",	0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
1067
{ "stws",	0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
1068
{ "stws",	0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
1069
{ "stws",	0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
1070
{ "stws",	0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
1071
{ "sths",	0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
1072
{ "sths",	0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
1073
{ "sths",	0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
1074
{ "sths",	0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
1075
{ "sths",	0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
1076
{ "sths",	0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
1077
{ "stbs",	0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
1078
{ "stbs",	0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
1079
{ "stbs",	0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
1080
{ "stbs",	0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
1081
{ "stbs",	0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
1082
{ "stbs",	0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
1083
{ "stwas",	0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
1084
{ "stwas",	0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
1085
{ "stwas",	0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
1086
{ "stdby",	0x0c001340, 0xfc00d3c0, "cscCx,V(b)", pa20, FLAG_STRICT},
1087
{ "stdby",	0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT},
1088
{ "stbys",	0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, FLAG_STRICT},
1089
{ "stbys",	0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, FLAG_STRICT},
1090
{ "stbys",	0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT},
1091
{ "stbys",	0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT},
1092
{ "stbys",	0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, 0},
1093
{ "stbys",	0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, 0},
1094

  
1095
/* Immediate instructions.  */
1096
{ "ldo",	0x34000000, 0xfc000000, "l(b),x", pa20w, 0},
1097
{ "ldo",	0x34000000, 0xfc00c000, "j(b),x", pa10, 0},
1098
{ "ldil",	0x20000000, 0xfc000000, "k,b", pa10, 0},
1099
{ "addil",	0x28000000, 0xfc000000, "k,b,Z", pa10, 0},
1100
{ "addil",	0x28000000, 0xfc000000, "k,b", pa10, 0},
1101

  
1102
/* Branching instructions.  */
1103
{ "b",		0xe8008000, 0xfc00e000, "cpnXL", pa20, FLAG_STRICT},
1104
{ "b",		0xe800a000, 0xfc00e000, "clnXL", pa20, FLAG_STRICT},
1105
{ "b",		0xe8000000, 0xfc00e000, "clnW,b", pa10, FLAG_STRICT},
1106
{ "b",		0xe8002000, 0xfc00e000, "cgnW,b", pa10, FLAG_STRICT},
1107
{ "b",		0xe8000000, 0xffe0e000, "nW", pa10, 0},  /* b,l foo,r0 */
1108
{ "bl",		0xe8000000, 0xfc00e000, "nW,b", pa10, 0},
1109
{ "gate",	0xe8002000, 0xfc00e000, "nW,b", pa10, 0},
1110
{ "blr",	0xe8004000, 0xfc00e001, "nx,b", pa10, 0},
1111
{ "bv",		0xe800c000, 0xfc00fffd, "nx(b)", pa10, 0},
1112
{ "bv",		0xe800c000, 0xfc00fffd, "n(b)", pa10, 0},
1113
{ "bve",	0xe800f001, 0xfc1ffffd, "cpn(b)L", pa20, FLAG_STRICT},
1114
{ "bve",	0xe800f000, 0xfc1ffffd, "cln(b)L", pa20, FLAG_STRICT},
1115
{ "bve",	0xe800d001, 0xfc1ffffd, "cPn(b)", pa20, FLAG_STRICT},
1116
{ "bve",	0xe800d000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT},
1117
{ "be",		0xe4000000, 0xfc000000, "clnz(S,b),Y", pa10, FLAG_STRICT},
1118
{ "be",		0xe4000000, 0xfc000000, "clnz(b),Y", pa10, FLAG_STRICT},
1119
{ "be",		0xe0000000, 0xfc000000, "nz(S,b)", pa10, 0},
1120
{ "be",		0xe0000000, 0xfc000000, "nz(b)", pa10, 0},
... This diff was truncated because it exceeds the maximum size that can be displayed.

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