Archipelago » qemu

/* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c.

   Copyright 1989, 1990, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2003,

   2005 Free Software Foundation, Inc.

   Contributed by the Center for Software Science at the

   University of Utah (pa-gdb-bugs@cs.utah.edu).

   This program is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 2 of the License, or

   (at your option) any later version.

   This program is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License

   along with this program; if not, write to the Free Software

   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,

   MA 02110-1301, USA.  */

#include "dis-asm.h"

/* HP PA-RISC SOM object file format:  definitions internal to BFD.

   Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,

   2003 Free Software Foundation, Inc.

   Contributed by the Center for Software Science at the

   University of Utah (pa-gdb-bugs@cs.utah.edu).

   This file is part of BFD, the Binary File Descriptor library.

   This program is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 2 of the License, or

   (at your option) any later version.

   This program is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License

   along with this program; if not, write to the Free Software

   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

#ifndef _LIBHPPA_H

#define _LIBHPPA_H

#define BYTES_IN_WORD 4

#define PA_PAGESIZE 0x1000

/* The PA instruction set variants.  */

enum pa_arch {pa10 = 10, pa11 = 11, pa20 = 20, pa20w = 25};

/* HP PA-RISC relocation types */

enum hppa_reloc_field_selector_type

  {

    R_HPPA_FSEL = 0x0,

    R_HPPA_LSSEL = 0x1,

    R_HPPA_RSSEL = 0x2,

    R_HPPA_LSEL = 0x3,

    R_HPPA_RSEL = 0x4,

    R_HPPA_LDSEL = 0x5,

    R_HPPA_RDSEL = 0x6,

    R_HPPA_LRSEL = 0x7,

    R_HPPA_RRSEL = 0x8,

    R_HPPA_NSEL  = 0x9,

    R_HPPA_NLSEL  = 0xa,

    R_HPPA_NLRSEL  = 0xb,

    R_HPPA_PSEL = 0xc,

    R_HPPA_LPSEL = 0xd,

    R_HPPA_RPSEL = 0xe,

    R_HPPA_TSEL = 0xf,

    R_HPPA_LTSEL = 0x10,

    R_HPPA_RTSEL = 0x11,

    R_HPPA_LTPSEL = 0x12,

    R_HPPA_RTPSEL = 0x13

  };

/* /usr/include/reloc.h defines these to constants.  We want to use

   them in enums, so #undef them before we start using them.  We might

   be able to fix this another way by simply managing not to include

   /usr/include/reloc.h, but currently GDB picks up these defines

   somewhere.  */

#undef e_fsel

#undef e_lssel

#undef e_rssel

#undef e_lsel

#undef e_rsel

#undef e_ldsel

#undef e_rdsel

#undef e_lrsel

#undef e_rrsel

#undef e_nsel

#undef e_nlsel

#undef e_nlrsel

#undef e_psel

#undef e_lpsel

#undef e_rpsel

#undef e_tsel

#undef e_ltsel

#undef e_rtsel

#undef e_one

#undef e_two

#undef e_pcrel

#undef e_con

#undef e_plabel

#undef e_abs

/* for compatibility */

enum hppa_reloc_field_selector_type_alt

  {

    e_fsel = R_HPPA_FSEL,

    e_lssel = R_HPPA_LSSEL,

    e_rssel = R_HPPA_RSSEL,

    e_lsel = R_HPPA_LSEL,

    e_rsel = R_HPPA_RSEL,

    e_ldsel = R_HPPA_LDSEL,

    e_rdsel = R_HPPA_RDSEL,

    e_lrsel = R_HPPA_LRSEL,

    e_rrsel = R_HPPA_RRSEL,

    e_nsel = R_HPPA_NSEL,

    e_nlsel = R_HPPA_NLSEL,

    e_nlrsel = R_HPPA_NLRSEL,

    e_psel = R_HPPA_PSEL,

    e_lpsel = R_HPPA_LPSEL,

    e_rpsel = R_HPPA_RPSEL,

    e_tsel = R_HPPA_TSEL,

    e_ltsel = R_HPPA_LTSEL,

    e_rtsel = R_HPPA_RTSEL,

    e_ltpsel = R_HPPA_LTPSEL,

    e_rtpsel = R_HPPA_RTPSEL

  };

enum hppa_reloc_expr_type

  {

    R_HPPA_E_ONE = 0,

    R_HPPA_E_TWO = 1,

    R_HPPA_E_PCREL = 2,

    R_HPPA_E_CON = 3,

    R_HPPA_E_PLABEL = 7,

    R_HPPA_E_ABS = 18

  };

/* for compatibility */

enum hppa_reloc_expr_type_alt

  {

    e_one = R_HPPA_E_ONE,

    e_two = R_HPPA_E_TWO,

    e_pcrel = R_HPPA_E_PCREL,

    e_con = R_HPPA_E_CON,

    e_plabel = R_HPPA_E_PLABEL,

    e_abs = R_HPPA_E_ABS

  };

/* Relocations for function calls must be accompanied by parameter

   relocation bits.  These bits describe exactly where the caller has

   placed the function's arguments and where it expects to find a return

   value.

   Both ELF and SOM encode this information within the addend field

   of the call relocation.  (Note this could break very badly if one

   was to make a call like bl foo + 0x12345678).

   The high order 10 bits contain parameter relocation information,

   the low order 22 bits contain the constant offset.  */

#define HPPA_R_ARG_RELOC(a)        \

  (((a) >> 22) & 0x3ff)

#define HPPA_R_CONSTANT(a)        \

  ((((bfd_signed_vma)(a)) << (BFD_ARCH_SIZE-22)) >> (BFD_ARCH_SIZE-22))

#define HPPA_R_ADDEND(r, c)        \

  (((r) << 22) + ((c) & 0x3fffff))

/* Some functions to manipulate PA instructions.  */

/* Declare the functions with the unused attribute to avoid warnings.  */

static inline int sign_extend (int, int) ATTRIBUTE_UNUSED;

static inline int low_sign_extend (int, int) ATTRIBUTE_UNUSED;

static inline int sign_unext (int, int) ATTRIBUTE_UNUSED;

static inline int low_sign_unext (int, int) ATTRIBUTE_UNUSED;

static inline int re_assemble_3 (int) ATTRIBUTE_UNUSED;

static inline int re_assemble_12 (int) ATTRIBUTE_UNUSED;

static inline int re_assemble_14 (int) ATTRIBUTE_UNUSED;

static inline int re_assemble_16 (int) ATTRIBUTE_UNUSED;

static inline int re_assemble_17 (int) ATTRIBUTE_UNUSED;

static inline int re_assemble_21 (int) ATTRIBUTE_UNUSED;

static inline int re_assemble_22 (int) ATTRIBUTE_UNUSED;

static inline bfd_signed_vma hppa_field_adjust

  (bfd_vma, bfd_signed_vma, enum hppa_reloc_field_selector_type_alt)

  ATTRIBUTE_UNUSED;

static inline int hppa_rebuild_insn (int, int, int) ATTRIBUTE_UNUSED;

/* The *sign_extend functions are used to assemble various bitfields

   taken from an instruction and return the resulting immediate

   value.  */

static inline int

sign_extend (int x, int len)

{

  int signbit = (1 << (len - 1));

  int mask = (signbit << 1) - 1;

  return ((x & mask) ^ signbit) - signbit;

}

static inline int

low_sign_extend (int x, int len)

{

  return (x >> 1) - ((x & 1) << (len - 1));

}

/* The re_assemble_* functions prepare an immediate value for

   insertion into an opcode. pa-risc uses all sorts of weird bitfields

   in the instruction to hold the value.  */

static inline int

sign_unext (int x, int len)

{

  int len_ones;

  len_ones = (1 << len) - 1;

  return x & len_ones;

}

static inline int

low_sign_unext (int x, int len)

{

  int temp;

  int sign;

  sign = (x >> (len-1)) & 1;

  temp = sign_unext (x, len-1);

  return (temp << 1) | sign;

}

static inline int

re_assemble_3 (int as3)

{

  return ((  (as3 & 4) << (13-2))

          | ((as3 & 3) << (13+1)));

}

static inline int

re_assemble_12 (int as12)

{

  return ((  (as12 & 0x800) >> 11)

          | ((as12 & 0x400) >> (10 - 2))

          | ((as12 & 0x3ff) << (1 + 2)));

}

static inline int

re_assemble_14 (int as14)

{

  return ((  (as14 & 0x1fff) << 1)

          | ((as14 & 0x2000) >> 13));

}

static inline int

re_assemble_16 (int as16)

{

  int s, t;

  /* Unusual 16-bit encoding, for wide mode only.  */

  t = (as16 << 1) & 0xffff;

  s = (as16 & 0x8000);

  return (t ^ s ^ (s >> 1)) | (s >> 15);

}

static inline int

re_assemble_17 (int as17)

{

  return ((  (as17 & 0x10000) >> 16)

          | ((as17 & 0x0f800) << (16 - 11))

          | ((as17 & 0x00400) >> (10 - 2))

          | ((as17 & 0x003ff) << (1 + 2)));

}

static inline int

re_assemble_21 (int as21)

{

  return ((  (as21 & 0x100000) >> 20)

          | ((as21 & 0x0ffe00) >> 8)

          | ((as21 & 0x000180) << 7)

          | ((as21 & 0x00007c) << 14)

          | ((as21 & 0x000003) << 12));

}

static inline int

re_assemble_22 (int as22)

{

  return ((  (as22 & 0x200000) >> 21)

          | ((as22 & 0x1f0000) << (21 - 16))

          | ((as22 & 0x00f800) << (16 - 11))

          | ((as22 & 0x000400) >> (10 - 2))

          | ((as22 & 0x0003ff) << (1 + 2)));

}

/* Handle field selectors for PA instructions.

   The L and R (and LS, RS etc.) selectors are used in pairs to form a

   full 32 bit address.  eg.

   LDIL        L'start,%r1                ; put left part into r1

   LDW        R'start(%r1),%r2        ; add r1 and right part to form address

   This function returns sign extended values in all cases.

*/

static inline bfd_signed_vma

hppa_field_adjust (bfd_vma sym_val,

                   bfd_signed_vma addend,

                   enum hppa_reloc_field_selector_type_alt r_field)

{

  bfd_signed_vma value;

  value = sym_val + addend;

  switch (r_field)

    {

    case e_fsel:

      /* F: No change.  */

      break;

    case e_nsel:

      /* N: null selector.  I don't really understand what this is all

         about, but HP's documentation says "this indicates that zero

         bits are to be used for the displacement on the instruction.

         This fixup is used to identify three-instruction sequences to

         access data (for importing shared library data)."  */

      value = 0;

      break;

    case e_lsel:

    case e_nlsel:

      /* L:  Select top 21 bits.  */

      value = value >> 11;

      break;

    case e_rsel:

      /* R:  Select bottom 11 bits.  */

      value = value & 0x7ff;

      break;

    case e_lssel:

      /* LS:  Round to nearest multiple of 2048 then select top 21 bits.  */

      value = value + 0x400;

      value = value >> 11;

      break;

    case e_rssel:

      /* RS:  Select bottom 11 bits for LS.

         We need to return a value such that 2048 * LS'x + RS'x == x.

         ie. RS'x = x - ((x + 0x400) & -0x800)

         this is just a sign extension from bit 21.  */

      value = ((value & 0x7ff) ^ 0x400) - 0x400;

      break;

    case e_ldsel:

      /* LD:  Round to next multiple of 2048 then select top 21 bits.

         Yes, if we are already on a multiple of 2048, we go up to the

         next one.  RD in this case will be -2048.  */

      value = value + 0x800;

      value = value >> 11;

      break;

    case e_rdsel:

      /* RD:  Set bits 0-20 to one.  */

      value = value | -0x800;

      break;

    case e_lrsel:

    case e_nlrsel:

      /* LR:  L with rounding of the addend to nearest 8k.  */

      value = sym_val + ((addend + 0x1000) & -0x2000);

      value = value >> 11;

      break;

    case e_rrsel:

      /* RR:  R with rounding of the addend to nearest 8k.

         We need to return a value such that 2048 * LR'x + RR'x == x

         ie. RR'x = s+a - (s + (((a + 0x1000) & -0x2000) & -0x800))

         .          = s+a - ((s & -0x800) + ((a + 0x1000) & -0x2000))

         .          = (s & 0x7ff) + a - ((a + 0x1000) & -0x2000)  */

      value = (sym_val & 0x7ff) + (((addend & 0x1fff) ^ 0x1000) - 0x1000);

      break;

    default:

      abort ();

    }

  return value;

}

/* PA-RISC OPCODES */

#define get_opcode(insn)        (((insn) >> 26) & 0x3f)

enum hppa_opcode_type

{

  /* None of the opcodes in the first group generate relocs, so we

     aren't too concerned about them.  */

  OP_SYSOP   = 0x00,

  OP_MEMMNG  = 0x01,

  OP_ALU     = 0x02,

  OP_NDXMEM  = 0x03,

  OP_SPOP    = 0x04,

  OP_DIAG    = 0x05,

  OP_FMPYADD = 0x06,

  OP_UNDEF07 = 0x07,

  OP_COPRW   = 0x09,

  OP_COPRDW  = 0x0b,

  OP_COPR    = 0x0c,

  OP_FLOAT   = 0x0e,

  OP_PRDSPEC = 0x0f,

  OP_UNDEF15 = 0x15,

  OP_UNDEF1d = 0x1d,

  OP_FMPYSUB = 0x26,

  OP_FPFUSED = 0x2e,

  OP_SHEXDP0 = 0x34,

  OP_SHEXDP1 = 0x35,

  OP_SHEXDP2 = 0x36,

  OP_UNDEF37 = 0x37,

  OP_SHEXDP3 = 0x3c,

  OP_SHEXDP4 = 0x3d,

  OP_MULTMED = 0x3e,

  OP_UNDEF3f = 0x3f,

  OP_LDIL    = 0x08,

  OP_ADDIL   = 0x0a,

  OP_LDO     = 0x0d,

  OP_LDB     = 0x10,

  OP_LDH     = 0x11,

  OP_LDW     = 0x12,

  OP_LDWM    = 0x13,

  OP_STB     = 0x18,

  OP_STH     = 0x19,

  OP_STW     = 0x1a,

  OP_STWM    = 0x1b,

  OP_LDD     = 0x14,

  OP_STD     = 0x1c,

  OP_FLDW    = 0x16,

  OP_LDWL    = 0x17,

  OP_FSTW    = 0x1e,

  OP_STWL    = 0x1f,

  OP_COMBT   = 0x20,

  OP_COMIBT  = 0x21,

  OP_COMBF   = 0x22,

  OP_COMIBF  = 0x23,

  OP_CMPBDT  = 0x27,

  OP_ADDBT   = 0x28,

  OP_ADDIBT  = 0x29,

  OP_ADDBF   = 0x2a,

  OP_ADDIBF  = 0x2b,

  OP_CMPBDF  = 0x2f,

  OP_BVB     = 0x30,

  OP_BB      = 0x31,

  OP_MOVB    = 0x32,

  OP_MOVIB   = 0x33,

  OP_CMPIBD  = 0x3b,

  OP_COMICLR = 0x24,

  OP_SUBI    = 0x25,

  OP_ADDIT   = 0x2c,

  OP_ADDI    = 0x2d,

  OP_BE      = 0x38,

  OP_BLE     = 0x39,

  OP_BL      = 0x3a

};

/* Insert VALUE into INSN using R_FORMAT to determine exactly what

   bits to change.  */

static inline int

hppa_rebuild_insn (int insn, int value, int r_format)

{

  switch (r_format)

    {

    case 11:

      return (insn & ~ 0x7ff) | low_sign_unext (value, 11);

    case 12:

      return (insn & ~ 0x1ffd) | re_assemble_12 (value);

    case 10:

      return (insn & ~ 0x3ff1) | re_assemble_14 (value & -8);

    case -11:

      return (insn & ~ 0x3ff9) | re_assemble_14 (value & -4);

    case 14:

      return (insn & ~ 0x3fff) | re_assemble_14 (value);

    case -10:

      return (insn & ~ 0xfff1) | re_assemble_16 (value & -8);

    case -16:

      return (insn & ~ 0xfff9) | re_assemble_16 (value & -4);

    case 16:

      return (insn & ~ 0xffff) | re_assemble_16 (value);

    case 17:

      return (insn & ~ 0x1f1ffd) | re_assemble_17 (value);

    case 21:

      return (insn & ~ 0x1fffff) | re_assemble_21 (value);

    case 22:

      return (insn & ~ 0x3ff1ffd) | re_assemble_22 (value);

    case 32:

      return value;

    default:

      abort ();

    }

  return insn;

}

#endif /* _LIBHPPA_H */

/* Table of opcodes for the PA-RISC.

   Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,

   2001, 2002, 2003, 2004, 2005

   Free Software Foundation, Inc.

   Contributed by the Center for Software Science at the

   University of Utah (pa-gdb-bugs@cs.utah.edu).

This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.

GAS/GDB is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 1, or (at your option)

any later version.

GAS/GDB is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with GAS or GDB; see the file COPYING.  If not, write to

the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

#if !defined(__STDC__) && !defined(const)

#define const

#endif

/*

 * Structure of an opcode table entry.

 */

/* There are two kinds of delay slot nullification: normal which is

 * controled by the nullification bit, and conditional, which depends

 * on the direction of the branch and its success or failure.

 *

 * NONE is unfortunately #defined in the hiux system include files.

 * #undef it away.

 */

#undef NONE

struct pa_opcode

{

    const char *name;

    unsigned long int match;        /* Bits that must be set...  */

    unsigned long int mask;        /* ... in these bits. */

    char *args;

    enum pa_arch arch;

    char flags;

};

/* Enables strict matching.  Opcodes with match errors are skipped

   when this bit is set.  */

#define FLAG_STRICT 0x1

/*

   All hppa opcodes are 32 bits.

   The match component is a mask saying which bits must match a

   particular opcode in order for an instruction to be an instance

   of that opcode.

   The args component is a string containing one character for each operand of

   the instruction.  Characters used as a prefix allow any second character to

   be used without conflicting with the main operand characters.

   Bit positions in this description follow HP usage of lsb = 31,

   "at" is lsb of field.

   In the args field, the following characters must match exactly:

        '+,() '

   In the args field, the following characters are unused:

        '  "         -  /   34 6789:;    '

        '@  C         M             [\]  '

        '`    e g                     }  '

   Here are all the characters:

        ' !"#$%&'()*+-,./0123456789:;<=>?'

        '@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'

        '`abcdefghijklmnopqrstuvwxyz{|}~ '

Kinds of operands:

   x    integer register field at 15.

   b    integer register field at 10.

   t    integer register field at 31.

   a        integer register field at 10 and 15 (for PERMH)

   5    5 bit immediate at 15.

   s    2 bit space specifier at 17.

   S    3 bit space specifier at 18.

   V    5 bit immediate value at 31

   i    11 bit immediate value at 31

   j    14 bit immediate value at 31

   k    21 bit immediate value at 31

   l    16 bit immediate value at 31 (wide mode only, unusual encoding).

   n        nullification for branch instructions

   N        nullification for spop and copr instructions

   w    12 bit branch displacement

   W    17 bit branch displacement (PC relative)

   X    22 bit branch displacement (PC relative)

   z    17 bit branch displacement (just a number, not an address)

Also these:

   .    2 bit shift amount at 25

   *    4 bit shift amount at 25

   p    5 bit shift count at 26 (to support the SHD instruction) encoded as

        31-p

   ~    6 bit shift count at 20,22:26 encoded as 63-~.

   P    5 bit bit position at 26

   q    6 bit bit position at 20,22:26

   T    5 bit field length at 31 (encoded as 32-T)

   %        6 bit field length at 23,27:31 (variable extract/deposit)

   |        6 bit field length at 19,27:31 (fixed extract/deposit)

   A    13 bit immediate at 18 (to support the BREAK instruction)

   ^        like b, but describes a control register

   !    sar (cr11) register

   D    26 bit immediate at 31 (to support the DIAG instruction)

   $    9 bit immediate at 28 (to support POPBTS)

   v    3 bit Special Function Unit identifier at 25

   O    20 bit Special Function Unit operation split between 15 bits at 20

        and 5 bits at 31

   o    15 bit Special Function Unit operation at 20

   2    22 bit Special Function Unit operation split between 17 bits at 20

        and 5 bits at 31

   1    15 bit Special Function Unit operation split between 10 bits at 20

        and 5 bits at 31

   0    10 bit Special Function Unit operation split between 5 bits at 20

        and 5 bits at 31

   u    3 bit coprocessor unit identifier at 25

   F    Source Floating Point Operand Format Completer encoded 2 bits at 20

   I    Source Floating Point Operand Format Completer encoded 1 bits at 20

        (for 0xe format FP instructions)

   G    Destination Floating Point Operand Format Completer encoded 2 bits at 18

   H    Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'

        (very similar to 'F')

   r        5 bit immediate value at 31 (for the break instruction)

        (very similar to V above, except the value is unsigned instead of

        low_sign_ext)

   R        5 bit immediate value at 15 (for the ssm, rsm, probei instructions)

        (same as r above, except the value is in a different location)

   U        10 bit immediate value at 15 (for SSM, RSM on pa2.0)

   Q        5 bit immediate value at 10 (a bit position specified in

        the bb instruction. It's the same as r above, except the

        value is in a different location)

   B        5 bit immediate value at 10 (a bit position specified in

        the bb instruction. Similar to Q, but 64 bit handling is

        different.

   Z    %r1 -- implicit target of addil instruction.

   L    ,%r2 completer for new syntax branch

   {    Source format completer for fcnv

   _    Destination format completer for fcnv

   h    cbit for fcmp

   =    gfx tests for ftest

   d    14 bit offset for single precision FP long load/store.

   #    14 bit offset for double precision FP load long/store.

   J    Yet another 14 bit offset for load/store with ma,mb completers.

   K    Yet another 14 bit offset for load/store with ma,mb completers.

   y    16 bit offset for word aligned load/store (PA2.0 wide).

   &    16 bit offset for dword aligned load/store (PA2.0 wide).

   <    16 bit offset for load/store with ma,mb completers (PA2.0 wide).

   >    16 bit offset for load/store with ma,mb completers (PA2.0 wide).

   Y    %sr0,%r31 -- implicit target of be,l instruction.

   @        implicit immediate value of 0

Completer operands all have 'c' as the prefix:

   cx   indexed load and store completer.

   cX   indexed load and store completer.  Like cx, but emits a space

        after in disassembler.

   cm   short load and store completer.

   cM   short load and store completer.  Like cm, but emits a space

        after in disassembler.

   cq   long load and store completer (like cm, but inserted into a

        different location in the target instruction).

   cs   store bytes short completer.

   cA   store bytes short completer.  Like cs, but emits a space

        after in disassembler.

   ce   long load/store completer for LDW/STW with a different encoding

        than the others

   cc   load cache control hint

   cd   load and clear cache control hint

   cC   store cache control hint

   co        ordered access

   cp        branch link and push completer

   cP        branch pop completer

   cl        branch link completer

   cg        branch gate completer

   cw        read/write completer for PROBE

   cW        wide completer for MFCTL

   cL        local processor completer for cache control

   cZ   System Control Completer (to support LPA, LHA, etc.)

   ci        correction completer for DCOR

   ca        add completer

   cy        32 bit add carry completer

   cY        64 bit add carry completer

   cv        signed overflow trap completer

   ct        trap on condition completer for ADDI, SUB

   cT        trap on condition completer for UADDCM

   cb        32 bit borrow completer for SUB

   cB        64 bit borrow completer for SUB

   ch        left/right half completer

   cH        signed/unsigned saturation completer

   cS        signed/unsigned completer at 21

   cz        zero/sign extension completer.

   c*        permutation completer

Condition operands all have '?' as the prefix:

   ?f   Floating point compare conditions (encoded as 5 bits at 31)

   ?a        add conditions

   ?A        64 bit add conditions

   ?@   add branch conditions followed by nullify

   ?d        non-negated add branch conditions

   ?D        negated add branch conditions

   ?w        wide mode non-negated add branch conditions

   ?W        wide mode negated add branch conditions

   ?s   compare/subtract conditions

   ?S        64 bit compare/subtract conditions

   ?t   non-negated compare and branch conditions

   ?n   32 bit compare and branch conditions followed by nullify

   ?N   64 bit compare and branch conditions followed by nullify

   ?Q        64 bit compare and branch conditions for CMPIB instruction

   ?l   logical conditions

   ?L        64 bit logical conditions

   ?b   branch on bit conditions

   ?B        64 bit branch on bit conditions

   ?x   shift/extract/deposit conditions

   ?X        64 bit shift/extract/deposit conditions

   ?y   shift/extract/deposit conditions followed by nullify for conditional

        branches

   ?u   unit conditions

   ?U   64 bit unit conditions

Floating point registers all have 'f' as a prefix:

   ft        target register at 31

   fT        target register with L/R halves at 31

   fa        operand 1 register at 10

   fA   operand 1 register with L/R halves at 10

   fX   Same as fA, except prints a space before register during disasm

   fb        operand 2 register at 15

   fB   operand 2 register with L/R halves at 15

   fC   operand 3 register with L/R halves at 16:18,21:23

   fe   Like fT, but encoding is different.

   fE   Same as fe, except prints a space before register during disasm.

   fx        target register at 15 (only for PA 2.0 long format FLDD/FSTD).

Float registers for fmpyadd and fmpysub:

   fi        mult operand 1 register at 10

   fj        mult operand 2 register at 15

   fk        mult target register at 20

   fl        add/sub operand register at 25

   fm        add/sub target register at 31

*/

#if 0

/* List of characters not to put a space after.  Note that

   "," is included, as the "spopN" operations use literal

   commas in their completer sections.  */

static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";

#endif

/* The order of the opcodes in this table is significant:

   * The assembler requires that all instances of the same mnemonic be

     consecutive.  If they aren't, the assembler will bomb at runtime.

   * Immediate fields use pa_get_absolute_expression to parse the

     string.  It will generate a "bad expression" error if passed

     a register name.  Thus, register index variants of an opcode

     need to precede immediate variants.

   * The disassembler does not care about the order of the opcodes

     except in cases where implicit addressing is used.

   Here are the rules for ordering the opcodes of a mnemonic:

   1) Opcodes with FLAG_STRICT should precede opcodes without

      FLAG_STRICT.

   2) Opcodes with FLAG_STRICT should be ordered as follows:

      register index opcodes, short immediate opcodes, and finally

      long immediate opcodes.  When both pa10 and pa11 variants

      of the same opcode are available, the pa10 opcode should

      come first for correct architectural promotion.

   3) When implicit addressing is available for an opcode, the

      implicit opcode should precede the explicit opcode.

   4) Opcodes without FLAG_STRICT should be ordered as follows:

      register index opcodes, long immediate opcodes, and finally

      short immediate opcodes.  */

static const struct pa_opcode pa_opcodes[] =

{

/* Pseudo-instructions.  */

{ "ldi",        0x34000000, 0xffe00000, "l,x", pa20w, 0},/* ldo val(r0),r */

{ "ldi",        0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */

{ "cmpib",        0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT},

{ "cmpib",         0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT},

{ "comib",         0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/

/* This entry is for the disassembler only.  It will never be used by

   assembler.  */

{ "comib",         0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/

{ "cmpb",        0x9c000000, 0xdc000000, "?Nnx,b,w", pa20, FLAG_STRICT},

{ "cmpb",        0x80000000, 0xf4000000, "?nnx,b,w", pa10, FLAG_STRICT},

{ "comb",        0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */

/* This entry is for the disassembler only.  It will never be used by

   assembler.  */

{ "comb",        0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */

{ "addb",        0xa0000000, 0xf4000000, "?Wnx,b,w", pa20w, FLAG_STRICT},

{ "addb",        0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */

/* This entry is for the disassembler only.  It will never be used by

   assembler.  */

{ "addb",        0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0},

{ "addib",        0xa4000000, 0xf4000000, "?Wn5,b,w", pa20w, FLAG_STRICT},

{ "addib",        0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/

/* This entry is for the disassembler only.  It will never be used by

   assembler.  */

{ "addib",        0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/

{ "nop",        0x08000240, 0xffffffff, "", pa10, 0},      /* or 0,0,0 */

{ "copy",        0x08000240, 0xffe0ffe0, "x,t", pa10, 0},   /* or r,0,t */

{ "mtsar",        0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */

/* Loads and Stores for integer registers.  */

{ "ldd",        0x0c0000c0, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT},

{ "ldd",        0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT},

{ "ldd",        0x0c0010e0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},

{ "ldd",        0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},

{ "ldd",        0x0c0010c0, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT},

{ "ldd",        0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT},

{ "ldd",        0x50000000, 0xfc000002, "cq&(b),x", pa20w, FLAG_STRICT},

{ "ldd",        0x50000000, 0xfc00c002, "cq#(b),x", pa20, FLAG_STRICT},

{ "ldd",        0x50000000, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT},

{ "ldw",        0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldw",        0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldw",        0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldw",        0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},

{ "ldw",        0x0c0010a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},

{ "ldw",        0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},

{ "ldw",        0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},

{ "ldw",        0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},

{ "ldw",        0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},

{ "ldw",        0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},

{ "ldw",        0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT},

{ "ldw",        0x5c000004, 0xfc000006, "ce>(b),x", pa20w, FLAG_STRICT},

{ "ldw",        0x48000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},

{ "ldw",        0x5c000004, 0xfc00c006, "ceK(b),x", pa20, FLAG_STRICT},

{ "ldw",        0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT},

{ "ldw",        0x4c000000, 0xfc00c000, "ceJ(b),x", pa10, FLAG_STRICT},

{ "ldw",        0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT},

{ "ldw",        0x48000000, 0xfc00c000, "j(b),x", pa10, 0},

{ "ldw",        0x48000000, 0xfc000000, "j(s,b),x", pa10, 0},

{ "ldh",        0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldh",        0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldh",        0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldh",        0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},

{ "ldh",        0x0c001060, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},

{ "ldh",        0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},

{ "ldh",        0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},

{ "ldh",        0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},

{ "ldh",        0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},

{ "ldh",        0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},

{ "ldh",        0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},

{ "ldh",        0x44000000, 0xfc00c000, "j(b),x", pa10, 0},

{ "ldh",        0x44000000, 0xfc000000, "j(s,b),x", pa10, 0},

{ "ldb",        0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldb",        0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldb",        0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldb",        0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},

{ "ldb",        0x0c001020, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},

{ "ldb",        0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},

{ "ldb",        0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},

{ "ldb",        0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},

{ "ldb",        0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},

{ "ldb",        0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},

{ "ldb",        0x40000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},

{ "ldb",        0x40000000, 0xfc00c000, "j(b),x", pa10, 0},

{ "ldb",        0x40000000, 0xfc000000, "j(s,b),x", pa10, 0},

{ "std",        0x0c0012e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},

{ "std",        0x0c0012e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},

{ "std",        0x0c0012c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT},

{ "std",        0x0c0012c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT},

{ "std",        0x70000000, 0xfc000002, "cqx,&(b)", pa20w, FLAG_STRICT},

{ "std",        0x70000000, 0xfc00c002, "cqx,#(b)", pa20, FLAG_STRICT},

{ "std",        0x70000000, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT},

{ "stw",        0x0c0012a0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},

{ "stw",        0x0c0012a0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},

{ "stw",        0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},

{ "stw",        0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},

{ "stw",        0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},

{ "stw",        0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},

{ "stw",        0x6c000000, 0xfc000000, "cex,<(b)", pa20w, FLAG_STRICT},

{ "stw",        0x7c000004, 0xfc000006, "cex,>(b)", pa20w, FLAG_STRICT},

{ "stw",        0x68000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},

{ "stw",        0x7c000004, 0xfc00c006, "cex,K(b)", pa20, FLAG_STRICT},

{ "stw",        0x7c000004, 0xfc000006, "cex,K(s,b)", pa20, FLAG_STRICT},

{ "stw",        0x6c000000, 0xfc00c000, "cex,J(b)", pa10, FLAG_STRICT},

{ "stw",        0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT},

{ "stw",        0x68000000, 0xfc00c000, "x,j(b)", pa10, 0},

{ "stw",        0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0},

{ "sth",        0x0c001260, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},

{ "sth",        0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},

{ "sth",        0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},

{ "sth",        0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},

{ "sth",        0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},

{ "sth",        0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},

{ "sth",        0x64000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},

{ "sth",        0x64000000, 0xfc00c000, "x,j(b)", pa10, 0},

{ "sth",        0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0},

{ "stb",        0x0c001220, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},

{ "stb",        0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},

{ "stb",        0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},

{ "stb",        0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},

{ "stb",        0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},

{ "stb",        0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},

{ "stb",        0x60000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},

{ "stb",        0x60000000, 0xfc00c000, "x,j(b)", pa10, 0},

{ "stb",        0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0},

{ "ldwm",        0x4c000000, 0xfc00c000, "j(b),x", pa10, 0},

{ "ldwm",        0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0},

{ "stwm",        0x6c000000, 0xfc00c000, "x,j(b)", pa10, 0},

{ "stwm",        0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0},

{ "ldwx",        0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldwx",        0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldwx",        0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldwx",        0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},

{ "ldwx",        0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, 0},

{ "ldwx",        0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0},

{ "ldhx",        0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldhx",        0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldhx",        0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldhx",        0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},

{ "ldhx",        0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, 0},

{ "ldhx",        0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0},

{ "ldbx",        0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldbx",        0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldbx",        0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldbx",        0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},

{ "ldbx",        0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, 0},

{ "ldbx",        0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, 0},

{ "ldwa",        0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldwa",        0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldwa",        0x0c0011a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},

{ "ldwa",        0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},

{ "ldwa",        0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},

{ "ldcw",        0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldcw",        0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldcw",        0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT},

{ "ldcw",        0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT},

{ "ldcw",        0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},

{ "ldcw",        0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},

{ "ldcw",        0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT},

{ "ldcw",        0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT},

{ "stwa",        0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT},

{ "stwa",        0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},

{ "stwa",        0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},

{ "stby",        0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, FLAG_STRICT},

{ "stby",        0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, FLAG_STRICT},

{ "stby",        0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT},

{ "stby",        0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT},

{ "ldda",        0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT},

{ "ldda",        0x0c001120, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},

{ "ldda",        0x0c001100, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT},

{ "ldcd",        0x0c000140, 0xfc00d3c0, "cxcdx(b),t", pa20, FLAG_STRICT},

{ "ldcd",        0x0c000140, 0xfc0013c0, "cxcdx(s,b),t", pa20, FLAG_STRICT},

{ "ldcd",        0x0c001140, 0xfc00d3c0, "cmcd5(b),t", pa20, FLAG_STRICT},

{ "ldcd",        0x0c001140, 0xfc0013c0, "cmcd5(s,b),t", pa20, FLAG_STRICT},

{ "stda",        0x0c0013e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},

{ "stda",        0x0c0013c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT},

{ "ldwax",        0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldwax",        0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},

{ "ldwax",        0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0},

{ "ldcwx",        0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},

{ "ldcwx",        0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},

{ "ldcwx",        0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT},

{ "ldcwx",        0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT},

{ "ldcwx",        0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, 0},

{ "ldcwx",        0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0},

{ "ldws",        0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},

{ "ldws",        0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},

{ "ldws",        0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},

{ "ldws",        0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},

{ "ldws",        0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, 0},

{ "ldws",        0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0},