root / target-ppc / cpu.h @ f5fc40bb
History | View | Annotate | Download (82.5 kB)
1 |
/*
|
---|---|
2 |
* PowerPC emulation cpu definitions for qemu.
|
3 |
*
|
4 |
* Copyright (c) 2003-2007 Jocelyn Mayer
|
5 |
*
|
6 |
* This library is free software; you can redistribute it and/or
|
7 |
* modify it under the terms of the GNU Lesser General Public
|
8 |
* License as published by the Free Software Foundation; either
|
9 |
* version 2 of the License, or (at your option) any later version.
|
10 |
*
|
11 |
* This library is distributed in the hope that it will be useful,
|
12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 |
* Lesser General Public License for more details.
|
15 |
*
|
16 |
* You should have received a copy of the GNU Lesser General Public
|
17 |
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
18 |
*/
|
19 |
#if !defined (__CPU_PPC_H__)
|
20 |
#define __CPU_PPC_H__
|
21 |
|
22 |
#include "config.h" |
23 |
#include "qemu-common.h" |
24 |
|
25 |
//#define PPC_EMULATE_32BITS_HYPV
|
26 |
|
27 |
#if defined (TARGET_PPC64)
|
28 |
/* PowerPC 64 definitions */
|
29 |
#define TARGET_LONG_BITS 64 |
30 |
#define TARGET_PAGE_BITS 12 |
31 |
|
32 |
/* Note that the official physical address space bits is 62-M where M
|
33 |
is implementation dependent. I've not looked up M for the set of
|
34 |
cpus we emulate at the system level. */
|
35 |
#define TARGET_PHYS_ADDR_SPACE_BITS 62 |
36 |
|
37 |
/* Note that the PPC environment architecture talks about 80 bit virtual
|
38 |
addresses, with segmentation. Obviously that's not all visible to a
|
39 |
single process, which is all we're concerned with here. */
|
40 |
#ifdef TARGET_ABI32
|
41 |
# define TARGET_VIRT_ADDR_SPACE_BITS 32 |
42 |
#else
|
43 |
# define TARGET_VIRT_ADDR_SPACE_BITS 64 |
44 |
#endif
|
45 |
|
46 |
#define TARGET_PAGE_BITS_16M 24 |
47 |
|
48 |
#else /* defined (TARGET_PPC64) */ |
49 |
/* PowerPC 32 definitions */
|
50 |
#define TARGET_LONG_BITS 32 |
51 |
|
52 |
#if defined(TARGET_PPCEMB)
|
53 |
/* Specific definitions for PowerPC embedded */
|
54 |
/* BookE have 36 bits physical address space */
|
55 |
#if defined(CONFIG_USER_ONLY)
|
56 |
/* It looks like a lot of Linux programs assume page size
|
57 |
* is 4kB long. This is evil, but we have to deal with it...
|
58 |
*/
|
59 |
#define TARGET_PAGE_BITS 12 |
60 |
#else /* defined(CONFIG_USER_ONLY) */ |
61 |
/* Pages can be 1 kB small */
|
62 |
#define TARGET_PAGE_BITS 10 |
63 |
#endif /* defined(CONFIG_USER_ONLY) */ |
64 |
#else /* defined(TARGET_PPCEMB) */ |
65 |
/* "standard" PowerPC 32 definitions */
|
66 |
#define TARGET_PAGE_BITS 12 |
67 |
#endif /* defined(TARGET_PPCEMB) */ |
68 |
|
69 |
#define TARGET_PHYS_ADDR_SPACE_BITS 32 |
70 |
#define TARGET_VIRT_ADDR_SPACE_BITS 32 |
71 |
|
72 |
#endif /* defined (TARGET_PPC64) */ |
73 |
|
74 |
#define CPUState struct CPUPPCState |
75 |
|
76 |
#include "cpu-defs.h" |
77 |
|
78 |
#include "softfloat.h" |
79 |
|
80 |
#define TARGET_HAS_ICE 1 |
81 |
|
82 |
#if defined (TARGET_PPC64)
|
83 |
#define ELF_MACHINE EM_PPC64
|
84 |
#else
|
85 |
#define ELF_MACHINE EM_PPC
|
86 |
#endif
|
87 |
|
88 |
/*****************************************************************************/
|
89 |
/* MMU model */
|
90 |
typedef enum powerpc_mmu_t powerpc_mmu_t; |
91 |
enum powerpc_mmu_t {
|
92 |
POWERPC_MMU_UNKNOWN = 0x00000000,
|
93 |
/* Standard 32 bits PowerPC MMU */
|
94 |
POWERPC_MMU_32B = 0x00000001,
|
95 |
/* PowerPC 6xx MMU with software TLB */
|
96 |
POWERPC_MMU_SOFT_6xx = 0x00000002,
|
97 |
/* PowerPC 74xx MMU with software TLB */
|
98 |
POWERPC_MMU_SOFT_74xx = 0x00000003,
|
99 |
/* PowerPC 4xx MMU with software TLB */
|
100 |
POWERPC_MMU_SOFT_4xx = 0x00000004,
|
101 |
/* PowerPC 4xx MMU with software TLB and zones protections */
|
102 |
POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
|
103 |
/* PowerPC MMU in real mode only */
|
104 |
POWERPC_MMU_REAL = 0x00000006,
|
105 |
/* Freescale MPC8xx MMU model */
|
106 |
POWERPC_MMU_MPC8xx = 0x00000007,
|
107 |
/* BookE MMU model */
|
108 |
POWERPC_MMU_BOOKE = 0x00000008,
|
109 |
/* BookE 2.06 MMU model */
|
110 |
POWERPC_MMU_BOOKE206 = 0x00000009,
|
111 |
/* PowerPC 601 MMU model (specific BATs format) */
|
112 |
POWERPC_MMU_601 = 0x0000000A,
|
113 |
#if defined(TARGET_PPC64)
|
114 |
#define POWERPC_MMU_64 0x00010000 |
115 |
#define POWERPC_MMU_1TSEG 0x00020000 |
116 |
/* 64 bits PowerPC MMU */
|
117 |
POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
|
118 |
/* 620 variant (no segment exceptions) */
|
119 |
POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
|
120 |
/* Architecture 2.06 variant */
|
121 |
POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,
|
122 |
#endif /* defined(TARGET_PPC64) */ |
123 |
}; |
124 |
|
125 |
/*****************************************************************************/
|
126 |
/* Exception model */
|
127 |
typedef enum powerpc_excp_t powerpc_excp_t; |
128 |
enum powerpc_excp_t {
|
129 |
POWERPC_EXCP_UNKNOWN = 0,
|
130 |
/* Standard PowerPC exception model */
|
131 |
POWERPC_EXCP_STD, |
132 |
/* PowerPC 40x exception model */
|
133 |
POWERPC_EXCP_40x, |
134 |
/* PowerPC 601 exception model */
|
135 |
POWERPC_EXCP_601, |
136 |
/* PowerPC 602 exception model */
|
137 |
POWERPC_EXCP_602, |
138 |
/* PowerPC 603 exception model */
|
139 |
POWERPC_EXCP_603, |
140 |
/* PowerPC 603e exception model */
|
141 |
POWERPC_EXCP_603E, |
142 |
/* PowerPC G2 exception model */
|
143 |
POWERPC_EXCP_G2, |
144 |
/* PowerPC 604 exception model */
|
145 |
POWERPC_EXCP_604, |
146 |
/* PowerPC 7x0 exception model */
|
147 |
POWERPC_EXCP_7x0, |
148 |
/* PowerPC 7x5 exception model */
|
149 |
POWERPC_EXCP_7x5, |
150 |
/* PowerPC 74xx exception model */
|
151 |
POWERPC_EXCP_74xx, |
152 |
/* BookE exception model */
|
153 |
POWERPC_EXCP_BOOKE, |
154 |
#if defined(TARGET_PPC64)
|
155 |
/* PowerPC 970 exception model */
|
156 |
POWERPC_EXCP_970, |
157 |
/* POWER7 exception model */
|
158 |
POWERPC_EXCP_POWER7, |
159 |
#endif /* defined(TARGET_PPC64) */ |
160 |
}; |
161 |
|
162 |
/*****************************************************************************/
|
163 |
/* Exception vectors definitions */
|
164 |
enum {
|
165 |
POWERPC_EXCP_NONE = -1,
|
166 |
/* The 64 first entries are used by the PowerPC embedded specification */
|
167 |
POWERPC_EXCP_CRITICAL = 0, /* Critical input */ |
168 |
POWERPC_EXCP_MCHECK = 1, /* Machine check exception */ |
169 |
POWERPC_EXCP_DSI = 2, /* Data storage exception */ |
170 |
POWERPC_EXCP_ISI = 3, /* Instruction storage exception */ |
171 |
POWERPC_EXCP_EXTERNAL = 4, /* External input */ |
172 |
POWERPC_EXCP_ALIGN = 5, /* Alignment exception */ |
173 |
POWERPC_EXCP_PROGRAM = 6, /* Program exception */ |
174 |
POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */ |
175 |
POWERPC_EXCP_SYSCALL = 8, /* System call exception */ |
176 |
POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */ |
177 |
POWERPC_EXCP_DECR = 10, /* Decrementer exception */ |
178 |
POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */ |
179 |
POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */ |
180 |
POWERPC_EXCP_DTLB = 13, /* Data TLB miss */ |
181 |
POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */ |
182 |
POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */ |
183 |
/* Vectors 16 to 31 are reserved */
|
184 |
POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */ |
185 |
POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */ |
186 |
POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */ |
187 |
POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */ |
188 |
POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */ |
189 |
POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */ |
190 |
/* Vectors 38 to 63 are reserved */
|
191 |
/* Exceptions defined in the PowerPC server specification */
|
192 |
POWERPC_EXCP_RESET = 64, /* System reset exception */ |
193 |
POWERPC_EXCP_DSEG = 65, /* Data segment exception */ |
194 |
POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */ |
195 |
POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */ |
196 |
POWERPC_EXCP_TRACE = 68, /* Trace exception */ |
197 |
POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */ |
198 |
POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */ |
199 |
POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */ |
200 |
POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */ |
201 |
POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */ |
202 |
/* 40x specific exceptions */
|
203 |
POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */ |
204 |
/* 601 specific exceptions */
|
205 |
POWERPC_EXCP_IO = 75, /* IO error exception */ |
206 |
POWERPC_EXCP_RUNM = 76, /* Run mode exception */ |
207 |
/* 602 specific exceptions */
|
208 |
POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */ |
209 |
/* 602/603 specific exceptions */
|
210 |
POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */ |
211 |
POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */ |
212 |
POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */ |
213 |
/* Exceptions available on most PowerPC */
|
214 |
POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */ |
215 |
POWERPC_EXCP_DABR = 82, /* Data address breakpoint */ |
216 |
POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */ |
217 |
POWERPC_EXCP_SMI = 84, /* System management interrupt */ |
218 |
POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */ |
219 |
/* 7xx/74xx specific exceptions */
|
220 |
POWERPC_EXCP_THERM = 86, /* Thermal interrupt */ |
221 |
/* 74xx specific exceptions */
|
222 |
POWERPC_EXCP_VPUA = 87, /* Vector assist exception */ |
223 |
/* 970FX specific exceptions */
|
224 |
POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */ |
225 |
POWERPC_EXCP_MAINT = 89, /* Maintenance exception */ |
226 |
/* Freescale embedded cores specific exceptions */
|
227 |
POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */ |
228 |
POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */ |
229 |
POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */ |
230 |
POWERPC_EXCP_DTLBE = 93, /* Data TLB error */ |
231 |
/* EOL */
|
232 |
POWERPC_EXCP_NB = 96,
|
233 |
/* Qemu exceptions: used internally during code translation */
|
234 |
POWERPC_EXCP_STOP = 0x200, /* stop translation */ |
235 |
POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */ |
236 |
/* Qemu exceptions: special cases we want to stop translation */
|
237 |
POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ |
238 |
POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ |
239 |
POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */ |
240 |
}; |
241 |
|
242 |
/* Exceptions error codes */
|
243 |
enum {
|
244 |
/* Exception subtypes for POWERPC_EXCP_ALIGN */
|
245 |
POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
246 |
POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
247 |
POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
248 |
POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
249 |
POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
250 |
POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
251 |
/* Exception subtypes for POWERPC_EXCP_PROGRAM */
|
252 |
/* FP exceptions */
|
253 |
POWERPC_EXCP_FP = 0x10,
|
254 |
POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */ |
255 |
POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */ |
256 |
POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
257 |
POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */ |
258 |
POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */ |
259 |
POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */ |
260 |
POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
261 |
POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
262 |
POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
263 |
POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
264 |
POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
265 |
POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
266 |
POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
267 |
/* Invalid instruction */
|
268 |
POWERPC_EXCP_INVAL = 0x20,
|
269 |
POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
270 |
POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
271 |
POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
272 |
POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
273 |
/* Privileged instruction */
|
274 |
POWERPC_EXCP_PRIV = 0x30,
|
275 |
POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */ |
276 |
POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */ |
277 |
/* Trap */
|
278 |
POWERPC_EXCP_TRAP = 0x40,
|
279 |
}; |
280 |
|
281 |
/*****************************************************************************/
|
282 |
/* Input pins model */
|
283 |
typedef enum powerpc_input_t powerpc_input_t; |
284 |
enum powerpc_input_t {
|
285 |
PPC_FLAGS_INPUT_UNKNOWN = 0,
|
286 |
/* PowerPC 6xx bus */
|
287 |
PPC_FLAGS_INPUT_6xx, |
288 |
/* BookE bus */
|
289 |
PPC_FLAGS_INPUT_BookE, |
290 |
/* PowerPC 405 bus */
|
291 |
PPC_FLAGS_INPUT_405, |
292 |
/* PowerPC 970 bus */
|
293 |
PPC_FLAGS_INPUT_970, |
294 |
/* PowerPC POWER7 bus */
|
295 |
PPC_FLAGS_INPUT_POWER7, |
296 |
/* PowerPC 401 bus */
|
297 |
PPC_FLAGS_INPUT_401, |
298 |
/* Freescale RCPU bus */
|
299 |
PPC_FLAGS_INPUT_RCPU, |
300 |
}; |
301 |
|
302 |
#define PPC_INPUT(env) (env->bus_model)
|
303 |
|
304 |
/*****************************************************************************/
|
305 |
typedef struct ppc_def_t ppc_def_t; |
306 |
typedef struct opc_handler_t opc_handler_t; |
307 |
|
308 |
/*****************************************************************************/
|
309 |
/* Types used to describe some PowerPC registers */
|
310 |
typedef struct CPUPPCState CPUPPCState; |
311 |
typedef struct ppc_tb_t ppc_tb_t; |
312 |
typedef struct ppc_spr_t ppc_spr_t; |
313 |
typedef struct ppc_dcr_t ppc_dcr_t; |
314 |
typedef union ppc_avr_t ppc_avr_t; |
315 |
typedef union ppc_tlb_t ppc_tlb_t; |
316 |
|
317 |
/* SPR access micro-ops generations callbacks */
|
318 |
struct ppc_spr_t {
|
319 |
void (*uea_read)(void *opaque, int gpr_num, int spr_num); |
320 |
void (*uea_write)(void *opaque, int spr_num, int gpr_num); |
321 |
#if !defined(CONFIG_USER_ONLY)
|
322 |
void (*oea_read)(void *opaque, int gpr_num, int spr_num); |
323 |
void (*oea_write)(void *opaque, int spr_num, int gpr_num); |
324 |
void (*hea_read)(void *opaque, int gpr_num, int spr_num); |
325 |
void (*hea_write)(void *opaque, int spr_num, int gpr_num); |
326 |
#endif
|
327 |
const char *name; |
328 |
}; |
329 |
|
330 |
/* Altivec registers (128 bits) */
|
331 |
union ppc_avr_t {
|
332 |
float32 f[4];
|
333 |
uint8_t u8[16];
|
334 |
uint16_t u16[8];
|
335 |
uint32_t u32[4];
|
336 |
int8_t s8[16];
|
337 |
int16_t s16[8];
|
338 |
int32_t s32[4];
|
339 |
uint64_t u64[2];
|
340 |
}; |
341 |
|
342 |
#if !defined(CONFIG_USER_ONLY)
|
343 |
/* Software TLB cache */
|
344 |
typedef struct ppc6xx_tlb_t ppc6xx_tlb_t; |
345 |
struct ppc6xx_tlb_t {
|
346 |
target_ulong pte0; |
347 |
target_ulong pte1; |
348 |
target_ulong EPN; |
349 |
}; |
350 |
|
351 |
typedef struct ppcemb_tlb_t ppcemb_tlb_t; |
352 |
struct ppcemb_tlb_t {
|
353 |
target_phys_addr_t RPN; |
354 |
target_ulong EPN; |
355 |
target_ulong PID; |
356 |
target_ulong size; |
357 |
uint32_t prot; |
358 |
uint32_t attr; /* Storage attributes */
|
359 |
}; |
360 |
|
361 |
typedef struct ppcmas_tlb_t { |
362 |
uint32_t mas8; |
363 |
uint32_t mas1; |
364 |
uint64_t mas2; |
365 |
uint64_t mas7_3; |
366 |
} ppcmas_tlb_t; |
367 |
|
368 |
union ppc_tlb_t {
|
369 |
ppc6xx_tlb_t *tlb6; |
370 |
ppcemb_tlb_t *tlbe; |
371 |
ppcmas_tlb_t *tlbm; |
372 |
}; |
373 |
|
374 |
/* possible TLB variants */
|
375 |
#define TLB_NONE 0 |
376 |
#define TLB_6XX 1 |
377 |
#define TLB_EMB 2 |
378 |
#define TLB_MAS 3 |
379 |
#endif
|
380 |
|
381 |
#define SDR_32_HTABORG 0xFFFF0000UL |
382 |
#define SDR_32_HTABMASK 0x000001FFUL |
383 |
|
384 |
#if defined(TARGET_PPC64)
|
385 |
#define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL |
386 |
#define SDR_64_HTABSIZE 0x000000000000001FULL |
387 |
#endif /* defined(TARGET_PPC64 */ |
388 |
|
389 |
#define HASH_PTE_SIZE_32 8 |
390 |
#define HASH_PTE_SIZE_64 16 |
391 |
|
392 |
typedef struct ppc_slb_t ppc_slb_t; |
393 |
struct ppc_slb_t {
|
394 |
uint64_t esid; |
395 |
uint64_t vsid; |
396 |
}; |
397 |
|
398 |
/* Bits in the SLB ESID word */
|
399 |
#define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL |
400 |
#define SLB_ESID_V 0x0000000008000000ULL /* valid */ |
401 |
|
402 |
/* Bits in the SLB VSID word */
|
403 |
#define SLB_VSID_SHIFT 12 |
404 |
#define SLB_VSID_SHIFT_1T 24 |
405 |
#define SLB_VSID_SSIZE_SHIFT 62 |
406 |
#define SLB_VSID_B 0xc000000000000000ULL |
407 |
#define SLB_VSID_B_256M 0x0000000000000000ULL |
408 |
#define SLB_VSID_B_1T 0x4000000000000000ULL |
409 |
#define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL |
410 |
#define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
|
411 |
#define SLB_VSID_KS 0x0000000000000800ULL |
412 |
#define SLB_VSID_KP 0x0000000000000400ULL |
413 |
#define SLB_VSID_N 0x0000000000000200ULL /* no-execute */ |
414 |
#define SLB_VSID_L 0x0000000000000100ULL |
415 |
#define SLB_VSID_C 0x0000000000000080ULL /* class */ |
416 |
#define SLB_VSID_LP 0x0000000000000030ULL |
417 |
#define SLB_VSID_ATTR 0x0000000000000FFFULL |
418 |
|
419 |
#define SEGMENT_SHIFT_256M 28 |
420 |
#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1)) |
421 |
|
422 |
#define SEGMENT_SHIFT_1T 40 |
423 |
#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1)) |
424 |
|
425 |
|
426 |
/*****************************************************************************/
|
427 |
/* Machine state register bits definition */
|
428 |
#define MSR_SF 63 /* Sixty-four-bit mode hflags */ |
429 |
#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */ |
430 |
#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ |
431 |
#define MSR_SHV 60 /* hypervisor state hflags */ |
432 |
#define MSR_CM 31 /* Computation mode for BookE hflags */ |
433 |
#define MSR_ICM 30 /* Interrupt computation mode for BookE */ |
434 |
#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */ |
435 |
#define MSR_GS 28 /* guest state for BookE */ |
436 |
#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ |
437 |
#define MSR_VR 25 /* altivec available x hflags */ |
438 |
#define MSR_SPE 25 /* SPE enable for BookE x hflags */ |
439 |
#define MSR_AP 23 /* Access privilege state on 602 hflags */ |
440 |
#define MSR_SA 22 /* Supervisor access mode on 602 hflags */ |
441 |
#define MSR_KEY 19 /* key bit on 603e */ |
442 |
#define MSR_POW 18 /* Power management */ |
443 |
#define MSR_TGPR 17 /* TGPR usage on 602/603 x */ |
444 |
#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */ |
445 |
#define MSR_ILE 16 /* Interrupt little-endian mode */ |
446 |
#define MSR_EE 15 /* External interrupt enable */ |
447 |
#define MSR_PR 14 /* Problem state hflags */ |
448 |
#define MSR_FP 13 /* Floating point available hflags */ |
449 |
#define MSR_ME 12 /* Machine check interrupt enable */ |
450 |
#define MSR_FE0 11 /* Floating point exception mode 0 hflags */ |
451 |
#define MSR_SE 10 /* Single-step trace enable x hflags */ |
452 |
#define MSR_DWE 10 /* Debug wait enable on 405 x */ |
453 |
#define MSR_UBLE 10 /* User BTB lock enable on e500 x */ |
454 |
#define MSR_BE 9 /* Branch trace enable x hflags */ |
455 |
#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */ |
456 |
#define MSR_FE1 8 /* Floating point exception mode 1 hflags */ |
457 |
#define MSR_AL 7 /* AL bit on POWER */ |
458 |
#define MSR_EP 6 /* Exception prefix on 601 */ |
459 |
#define MSR_IR 5 /* Instruction relocate */ |
460 |
#define MSR_DR 4 /* Data relocate */ |
461 |
#define MSR_PE 3 /* Protection enable on 403 */ |
462 |
#define MSR_PX 2 /* Protection exclusive on 403 x */ |
463 |
#define MSR_PMM 2 /* Performance monitor mark on POWER x */ |
464 |
#define MSR_RI 1 /* Recoverable interrupt 1 */ |
465 |
#define MSR_LE 0 /* Little-endian mode 1 hflags */ |
466 |
|
467 |
#define msr_sf ((env->msr >> MSR_SF) & 1) |
468 |
#define msr_isf ((env->msr >> MSR_ISF) & 1) |
469 |
#define msr_shv ((env->msr >> MSR_SHV) & 1) |
470 |
#define msr_cm ((env->msr >> MSR_CM) & 1) |
471 |
#define msr_icm ((env->msr >> MSR_ICM) & 1) |
472 |
#define msr_thv ((env->msr >> MSR_THV) & 1) |
473 |
#define msr_gs ((env->msr >> MSR_GS) & 1) |
474 |
#define msr_ucle ((env->msr >> MSR_UCLE) & 1) |
475 |
#define msr_vr ((env->msr >> MSR_VR) & 1) |
476 |
#define msr_spe ((env->msr >> MSR_SPE) & 1) |
477 |
#define msr_ap ((env->msr >> MSR_AP) & 1) |
478 |
#define msr_sa ((env->msr >> MSR_SA) & 1) |
479 |
#define msr_key ((env->msr >> MSR_KEY) & 1) |
480 |
#define msr_pow ((env->msr >> MSR_POW) & 1) |
481 |
#define msr_tgpr ((env->msr >> MSR_TGPR) & 1) |
482 |
#define msr_ce ((env->msr >> MSR_CE) & 1) |
483 |
#define msr_ile ((env->msr >> MSR_ILE) & 1) |
484 |
#define msr_ee ((env->msr >> MSR_EE) & 1) |
485 |
#define msr_pr ((env->msr >> MSR_PR) & 1) |
486 |
#define msr_fp ((env->msr >> MSR_FP) & 1) |
487 |
#define msr_me ((env->msr >> MSR_ME) & 1) |
488 |
#define msr_fe0 ((env->msr >> MSR_FE0) & 1) |
489 |
#define msr_se ((env->msr >> MSR_SE) & 1) |
490 |
#define msr_dwe ((env->msr >> MSR_DWE) & 1) |
491 |
#define msr_uble ((env->msr >> MSR_UBLE) & 1) |
492 |
#define msr_be ((env->msr >> MSR_BE) & 1) |
493 |
#define msr_de ((env->msr >> MSR_DE) & 1) |
494 |
#define msr_fe1 ((env->msr >> MSR_FE1) & 1) |
495 |
#define msr_al ((env->msr >> MSR_AL) & 1) |
496 |
#define msr_ep ((env->msr >> MSR_EP) & 1) |
497 |
#define msr_ir ((env->msr >> MSR_IR) & 1) |
498 |
#define msr_dr ((env->msr >> MSR_DR) & 1) |
499 |
#define msr_pe ((env->msr >> MSR_PE) & 1) |
500 |
#define msr_px ((env->msr >> MSR_PX) & 1) |
501 |
#define msr_pmm ((env->msr >> MSR_PMM) & 1) |
502 |
#define msr_ri ((env->msr >> MSR_RI) & 1) |
503 |
#define msr_le ((env->msr >> MSR_LE) & 1) |
504 |
/* Hypervisor bit is more specific */
|
505 |
#if defined(TARGET_PPC64)
|
506 |
#define MSR_HVB (1ULL << MSR_SHV) |
507 |
#define msr_hv msr_shv
|
508 |
#else
|
509 |
#if defined(PPC_EMULATE_32BITS_HYPV)
|
510 |
#define MSR_HVB (1ULL << MSR_THV) |
511 |
#define msr_hv msr_thv
|
512 |
#else
|
513 |
#define MSR_HVB (0ULL) |
514 |
#define msr_hv (0) |
515 |
#endif
|
516 |
#endif
|
517 |
|
518 |
/* Exception state register bits definition */
|
519 |
#define ESR_ST 23 /* Exception was caused by a store type access. */ |
520 |
|
521 |
enum {
|
522 |
POWERPC_FLAG_NONE = 0x00000000,
|
523 |
/* Flag for MSR bit 25 signification (VRE/SPE) */
|
524 |
POWERPC_FLAG_SPE = 0x00000001,
|
525 |
POWERPC_FLAG_VRE = 0x00000002,
|
526 |
/* Flag for MSR bit 17 signification (TGPR/CE) */
|
527 |
POWERPC_FLAG_TGPR = 0x00000004,
|
528 |
POWERPC_FLAG_CE = 0x00000008,
|
529 |
/* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
|
530 |
POWERPC_FLAG_SE = 0x00000010,
|
531 |
POWERPC_FLAG_DWE = 0x00000020,
|
532 |
POWERPC_FLAG_UBLE = 0x00000040,
|
533 |
/* Flag for MSR bit 9 signification (BE/DE) */
|
534 |
POWERPC_FLAG_BE = 0x00000080,
|
535 |
POWERPC_FLAG_DE = 0x00000100,
|
536 |
/* Flag for MSR bit 2 signification (PX/PMM) */
|
537 |
POWERPC_FLAG_PX = 0x00000200,
|
538 |
POWERPC_FLAG_PMM = 0x00000400,
|
539 |
/* Flag for special features */
|
540 |
/* Decrementer clock: RTC clock (POWER, 601) or bus clock */
|
541 |
POWERPC_FLAG_RTC_CLK = 0x00010000,
|
542 |
POWERPC_FLAG_BUS_CLK = 0x00020000,
|
543 |
}; |
544 |
|
545 |
/*****************************************************************************/
|
546 |
/* Floating point status and control register */
|
547 |
#define FPSCR_FX 31 /* Floating-point exception summary */ |
548 |
#define FPSCR_FEX 30 /* Floating-point enabled exception summary */ |
549 |
#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */ |
550 |
#define FPSCR_OX 28 /* Floating-point overflow exception */ |
551 |
#define FPSCR_UX 27 /* Floating-point underflow exception */ |
552 |
#define FPSCR_ZX 26 /* Floating-point zero divide exception */ |
553 |
#define FPSCR_XX 25 /* Floating-point inexact exception */ |
554 |
#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */ |
555 |
#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */ |
556 |
#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */ |
557 |
#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */ |
558 |
#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */ |
559 |
#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */ |
560 |
#define FPSCR_FR 18 /* Floating-point fraction rounded */ |
561 |
#define FPSCR_FI 17 /* Floating-point fraction inexact */ |
562 |
#define FPSCR_C 16 /* Floating-point result class descriptor */ |
563 |
#define FPSCR_FL 15 /* Floating-point less than or negative */ |
564 |
#define FPSCR_FG 14 /* Floating-point greater than or negative */ |
565 |
#define FPSCR_FE 13 /* Floating-point equal or zero */ |
566 |
#define FPSCR_FU 12 /* Floating-point unordered or NaN */ |
567 |
#define FPSCR_FPCC 12 /* Floating-point condition code */ |
568 |
#define FPSCR_FPRF 12 /* Floating-point result flags */ |
569 |
#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */ |
570 |
#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */ |
571 |
#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */ |
572 |
#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */ |
573 |
#define FPSCR_OE 6 /* Floating-point overflow exception enable */ |
574 |
#define FPSCR_UE 5 /* Floating-point undeflow exception enable */ |
575 |
#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */ |
576 |
#define FPSCR_XE 3 /* Floating-point inexact exception enable */ |
577 |
#define FPSCR_NI 2 /* Floating-point non-IEEE mode */ |
578 |
#define FPSCR_RN1 1 |
579 |
#define FPSCR_RN 0 /* Floating-point rounding control */ |
580 |
#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1) |
581 |
#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1) |
582 |
#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1) |
583 |
#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1) |
584 |
#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1) |
585 |
#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1) |
586 |
#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1) |
587 |
#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1) |
588 |
#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1) |
589 |
#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1) |
590 |
#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1) |
591 |
#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1) |
592 |
#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF) |
593 |
#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1) |
594 |
#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1) |
595 |
#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1) |
596 |
#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1) |
597 |
#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1) |
598 |
#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1) |
599 |
#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1) |
600 |
#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1) |
601 |
#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1) |
602 |
#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3) |
603 |
/* Invalid operation exception summary */
|
604 |
#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \ |
605 |
(1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \ |
606 |
(1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \ |
607 |
(1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \ |
608 |
(1 << FPSCR_VXCVI)))
|
609 |
/* exception summary */
|
610 |
#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F) |
611 |
/* enabled exception summary */
|
612 |
#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
|
613 |
0x1F)
|
614 |
|
615 |
/*****************************************************************************/
|
616 |
/* Vector status and control register */
|
617 |
#define VSCR_NJ 16 /* Vector non-java */ |
618 |
#define VSCR_SAT 0 /* Vector saturation */ |
619 |
#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1) |
620 |
#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1) |
621 |
|
622 |
/*****************************************************************************/
|
623 |
/* BookE e500 MMU registers */
|
624 |
|
625 |
#define MAS0_NV_SHIFT 0 |
626 |
#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT) |
627 |
|
628 |
#define MAS0_WQ_SHIFT 12 |
629 |
#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT) |
630 |
/* Write TLB entry regardless of reservation */
|
631 |
#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT) |
632 |
/* Write TLB entry only already in use */
|
633 |
#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT) |
634 |
/* Clear TLB entry */
|
635 |
#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT) |
636 |
|
637 |
#define MAS0_HES_SHIFT 14 |
638 |
#define MAS0_HES (1 << MAS0_HES_SHIFT) |
639 |
|
640 |
#define MAS0_ESEL_SHIFT 16 |
641 |
#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT) |
642 |
|
643 |
#define MAS0_TLBSEL_SHIFT 28 |
644 |
#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT) |
645 |
#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT) |
646 |
#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT) |
647 |
#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT) |
648 |
#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT) |
649 |
|
650 |
#define MAS0_ATSEL_SHIFT 31 |
651 |
#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT) |
652 |
#define MAS0_ATSEL_TLB 0 |
653 |
#define MAS0_ATSEL_LRAT MAS0_ATSEL
|
654 |
|
655 |
#define MAS1_TSIZE_SHIFT 8 |
656 |
#define MAS1_TSIZE_MASK (0xf << MAS1_TSIZE_SHIFT) |
657 |
|
658 |
#define MAS1_TS_SHIFT 12 |
659 |
#define MAS1_TS (1 << MAS1_TS_SHIFT) |
660 |
|
661 |
#define MAS1_IND_SHIFT 13 |
662 |
#define MAS1_IND (1 << MAS1_IND_SHIFT) |
663 |
|
664 |
#define MAS1_TID_SHIFT 16 |
665 |
#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT) |
666 |
|
667 |
#define MAS1_IPROT_SHIFT 30 |
668 |
#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT) |
669 |
|
670 |
#define MAS1_VALID_SHIFT 31 |
671 |
#define MAS1_VALID 0x80000000 |
672 |
|
673 |
#define MAS2_EPN_SHIFT 12 |
674 |
#define MAS2_EPN_MASK (0xfffff << MAS2_EPN_SHIFT) |
675 |
|
676 |
#define MAS2_ACM_SHIFT 6 |
677 |
#define MAS2_ACM (1 << MAS2_ACM_SHIFT) |
678 |
|
679 |
#define MAS2_VLE_SHIFT 5 |
680 |
#define MAS2_VLE (1 << MAS2_VLE_SHIFT) |
681 |
|
682 |
#define MAS2_W_SHIFT 4 |
683 |
#define MAS2_W (1 << MAS2_W_SHIFT) |
684 |
|
685 |
#define MAS2_I_SHIFT 3 |
686 |
#define MAS2_I (1 << MAS2_I_SHIFT) |
687 |
|
688 |
#define MAS2_M_SHIFT 2 |
689 |
#define MAS2_M (1 << MAS2_M_SHIFT) |
690 |
|
691 |
#define MAS2_G_SHIFT 1 |
692 |
#define MAS2_G (1 << MAS2_G_SHIFT) |
693 |
|
694 |
#define MAS2_E_SHIFT 0 |
695 |
#define MAS2_E (1 << MAS2_E_SHIFT) |
696 |
|
697 |
#define MAS3_RPN_SHIFT 12 |
698 |
#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT) |
699 |
|
700 |
#define MAS3_U0 0x00000200 |
701 |
#define MAS3_U1 0x00000100 |
702 |
#define MAS3_U2 0x00000080 |
703 |
#define MAS3_U3 0x00000040 |
704 |
#define MAS3_UX 0x00000020 |
705 |
#define MAS3_SX 0x00000010 |
706 |
#define MAS3_UW 0x00000008 |
707 |
#define MAS3_SW 0x00000004 |
708 |
#define MAS3_UR 0x00000002 |
709 |
#define MAS3_SR 0x00000001 |
710 |
#define MAS3_SPSIZE_SHIFT 1 |
711 |
#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT) |
712 |
|
713 |
#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
|
714 |
#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
|
715 |
#define MAS4_TIDSELD_MASK 0x00030000 |
716 |
#define MAS4_TIDSELD_PID0 0x00000000 |
717 |
#define MAS4_TIDSELD_PID1 0x00010000 |
718 |
#define MAS4_TIDSELD_PID2 0x00020000 |
719 |
#define MAS4_TIDSELD_PIDZ 0x00030000 |
720 |
#define MAS4_INDD 0x00008000 /* Default IND */ |
721 |
#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
|
722 |
#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
|
723 |
#define MAS4_ACMD 0x00000040 |
724 |
#define MAS4_VLED 0x00000020 |
725 |
#define MAS4_WD 0x00000010 |
726 |
#define MAS4_ID 0x00000008 |
727 |
#define MAS4_MD 0x00000004 |
728 |
#define MAS4_GD 0x00000002 |
729 |
#define MAS4_ED 0x00000001 |
730 |
#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */ |
731 |
#define MAS4_WIMGED_SHIFT 0 |
732 |
|
733 |
#define MAS5_SGS 0x80000000 |
734 |
#define MAS5_SLPID_MASK 0x00000fff |
735 |
|
736 |
#define MAS6_SPID0 0x3fff0000 |
737 |
#define MAS6_SPID1 0x00007ffe |
738 |
#define MAS6_ISIZE(x) MAS1_TSIZE(x)
|
739 |
#define MAS6_SAS 0x00000001 |
740 |
#define MAS6_SPID MAS6_SPID0
|
741 |
#define MAS6_SIND 0x00000002 /* Indirect page */ |
742 |
#define MAS6_SIND_SHIFT 1 |
743 |
#define MAS6_SPID_MASK 0x3fff0000 |
744 |
#define MAS6_SPID_SHIFT 16 |
745 |
#define MAS6_ISIZE_MASK 0x00000f80 |
746 |
#define MAS6_ISIZE_SHIFT 7 |
747 |
|
748 |
#define MAS7_RPN 0xffffffff |
749 |
|
750 |
#define MAS8_TGS 0x80000000 |
751 |
#define MAS8_VF 0x40000000 |
752 |
#define MAS8_TLBPID 0x00000fff |
753 |
|
754 |
/* Bit definitions for MMUCFG */
|
755 |
#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */ |
756 |
#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */ |
757 |
#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */ |
758 |
#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */ |
759 |
#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */ |
760 |
#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */ |
761 |
#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */ |
762 |
#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */ |
763 |
#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */ |
764 |
|
765 |
/* Bit definitions for MMUCSR0 */
|
766 |
#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */ |
767 |
#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */ |
768 |
#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */ |
769 |
#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */ |
770 |
#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
|
771 |
MMUCSR0_TLB2FI | MMUCSR0_TLB3FI) |
772 |
#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */ |
773 |
#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */ |
774 |
#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */ |
775 |
#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */ |
776 |
|
777 |
/* TLBnCFG encoding */
|
778 |
#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */ |
779 |
#define TLBnCFG_HES 0x00002000 /* HW select supported */ |
780 |
#define TLBnCFG_AVAIL 0x00004000 /* variable page size */ |
781 |
#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */ |
782 |
#define TLBnCFG_GTWE 0x00010000 /* Guest can write */ |
783 |
#define TLBnCFG_IND 0x00020000 /* IND entries supported */ |
784 |
#define TLBnCFG_PT 0x00040000 /* Can load from page table */ |
785 |
#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */ |
786 |
#define TLBnCFG_MINSIZE_SHIFT 20 |
787 |
#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */ |
788 |
#define TLBnCFG_MAXSIZE_SHIFT 16 |
789 |
#define TLBnCFG_ASSOC 0xff000000 /* Associativity */ |
790 |
#define TLBnCFG_ASSOC_SHIFT 24 |
791 |
|
792 |
/* TLBnPS encoding */
|
793 |
#define TLBnPS_4K 0x00000004 |
794 |
#define TLBnPS_8K 0x00000008 |
795 |
#define TLBnPS_16K 0x00000010 |
796 |
#define TLBnPS_32K 0x00000020 |
797 |
#define TLBnPS_64K 0x00000040 |
798 |
#define TLBnPS_128K 0x00000080 |
799 |
#define TLBnPS_256K 0x00000100 |
800 |
#define TLBnPS_512K 0x00000200 |
801 |
#define TLBnPS_1M 0x00000400 |
802 |
#define TLBnPS_2M 0x00000800 |
803 |
#define TLBnPS_4M 0x00001000 |
804 |
#define TLBnPS_8M 0x00002000 |
805 |
#define TLBnPS_16M 0x00004000 |
806 |
#define TLBnPS_32M 0x00008000 |
807 |
#define TLBnPS_64M 0x00010000 |
808 |
#define TLBnPS_128M 0x00020000 |
809 |
#define TLBnPS_256M 0x00040000 |
810 |
#define TLBnPS_512M 0x00080000 |
811 |
#define TLBnPS_1G 0x00100000 |
812 |
#define TLBnPS_2G 0x00200000 |
813 |
#define TLBnPS_4G 0x00400000 |
814 |
#define TLBnPS_8G 0x00800000 |
815 |
#define TLBnPS_16G 0x01000000 |
816 |
#define TLBnPS_32G 0x02000000 |
817 |
#define TLBnPS_64G 0x04000000 |
818 |
#define TLBnPS_128G 0x08000000 |
819 |
#define TLBnPS_256G 0x10000000 |
820 |
|
821 |
/* tlbilx action encoding */
|
822 |
#define TLBILX_T_ALL 0 |
823 |
#define TLBILX_T_TID 1 |
824 |
#define TLBILX_T_FULLMATCH 3 |
825 |
#define TLBILX_T_CLASS0 4 |
826 |
#define TLBILX_T_CLASS1 5 |
827 |
#define TLBILX_T_CLASS2 6 |
828 |
#define TLBILX_T_CLASS3 7 |
829 |
|
830 |
/* BookE 2.06 helper defines */
|
831 |
|
832 |
#define BOOKE206_FLUSH_TLB0 (1 << 0) |
833 |
#define BOOKE206_FLUSH_TLB1 (1 << 1) |
834 |
#define BOOKE206_FLUSH_TLB2 (1 << 2) |
835 |
#define BOOKE206_FLUSH_TLB3 (1 << 3) |
836 |
|
837 |
/* number of possible TLBs */
|
838 |
#define BOOKE206_MAX_TLBN 4 |
839 |
|
840 |
/*****************************************************************************/
|
841 |
/* The whole PowerPC CPU context */
|
842 |
#define NB_MMU_MODES 3 |
843 |
|
844 |
struct CPUPPCState {
|
845 |
/* First are the most commonly used resources
|
846 |
* during translated code execution
|
847 |
*/
|
848 |
/* general purpose registers */
|
849 |
target_ulong gpr[32];
|
850 |
#if !defined(TARGET_PPC64)
|
851 |
/* Storage for GPR MSB, used by the SPE extension */
|
852 |
target_ulong gprh[32];
|
853 |
#endif
|
854 |
/* LR */
|
855 |
target_ulong lr; |
856 |
/* CTR */
|
857 |
target_ulong ctr; |
858 |
/* condition register */
|
859 |
uint32_t crf[8];
|
860 |
/* XER */
|
861 |
target_ulong xer; |
862 |
/* Reservation address */
|
863 |
target_ulong reserve_addr; |
864 |
/* Reservation value */
|
865 |
target_ulong reserve_val; |
866 |
/* Reservation store address */
|
867 |
target_ulong reserve_ea; |
868 |
/* Reserved store source register and size */
|
869 |
target_ulong reserve_info; |
870 |
|
871 |
/* Those ones are used in supervisor mode only */
|
872 |
/* machine state register */
|
873 |
target_ulong msr; |
874 |
/* temporary general purpose registers */
|
875 |
target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */ |
876 |
|
877 |
/* Floating point execution context */
|
878 |
float_status fp_status; |
879 |
/* floating point registers */
|
880 |
float64 fpr[32];
|
881 |
/* floating point status and control register */
|
882 |
uint32_t fpscr; |
883 |
|
884 |
/* Next instruction pointer */
|
885 |
target_ulong nip; |
886 |
|
887 |
int access_type; /* when a memory exception occurs, the access |
888 |
type is stored here */
|
889 |
|
890 |
CPU_COMMON |
891 |
|
892 |
/* MMU context - only relevant for full system emulation */
|
893 |
#if !defined(CONFIG_USER_ONLY)
|
894 |
#if defined(TARGET_PPC64)
|
895 |
/* Address space register */
|
896 |
target_ulong asr; |
897 |
/* PowerPC 64 SLB area */
|
898 |
ppc_slb_t slb[64];
|
899 |
int slb_nr;
|
900 |
#endif
|
901 |
/* segment registers */
|
902 |
target_phys_addr_t htab_base; |
903 |
target_phys_addr_t htab_mask; |
904 |
target_ulong sr[32];
|
905 |
/* externally stored hash table */
|
906 |
uint8_t *external_htab; |
907 |
/* BATs */
|
908 |
int nb_BATs;
|
909 |
target_ulong DBAT[2][8]; |
910 |
target_ulong IBAT[2][8]; |
911 |
/* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
|
912 |
int nb_tlb; /* Total number of TLB */ |
913 |
int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */ |
914 |
int nb_ways; /* Number of ways in the TLB set */ |
915 |
int last_way; /* Last used way used to allocate TLB in a LRU way */ |
916 |
int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ |
917 |
int nb_pids; /* Number of available PID registers */ |
918 |
int tlb_type; /* Type of TLB we're dealing with */ |
919 |
ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
|
920 |
/* 403 dedicated access protection registers */
|
921 |
target_ulong pb[4];
|
922 |
#endif
|
923 |
|
924 |
/* Other registers */
|
925 |
/* Special purpose registers */
|
926 |
target_ulong spr[1024];
|
927 |
ppc_spr_t spr_cb[1024];
|
928 |
/* Altivec registers */
|
929 |
ppc_avr_t avr[32];
|
930 |
uint32_t vscr; |
931 |
/* SPE registers */
|
932 |
uint64_t spe_acc; |
933 |
uint32_t spe_fscr; |
934 |
/* SPE and Altivec can share a status since they will never be used
|
935 |
* simultaneously */
|
936 |
float_status vec_status; |
937 |
|
938 |
/* Internal devices resources */
|
939 |
/* Time base and decrementer */
|
940 |
ppc_tb_t *tb_env; |
941 |
/* Device control registers */
|
942 |
ppc_dcr_t *dcr_env; |
943 |
|
944 |
int dcache_line_size;
|
945 |
int icache_line_size;
|
946 |
|
947 |
/* Those resources are used during exception processing */
|
948 |
/* CPU model definition */
|
949 |
target_ulong msr_mask; |
950 |
powerpc_mmu_t mmu_model; |
951 |
powerpc_excp_t excp_model; |
952 |
powerpc_input_t bus_model; |
953 |
int bfd_mach;
|
954 |
uint32_t flags; |
955 |
uint64_t insns_flags; |
956 |
uint64_t insns_flags2; |
957 |
|
958 |
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
|
959 |
target_phys_addr_t vpa; |
960 |
target_phys_addr_t slb_shadow; |
961 |
target_phys_addr_t dispatch_trace_log; |
962 |
uint32_t dtl_size; |
963 |
#endif /* TARGET_PPC64 */ |
964 |
|
965 |
int error_code;
|
966 |
uint32_t pending_interrupts; |
967 |
#if !defined(CONFIG_USER_ONLY)
|
968 |
/* This is the IRQ controller, which is implementation dependant
|
969 |
* and only relevant when emulating a complete machine.
|
970 |
*/
|
971 |
uint32_t irq_input_state; |
972 |
void **irq_inputs;
|
973 |
/* Exception vectors */
|
974 |
target_ulong excp_vectors[POWERPC_EXCP_NB]; |
975 |
target_ulong excp_prefix; |
976 |
target_ulong hreset_excp_prefix; |
977 |
target_ulong ivor_mask; |
978 |
target_ulong ivpr_mask; |
979 |
target_ulong hreset_vector; |
980 |
#endif
|
981 |
|
982 |
/* Those resources are used only during code translation */
|
983 |
/* opcode handlers */
|
984 |
opc_handler_t *opcodes[0x40];
|
985 |
|
986 |
/* Those resources are used only in Qemu core */
|
987 |
target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
|
988 |
target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
|
989 |
int mmu_idx; /* precomputed MMU index to speed up mem accesses */ |
990 |
|
991 |
/* Power management */
|
992 |
int power_mode;
|
993 |
int (*check_pow)(CPUPPCState *env);
|
994 |
|
995 |
#if !defined(CONFIG_USER_ONLY)
|
996 |
void *load_info; /* Holds boot loading state. */ |
997 |
#endif
|
998 |
}; |
999 |
|
1000 |
#if !defined(CONFIG_USER_ONLY)
|
1001 |
/* Context used internally during MMU translations */
|
1002 |
typedef struct mmu_ctx_t mmu_ctx_t; |
1003 |
struct mmu_ctx_t {
|
1004 |
target_phys_addr_t raddr; /* Real address */
|
1005 |
target_phys_addr_t eaddr; /* Effective address */
|
1006 |
int prot; /* Protection bits */ |
1007 |
target_phys_addr_t hash[2]; /* Pagetable hash values */ |
1008 |
target_ulong ptem; /* Virtual segment ID | API */
|
1009 |
int key; /* Access key */ |
1010 |
int nx; /* Non-execute area */ |
1011 |
}; |
1012 |
#endif
|
1013 |
|
1014 |
/*****************************************************************************/
|
1015 |
CPUPPCState *cpu_ppc_init (const char *cpu_model); |
1016 |
void ppc_translate_init(void); |
1017 |
int cpu_ppc_exec (CPUPPCState *s);
|
1018 |
void cpu_ppc_close (CPUPPCState *s);
|
1019 |
/* you can call this signal handler from your SIGBUS and SIGSEGV
|
1020 |
signal handlers to inform the virtual CPU of exceptions. non zero
|
1021 |
is returned if the signal was handled by the virtual CPU. */
|
1022 |
int cpu_ppc_signal_handler (int host_signum, void *pinfo, |
1023 |
void *puc);
|
1024 |
int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw, |
1025 |
int mmu_idx, int is_softmmu); |
1026 |
#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
|
1027 |
#if !defined(CONFIG_USER_ONLY)
|
1028 |
int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
|
1029 |
int rw, int access_type); |
1030 |
#endif
|
1031 |
void do_interrupt (CPUPPCState *env);
|
1032 |
void ppc_hw_interrupt (CPUPPCState *env);
|
1033 |
|
1034 |
void cpu_dump_rfi (target_ulong RA, target_ulong msr);
|
1035 |
|
1036 |
#if !defined(CONFIG_USER_ONLY)
|
1037 |
void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code, |
1038 |
target_ulong pte0, target_ulong pte1); |
1039 |
void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value); |
1040 |
void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value); |
1041 |
void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value); |
1042 |
void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value); |
1043 |
void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value); |
1044 |
void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value); |
1045 |
void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
|
1046 |
#if defined(TARGET_PPC64)
|
1047 |
void ppc_store_asr (CPUPPCState *env, target_ulong value);
|
1048 |
target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
|
1049 |
target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr);
|
1050 |
int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
|
1051 |
int ppc_load_slb_esid (CPUPPCState *env, target_ulong rb, target_ulong *rt);
|
1052 |
int ppc_load_slb_vsid (CPUPPCState *env, target_ulong rb, target_ulong *rt);
|
1053 |
#endif /* defined(TARGET_PPC64) */ |
1054 |
void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value); |
1055 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
1056 |
void ppc_store_msr (CPUPPCState *env, target_ulong value);
|
1057 |
|
1058 |
void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
|
1059 |
|
1060 |
const ppc_def_t *cpu_ppc_find_by_name (const char *name); |
1061 |
int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def); |
1062 |
|
1063 |
/* Time-base and decrementer management */
|
1064 |
#ifndef NO_CPU_IO_DEFS
|
1065 |
uint64_t cpu_ppc_load_tbl (CPUPPCState *env); |
1066 |
uint32_t cpu_ppc_load_tbu (CPUPPCState *env); |
1067 |
void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
|
1068 |
void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
|
1069 |
uint64_t cpu_ppc_load_atbl (CPUPPCState *env); |
1070 |
uint32_t cpu_ppc_load_atbu (CPUPPCState *env); |
1071 |
void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
|
1072 |
void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
|
1073 |
uint32_t cpu_ppc_load_decr (CPUPPCState *env); |
1074 |
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
|
1075 |
uint32_t cpu_ppc_load_hdecr (CPUPPCState *env); |
1076 |
void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
|
1077 |
uint64_t cpu_ppc_load_purr (CPUPPCState *env); |
1078 |
void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
|
1079 |
uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env); |
1080 |
uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env); |
1081 |
#if !defined(CONFIG_USER_ONLY)
|
1082 |
void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
|
1083 |
void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
|
1084 |
target_ulong load_40x_pit (CPUPPCState *env); |
1085 |
void store_40x_pit (CPUPPCState *env, target_ulong val);
|
1086 |
void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
|
1087 |
void store_40x_sler (CPUPPCState *env, uint32_t val);
|
1088 |
void store_booke_tcr (CPUPPCState *env, target_ulong val);
|
1089 |
void store_booke_tsr (CPUPPCState *env, target_ulong val);
|
1090 |
void booke206_flush_tlb(CPUState *env, int flags, const int check_iprot); |
1091 |
target_phys_addr_t booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb); |
1092 |
int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
|
1093 |
target_phys_addr_t *raddrp, target_ulong address, |
1094 |
uint32_t pid, int ext, int i); |
1095 |
int ppcmas_tlb_check(CPUState *env, ppcmas_tlb_t *tlb,
|
1096 |
target_phys_addr_t *raddrp, target_ulong address, |
1097 |
uint32_t pid); |
1098 |
void ppc_tlb_invalidate_all (CPUPPCState *env);
|
1099 |
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
|
1100 |
#if defined(TARGET_PPC64)
|
1101 |
void ppc_slb_invalidate_all (CPUPPCState *env);
|
1102 |
void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
|
1103 |
#endif
|
1104 |
int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
|
1105 |
#endif
|
1106 |
#endif
|
1107 |
|
1108 |
static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn) |
1109 |
{ |
1110 |
uint64_t gprv; |
1111 |
|
1112 |
gprv = env->gpr[gprn]; |
1113 |
#if !defined(TARGET_PPC64)
|
1114 |
if (env->flags & POWERPC_FLAG_SPE) {
|
1115 |
/* If the CPU implements the SPE extension, we have to get the
|
1116 |
* high bits of the GPR from the gprh storage area
|
1117 |
*/
|
1118 |
gprv &= 0xFFFFFFFFULL;
|
1119 |
gprv |= (uint64_t)env->gprh[gprn] << 32;
|
1120 |
} |
1121 |
#endif
|
1122 |
|
1123 |
return gprv;
|
1124 |
} |
1125 |
|
1126 |
/* Device control registers */
|
1127 |
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp); |
1128 |
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val); |
1129 |
|
1130 |
#define cpu_init cpu_ppc_init
|
1131 |
#define cpu_exec cpu_ppc_exec
|
1132 |
#define cpu_gen_code cpu_ppc_gen_code
|
1133 |
#define cpu_signal_handler cpu_ppc_signal_handler
|
1134 |
#define cpu_list ppc_cpu_list
|
1135 |
|
1136 |
#define CPU_SAVE_VERSION 4 |
1137 |
|
1138 |
/* MMU modes definitions */
|
1139 |
#define MMU_MODE0_SUFFIX _user
|
1140 |
#define MMU_MODE1_SUFFIX _kernel
|
1141 |
#define MMU_MODE2_SUFFIX _hypv
|
1142 |
#define MMU_USER_IDX 0 |
1143 |
static inline int cpu_mmu_index (CPUState *env) |
1144 |
{ |
1145 |
return env->mmu_idx;
|
1146 |
} |
1147 |
|
1148 |
#if defined(CONFIG_USER_ONLY)
|
1149 |
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
1150 |
{ |
1151 |
if (newsp)
|
1152 |
env->gpr[1] = newsp;
|
1153 |
env->gpr[3] = 0; |
1154 |
} |
1155 |
#endif
|
1156 |
|
1157 |
#include "cpu-all.h" |
1158 |
|
1159 |
/*****************************************************************************/
|
1160 |
/* CRF definitions */
|
1161 |
#define CRF_LT 3 |
1162 |
#define CRF_GT 2 |
1163 |
#define CRF_EQ 1 |
1164 |
#define CRF_SO 0 |
1165 |
#define CRF_CH (1 << CRF_LT) |
1166 |
#define CRF_CL (1 << CRF_GT) |
1167 |
#define CRF_CH_OR_CL (1 << CRF_EQ) |
1168 |
#define CRF_CH_AND_CL (1 << CRF_SO) |
1169 |
|
1170 |
/* XER definitions */
|
1171 |
#define XER_SO 31 |
1172 |
#define XER_OV 30 |
1173 |
#define XER_CA 29 |
1174 |
#define XER_CMP 8 |
1175 |
#define XER_BC 0 |
1176 |
#define xer_so ((env->xer >> XER_SO) & 1) |
1177 |
#define xer_ov ((env->xer >> XER_OV) & 1) |
1178 |
#define xer_ca ((env->xer >> XER_CA) & 1) |
1179 |
#define xer_cmp ((env->xer >> XER_CMP) & 0xFF) |
1180 |
#define xer_bc ((env->xer >> XER_BC) & 0x7F) |
1181 |
|
1182 |
/* SPR definitions */
|
1183 |
#define SPR_MQ (0x000) |
1184 |
#define SPR_XER (0x001) |
1185 |
#define SPR_601_VRTCU (0x004) |
1186 |
#define SPR_601_VRTCL (0x005) |
1187 |
#define SPR_601_UDECR (0x006) |
1188 |
#define SPR_LR (0x008) |
1189 |
#define SPR_CTR (0x009) |
1190 |
#define SPR_DSISR (0x012) |
1191 |
#define SPR_DAR (0x013) /* DAE for PowerPC 601 */ |
1192 |
#define SPR_601_RTCU (0x014) |
1193 |
#define SPR_601_RTCL (0x015) |
1194 |
#define SPR_DECR (0x016) |
1195 |
#define SPR_SDR1 (0x019) |
1196 |
#define SPR_SRR0 (0x01A) |
1197 |
#define SPR_SRR1 (0x01B) |
1198 |
#define SPR_AMR (0x01D) |
1199 |
#define SPR_BOOKE_PID (0x030) |
1200 |
#define SPR_BOOKE_DECAR (0x036) |
1201 |
#define SPR_BOOKE_CSRR0 (0x03A) |
1202 |
#define SPR_BOOKE_CSRR1 (0x03B) |
1203 |
#define SPR_BOOKE_DEAR (0x03D) |
1204 |
#define SPR_BOOKE_ESR (0x03E) |
1205 |
#define SPR_BOOKE_IVPR (0x03F) |
1206 |
#define SPR_MPC_EIE (0x050) |
1207 |
#define SPR_MPC_EID (0x051) |
1208 |
#define SPR_MPC_NRI (0x052) |
1209 |
#define SPR_CTRL (0x088) |
1210 |
#define SPR_MPC_CMPA (0x090) |
1211 |
#define SPR_MPC_CMPB (0x091) |
1212 |
#define SPR_MPC_CMPC (0x092) |
1213 |
#define SPR_MPC_CMPD (0x093) |
1214 |
#define SPR_MPC_ECR (0x094) |
1215 |
#define SPR_MPC_DER (0x095) |
1216 |
#define SPR_MPC_COUNTA (0x096) |
1217 |
#define SPR_MPC_COUNTB (0x097) |
1218 |
#define SPR_UCTRL (0x098) |
1219 |
#define SPR_MPC_CMPE (0x098) |
1220 |
#define SPR_MPC_CMPF (0x099) |
1221 |
#define SPR_MPC_CMPG (0x09A) |
1222 |
#define SPR_MPC_CMPH (0x09B) |
1223 |
#define SPR_MPC_LCTRL1 (0x09C) |
1224 |
#define SPR_MPC_LCTRL2 (0x09D) |
1225 |
#define SPR_MPC_ICTRL (0x09E) |
1226 |
#define SPR_MPC_BAR (0x09F) |
1227 |
#define SPR_VRSAVE (0x100) |
1228 |
#define SPR_USPRG0 (0x100) |
1229 |
#define SPR_USPRG1 (0x101) |
1230 |
#define SPR_USPRG2 (0x102) |
1231 |
#define SPR_USPRG3 (0x103) |
1232 |
#define SPR_USPRG4 (0x104) |
1233 |
#define SPR_USPRG5 (0x105) |
1234 |
#define SPR_USPRG6 (0x106) |
1235 |
#define SPR_USPRG7 (0x107) |
1236 |
#define SPR_VTBL (0x10C) |
1237 |
#define SPR_VTBU (0x10D) |
1238 |
#define SPR_SPRG0 (0x110) |
1239 |
#define SPR_SPRG1 (0x111) |
1240 |
#define SPR_SPRG2 (0x112) |
1241 |
#define SPR_SPRG3 (0x113) |
1242 |
#define SPR_SPRG4 (0x114) |
1243 |
#define SPR_SCOMC (0x114) |
1244 |
#define SPR_SPRG5 (0x115) |
1245 |
#define SPR_SCOMD (0x115) |
1246 |
#define SPR_SPRG6 (0x116) |
1247 |
#define SPR_SPRG7 (0x117) |
1248 |
#define SPR_ASR (0x118) |
1249 |
#define SPR_EAR (0x11A) |
1250 |
#define SPR_TBL (0x11C) |
1251 |
#define SPR_TBU (0x11D) |
1252 |
#define SPR_TBU40 (0x11E) |
1253 |
#define SPR_SVR (0x11E) |
1254 |
#define SPR_BOOKE_PIR (0x11E) |
1255 |
#define SPR_PVR (0x11F) |
1256 |
#define SPR_HSPRG0 (0x130) |
1257 |
#define SPR_BOOKE_DBSR (0x130) |
1258 |
#define SPR_HSPRG1 (0x131) |
1259 |
#define SPR_HDSISR (0x132) |
1260 |
#define SPR_HDAR (0x133) |
1261 |
#define SPR_BOOKE_EPCR (0x133) |
1262 |
#define SPR_SPURR (0x134) |
1263 |
#define SPR_BOOKE_DBCR0 (0x134) |
1264 |
#define SPR_IBCR (0x135) |
1265 |
#define SPR_PURR (0x135) |
1266 |
#define SPR_BOOKE_DBCR1 (0x135) |
1267 |
#define SPR_DBCR (0x136) |
1268 |
#define SPR_HDEC (0x136) |
1269 |
#define SPR_BOOKE_DBCR2 (0x136) |
1270 |
#define SPR_HIOR (0x137) |
1271 |
#define SPR_MBAR (0x137) |
1272 |
#define SPR_RMOR (0x138) |
1273 |
#define SPR_BOOKE_IAC1 (0x138) |
1274 |
#define SPR_HRMOR (0x139) |
1275 |
#define SPR_BOOKE_IAC2 (0x139) |
1276 |
#define SPR_HSRR0 (0x13A) |
1277 |
#define SPR_BOOKE_IAC3 (0x13A) |
1278 |
#define SPR_HSRR1 (0x13B) |
1279 |
#define SPR_BOOKE_IAC4 (0x13B) |
1280 |
#define SPR_LPCR (0x13C) |
1281 |
#define SPR_BOOKE_DAC1 (0x13C) |
1282 |
#define SPR_LPIDR (0x13D) |
1283 |
#define SPR_DABR2 (0x13D) |
1284 |
#define SPR_BOOKE_DAC2 (0x13D) |
1285 |
#define SPR_BOOKE_DVC1 (0x13E) |
1286 |
#define SPR_BOOKE_DVC2 (0x13F) |
1287 |
#define SPR_BOOKE_TSR (0x150) |
1288 |
#define SPR_BOOKE_TCR (0x154) |
1289 |
#define SPR_BOOKE_IVOR0 (0x190) |
1290 |
#define SPR_BOOKE_IVOR1 (0x191) |
1291 |
#define SPR_BOOKE_IVOR2 (0x192) |
1292 |
#define SPR_BOOKE_IVOR3 (0x193) |
1293 |
#define SPR_BOOKE_IVOR4 (0x194) |
1294 |
#define SPR_BOOKE_IVOR5 (0x195) |
1295 |
#define SPR_BOOKE_IVOR6 (0x196) |
1296 |
#define SPR_BOOKE_IVOR7 (0x197) |
1297 |
#define SPR_BOOKE_IVOR8 (0x198) |
1298 |
#define SPR_BOOKE_IVOR9 (0x199) |
1299 |
#define SPR_BOOKE_IVOR10 (0x19A) |
1300 |
#define SPR_BOOKE_IVOR11 (0x19B) |
1301 |
#define SPR_BOOKE_IVOR12 (0x19C) |
1302 |
#define SPR_BOOKE_IVOR13 (0x19D) |
1303 |
#define SPR_BOOKE_IVOR14 (0x19E) |
1304 |
#define SPR_BOOKE_IVOR15 (0x19F) |
1305 |
#define SPR_BOOKE_SPEFSCR (0x200) |
1306 |
#define SPR_Exxx_BBEAR (0x201) |
1307 |
#define SPR_Exxx_BBTAR (0x202) |
1308 |
#define SPR_Exxx_L1CFG0 (0x203) |
1309 |
#define SPR_Exxx_NPIDR (0x205) |
1310 |
#define SPR_ATBL (0x20E) |
1311 |
#define SPR_ATBU (0x20F) |
1312 |
#define SPR_IBAT0U (0x210) |
1313 |
#define SPR_BOOKE_IVOR32 (0x210) |
1314 |
#define SPR_RCPU_MI_GRA (0x210) |
1315 |
#define SPR_IBAT0L (0x211) |
1316 |
#define SPR_BOOKE_IVOR33 (0x211) |
1317 |
#define SPR_IBAT1U (0x212) |
1318 |
#define SPR_BOOKE_IVOR34 (0x212) |
1319 |
#define SPR_IBAT1L (0x213) |
1320 |
#define SPR_BOOKE_IVOR35 (0x213) |
1321 |
#define SPR_IBAT2U (0x214) |
1322 |
#define SPR_BOOKE_IVOR36 (0x214) |
1323 |
#define SPR_IBAT2L (0x215) |
1324 |
#define SPR_BOOKE_IVOR37 (0x215) |
1325 |
#define SPR_IBAT3U (0x216) |
1326 |
#define SPR_IBAT3L (0x217) |
1327 |
#define SPR_DBAT0U (0x218) |
1328 |
#define SPR_RCPU_L2U_GRA (0x218) |
1329 |
#define SPR_DBAT0L (0x219) |
1330 |
#define SPR_DBAT1U (0x21A) |
1331 |
#define SPR_DBAT1L (0x21B) |
1332 |
#define SPR_DBAT2U (0x21C) |
1333 |
#define SPR_DBAT2L (0x21D) |
1334 |
#define SPR_DBAT3U (0x21E) |
1335 |
#define SPR_DBAT3L (0x21F) |
1336 |
#define SPR_IBAT4U (0x230) |
1337 |
#define SPR_RPCU_BBCMCR (0x230) |
1338 |
#define SPR_MPC_IC_CST (0x230) |
1339 |
#define SPR_Exxx_CTXCR (0x230) |
1340 |
#define SPR_IBAT4L (0x231) |
1341 |
#define SPR_MPC_IC_ADR (0x231) |
1342 |
#define SPR_Exxx_DBCR3 (0x231) |
1343 |
#define SPR_IBAT5U (0x232) |
1344 |
#define SPR_MPC_IC_DAT (0x232) |
1345 |
#define SPR_Exxx_DBCNT (0x232) |
1346 |
#define SPR_IBAT5L (0x233) |
1347 |
#define SPR_IBAT6U (0x234) |
1348 |
#define SPR_IBAT6L (0x235) |
1349 |
#define SPR_IBAT7U (0x236) |
1350 |
#define SPR_IBAT7L (0x237) |
1351 |
#define SPR_DBAT4U (0x238) |
1352 |
#define SPR_RCPU_L2U_MCR (0x238) |
1353 |
#define SPR_MPC_DC_CST (0x238) |
1354 |
#define SPR_Exxx_ALTCTXCR (0x238) |
1355 |
#define SPR_DBAT4L (0x239) |
1356 |
#define SPR_MPC_DC_ADR (0x239) |
1357 |
#define SPR_DBAT5U (0x23A) |
1358 |
#define SPR_BOOKE_MCSRR0 (0x23A) |
1359 |
#define SPR_MPC_DC_DAT (0x23A) |
1360 |
#define SPR_DBAT5L (0x23B) |
1361 |
#define SPR_BOOKE_MCSRR1 (0x23B) |
1362 |
#define SPR_DBAT6U (0x23C) |
1363 |
#define SPR_BOOKE_MCSR (0x23C) |
1364 |
#define SPR_DBAT6L (0x23D) |
1365 |
#define SPR_Exxx_MCAR (0x23D) |
1366 |
#define SPR_DBAT7U (0x23E) |
1367 |
#define SPR_BOOKE_DSRR0 (0x23E) |
1368 |
#define SPR_DBAT7L (0x23F) |
1369 |
#define SPR_BOOKE_DSRR1 (0x23F) |
1370 |
#define SPR_BOOKE_SPRG8 (0x25C) |
1371 |
#define SPR_BOOKE_SPRG9 (0x25D) |
1372 |
#define SPR_BOOKE_MAS0 (0x270) |
1373 |
#define SPR_BOOKE_MAS1 (0x271) |
1374 |
#define SPR_BOOKE_MAS2 (0x272) |
1375 |
#define SPR_BOOKE_MAS3 (0x273) |
1376 |
#define SPR_BOOKE_MAS4 (0x274) |
1377 |
#define SPR_BOOKE_MAS5 (0x275) |
1378 |
#define SPR_BOOKE_MAS6 (0x276) |
1379 |
#define SPR_BOOKE_PID1 (0x279) |
1380 |
#define SPR_BOOKE_PID2 (0x27A) |
1381 |
#define SPR_MPC_DPDR (0x280) |
1382 |
#define SPR_MPC_IMMR (0x288) |
1383 |
#define SPR_BOOKE_TLB0CFG (0x2B0) |
1384 |
#define SPR_BOOKE_TLB1CFG (0x2B1) |
1385 |
#define SPR_BOOKE_TLB2CFG (0x2B2) |
1386 |
#define SPR_BOOKE_TLB3CFG (0x2B3) |
1387 |
#define SPR_BOOKE_EPR (0x2BE) |
1388 |
#define SPR_PERF0 (0x300) |
1389 |
#define SPR_RCPU_MI_RBA0 (0x300) |
1390 |
#define SPR_MPC_MI_CTR (0x300) |
1391 |
#define SPR_PERF1 (0x301) |
1392 |
#define SPR_RCPU_MI_RBA1 (0x301) |
1393 |
#define SPR_PERF2 (0x302) |
1394 |
#define SPR_RCPU_MI_RBA2 (0x302) |
1395 |
#define SPR_MPC_MI_AP (0x302) |
1396 |
#define SPR_PERF3 (0x303) |
1397 |
#define SPR_620_PMC1R (0x303) |
1398 |
#define SPR_RCPU_MI_RBA3 (0x303) |
1399 |
#define SPR_MPC_MI_EPN (0x303) |
1400 |
#define SPR_PERF4 (0x304) |
1401 |
#define SPR_620_PMC2R (0x304) |
1402 |
#define SPR_PERF5 (0x305) |
1403 |
#define SPR_MPC_MI_TWC (0x305) |
1404 |
#define SPR_PERF6 (0x306) |
1405 |
#define SPR_MPC_MI_RPN (0x306) |
1406 |
#define SPR_PERF7 (0x307) |
1407 |
#define SPR_PERF8 (0x308) |
1408 |
#define SPR_RCPU_L2U_RBA0 (0x308) |
1409 |
#define SPR_MPC_MD_CTR (0x308) |
1410 |
#define SPR_PERF9 (0x309) |
1411 |
#define SPR_RCPU_L2U_RBA1 (0x309) |
1412 |
#define SPR_MPC_MD_CASID (0x309) |
1413 |
#define SPR_PERFA (0x30A) |
1414 |
#define SPR_RCPU_L2U_RBA2 (0x30A) |
1415 |
#define SPR_MPC_MD_AP (0x30A) |
1416 |
#define SPR_PERFB (0x30B) |
1417 |
#define SPR_620_MMCR0R (0x30B) |
1418 |
#define SPR_RCPU_L2U_RBA3 (0x30B) |
1419 |
#define SPR_MPC_MD_EPN (0x30B) |
1420 |
#define SPR_PERFC (0x30C) |
1421 |
#define SPR_MPC_MD_TWB (0x30C) |
1422 |
#define SPR_PERFD (0x30D) |
1423 |
#define SPR_MPC_MD_TWC (0x30D) |
1424 |
#define SPR_PERFE (0x30E) |
1425 |
#define SPR_MPC_MD_RPN (0x30E) |
1426 |
#define SPR_PERFF (0x30F) |
1427 |
#define SPR_MPC_MD_TW (0x30F) |
1428 |
#define SPR_UPERF0 (0x310) |
1429 |
#define SPR_UPERF1 (0x311) |
1430 |
#define SPR_UPERF2 (0x312) |
1431 |
#define SPR_UPERF3 (0x313) |
1432 |
#define SPR_620_PMC1W (0x313) |
1433 |
#define SPR_UPERF4 (0x314) |
1434 |
#define SPR_620_PMC2W (0x314) |
1435 |
#define SPR_UPERF5 (0x315) |
1436 |
#define SPR_UPERF6 (0x316) |
1437 |
#define SPR_UPERF7 (0x317) |
1438 |
#define SPR_UPERF8 (0x318) |
1439 |
#define SPR_UPERF9 (0x319) |
1440 |
#define SPR_UPERFA (0x31A) |
1441 |
#define SPR_UPERFB (0x31B) |
1442 |
#define SPR_620_MMCR0W (0x31B) |
1443 |
#define SPR_UPERFC (0x31C) |
1444 |
#define SPR_UPERFD (0x31D) |
1445 |
#define SPR_UPERFE (0x31E) |
1446 |
#define SPR_UPERFF (0x31F) |
1447 |
#define SPR_RCPU_MI_RA0 (0x320) |
1448 |
#define SPR_MPC_MI_DBCAM (0x320) |
1449 |
#define SPR_RCPU_MI_RA1 (0x321) |
1450 |
#define SPR_MPC_MI_DBRAM0 (0x321) |
1451 |
#define SPR_RCPU_MI_RA2 (0x322) |
1452 |
#define SPR_MPC_MI_DBRAM1 (0x322) |
1453 |
#define SPR_RCPU_MI_RA3 (0x323) |
1454 |
#define SPR_RCPU_L2U_RA0 (0x328) |
1455 |
#define SPR_MPC_MD_DBCAM (0x328) |
1456 |
#define SPR_RCPU_L2U_RA1 (0x329) |
1457 |
#define SPR_MPC_MD_DBRAM0 (0x329) |
1458 |
#define SPR_RCPU_L2U_RA2 (0x32A) |
1459 |
#define SPR_MPC_MD_DBRAM1 (0x32A) |
1460 |
#define SPR_RCPU_L2U_RA3 (0x32B) |
1461 |
#define SPR_440_INV0 (0x370) |
1462 |
#define SPR_440_INV1 (0x371) |
1463 |
#define SPR_440_INV2 (0x372) |
1464 |
#define SPR_440_INV3 (0x373) |
1465 |
#define SPR_440_ITV0 (0x374) |
1466 |
#define SPR_440_ITV1 (0x375) |
1467 |
#define SPR_440_ITV2 (0x376) |
1468 |
#define SPR_440_ITV3 (0x377) |
1469 |
#define SPR_440_CCR1 (0x378) |
1470 |
#define SPR_DCRIPR (0x37B) |
1471 |
#define SPR_PPR (0x380) |
1472 |
#define SPR_750_GQR0 (0x390) |
1473 |
#define SPR_440_DNV0 (0x390) |
1474 |
#define SPR_750_GQR1 (0x391) |
1475 |
#define SPR_440_DNV1 (0x391) |
1476 |
#define SPR_750_GQR2 (0x392) |
1477 |
#define SPR_440_DNV2 (0x392) |
1478 |
#define SPR_750_GQR3 (0x393) |
1479 |
#define SPR_440_DNV3 (0x393) |
1480 |
#define SPR_750_GQR4 (0x394) |
1481 |
#define SPR_440_DTV0 (0x394) |
1482 |
#define SPR_750_GQR5 (0x395) |
1483 |
#define SPR_440_DTV1 (0x395) |
1484 |
#define SPR_750_GQR6 (0x396) |
1485 |
#define SPR_440_DTV2 (0x396) |
1486 |
#define SPR_750_GQR7 (0x397) |
1487 |
#define SPR_440_DTV3 (0x397) |
1488 |
#define SPR_750_THRM4 (0x398) |
1489 |
#define SPR_750CL_HID2 (0x398) |
1490 |
#define SPR_440_DVLIM (0x398) |
1491 |
#define SPR_750_WPAR (0x399) |
1492 |
#define SPR_440_IVLIM (0x399) |
1493 |
#define SPR_750_DMAU (0x39A) |
1494 |
#define SPR_750_DMAL (0x39B) |
1495 |
#define SPR_440_RSTCFG (0x39B) |
1496 |
#define SPR_BOOKE_DCDBTRL (0x39C) |
1497 |
#define SPR_BOOKE_DCDBTRH (0x39D) |
1498 |
#define SPR_BOOKE_ICDBTRL (0x39E) |
1499 |
#define SPR_BOOKE_ICDBTRH (0x39F) |
1500 |
#define SPR_UMMCR2 (0x3A0) |
1501 |
#define SPR_UPMC5 (0x3A1) |
1502 |
#define SPR_UPMC6 (0x3A2) |
1503 |
#define SPR_UBAMR (0x3A7) |
1504 |
#define SPR_UMMCR0 (0x3A8) |
1505 |
#define SPR_UPMC1 (0x3A9) |
1506 |
#define SPR_UPMC2 (0x3AA) |
1507 |
#define SPR_USIAR (0x3AB) |
1508 |
#define SPR_UMMCR1 (0x3AC) |
1509 |
#define SPR_UPMC3 (0x3AD) |
1510 |
#define SPR_UPMC4 (0x3AE) |
1511 |
#define SPR_USDA (0x3AF) |
1512 |
#define SPR_40x_ZPR (0x3B0) |
1513 |
#define SPR_BOOKE_MAS7 (0x3B0) |
1514 |
#define SPR_620_PMR0 (0x3B0) |
1515 |
#define SPR_MMCR2 (0x3B0) |
1516 |
#define SPR_PMC5 (0x3B1) |
1517 |
#define SPR_40x_PID (0x3B1) |
1518 |
#define SPR_620_PMR1 (0x3B1) |
1519 |
#define SPR_PMC6 (0x3B2) |
1520 |
#define SPR_440_MMUCR (0x3B2) |
1521 |
#define SPR_620_PMR2 (0x3B2) |
1522 |
#define SPR_4xx_CCR0 (0x3B3) |
1523 |
#define SPR_BOOKE_EPLC (0x3B3) |
1524 |
#define SPR_620_PMR3 (0x3B3) |
1525 |
#define SPR_405_IAC3 (0x3B4) |
1526 |
#define SPR_BOOKE_EPSC (0x3B4) |
1527 |
#define SPR_620_PMR4 (0x3B4) |
1528 |
#define SPR_405_IAC4 (0x3B5) |
1529 |
#define SPR_620_PMR5 (0x3B5) |
1530 |
#define SPR_405_DVC1 (0x3B6) |
1531 |
#define SPR_620_PMR6 (0x3B6) |
1532 |
#define SPR_405_DVC2 (0x3B7) |
1533 |
#define SPR_620_PMR7 (0x3B7) |
1534 |
#define SPR_BAMR (0x3B7) |
1535 |
#define SPR_MMCR0 (0x3B8) |
1536 |
#define SPR_620_PMR8 (0x3B8) |
1537 |
#define SPR_PMC1 (0x3B9) |
1538 |
#define SPR_40x_SGR (0x3B9) |
1539 |
#define SPR_620_PMR9 (0x3B9) |
1540 |
#define SPR_PMC2 (0x3BA) |
1541 |
#define SPR_40x_DCWR (0x3BA) |
1542 |
#define SPR_620_PMRA (0x3BA) |
1543 |
#define SPR_SIAR (0x3BB) |
1544 |
#define SPR_405_SLER (0x3BB) |
1545 |
#define SPR_620_PMRB (0x3BB) |
1546 |
#define SPR_MMCR1 (0x3BC) |
1547 |
#define SPR_405_SU0R (0x3BC) |
1548 |
#define SPR_620_PMRC (0x3BC) |
1549 |
#define SPR_401_SKR (0x3BC) |
1550 |
#define SPR_PMC3 (0x3BD) |
1551 |
#define SPR_405_DBCR1 (0x3BD) |
1552 |
#define SPR_620_PMRD (0x3BD) |
1553 |
#define SPR_PMC4 (0x3BE) |
1554 |
#define SPR_620_PMRE (0x3BE) |
1555 |
#define SPR_SDA (0x3BF) |
1556 |
#define SPR_620_PMRF (0x3BF) |
1557 |
#define SPR_403_VTBL (0x3CC) |
1558 |
#define SPR_403_VTBU (0x3CD) |
1559 |
#define SPR_DMISS (0x3D0) |
1560 |
#define SPR_DCMP (0x3D1) |
1561 |
#define SPR_HASH1 (0x3D2) |
1562 |
#define SPR_HASH2 (0x3D3) |
1563 |
#define SPR_BOOKE_ICDBDR (0x3D3) |
1564 |
#define SPR_TLBMISS (0x3D4) |
1565 |
#define SPR_IMISS (0x3D4) |
1566 |
#define SPR_40x_ESR (0x3D4) |
1567 |
#define SPR_PTEHI (0x3D5) |
1568 |
#define SPR_ICMP (0x3D5) |
1569 |
#define SPR_40x_DEAR (0x3D5) |
1570 |
#define SPR_PTELO (0x3D6) |
1571 |
#define SPR_RPA (0x3D6) |
1572 |
#define SPR_40x_EVPR (0x3D6) |
1573 |
#define SPR_L3PM (0x3D7) |
1574 |
#define SPR_403_CDBCR (0x3D7) |
1575 |
#define SPR_L3ITCR0 (0x3D8) |
1576 |
#define SPR_TCR (0x3D8) |
1577 |
#define SPR_40x_TSR (0x3D8) |
1578 |
#define SPR_IBR (0x3DA) |
1579 |
#define SPR_40x_TCR (0x3DA) |
1580 |
#define SPR_ESASRR (0x3DB) |
1581 |
#define SPR_40x_PIT (0x3DB) |
1582 |
#define SPR_403_TBL (0x3DC) |
1583 |
#define SPR_403_TBU (0x3DD) |
1584 |
#define SPR_SEBR (0x3DE) |
1585 |
#define SPR_40x_SRR2 (0x3DE) |
1586 |
#define SPR_SER (0x3DF) |
1587 |
#define SPR_40x_SRR3 (0x3DF) |
1588 |
#define SPR_L3OHCR (0x3E8) |
1589 |
#define SPR_L3ITCR1 (0x3E9) |
1590 |
#define SPR_L3ITCR2 (0x3EA) |
1591 |
#define SPR_L3ITCR3 (0x3EB) |
1592 |
#define SPR_HID0 (0x3F0) |
1593 |
#define SPR_40x_DBSR (0x3F0) |
1594 |
#define SPR_HID1 (0x3F1) |
1595 |
#define SPR_IABR (0x3F2) |
1596 |
#define SPR_40x_DBCR0 (0x3F2) |
1597 |
#define SPR_601_HID2 (0x3F2) |
1598 |
#define SPR_Exxx_L1CSR0 (0x3F2) |
1599 |
#define SPR_ICTRL (0x3F3) |
1600 |
#define SPR_HID2 (0x3F3) |
1601 |
#define SPR_750CL_HID4 (0x3F3) |
1602 |
#define SPR_Exxx_L1CSR1 (0x3F3) |
1603 |
#define SPR_440_DBDR (0x3F3) |
1604 |
#define SPR_LDSTDB (0x3F4) |
1605 |
#define SPR_750_TDCL (0x3F4) |
1606 |
#define SPR_40x_IAC1 (0x3F4) |
1607 |
#define SPR_MMUCSR0 (0x3F4) |
1608 |
#define SPR_DABR (0x3F5) |
1609 |
#define DABR_MASK (~(target_ulong)0x7) |
1610 |
#define SPR_Exxx_BUCSR (0x3F5) |
1611 |
#define SPR_40x_IAC2 (0x3F5) |
1612 |
#define SPR_601_HID5 (0x3F5) |
1613 |
#define SPR_40x_DAC1 (0x3F6) |
1614 |
#define SPR_MSSCR0 (0x3F6) |
1615 |
#define SPR_970_HID5 (0x3F6) |
1616 |
#define SPR_MSSSR0 (0x3F7) |
1617 |
#define SPR_MSSCR1 (0x3F7) |
1618 |
#define SPR_DABRX (0x3F7) |
1619 |
#define SPR_40x_DAC2 (0x3F7) |
1620 |
#define SPR_MMUCFG (0x3F7) |
1621 |
#define SPR_LDSTCR (0x3F8) |
1622 |
#define SPR_L2PMCR (0x3F8) |
1623 |
#define SPR_750FX_HID2 (0x3F8) |
1624 |
#define SPR_620_BUSCSR (0x3F8) |
1625 |
#define SPR_Exxx_L1FINV0 (0x3F8) |
1626 |
#define SPR_L2CR (0x3F9) |
1627 |
#define SPR_620_L2CR (0x3F9) |
1628 |
#define SPR_L3CR (0x3FA) |
1629 |
#define SPR_750_TDCH (0x3FA) |
1630 |
#define SPR_IABR2 (0x3FA) |
1631 |
#define SPR_40x_DCCR (0x3FA) |
1632 |
#define SPR_620_L2SR (0x3FA) |
1633 |
#define SPR_ICTC (0x3FB) |
1634 |
#define SPR_40x_ICCR (0x3FB) |
1635 |
#define SPR_THRM1 (0x3FC) |
1636 |
#define SPR_403_PBL1 (0x3FC) |
1637 |
#define SPR_SP (0x3FD) |
1638 |
#define SPR_THRM2 (0x3FD) |
1639 |
#define SPR_403_PBU1 (0x3FD) |
1640 |
#define SPR_604_HID13 (0x3FD) |
1641 |
#define SPR_LT (0x3FE) |
1642 |
#define SPR_THRM3 (0x3FE) |
1643 |
#define SPR_RCPU_FPECR (0x3FE) |
1644 |
#define SPR_403_PBL2 (0x3FE) |
1645 |
#define SPR_PIR (0x3FF) |
1646 |
#define SPR_403_PBU2 (0x3FF) |
1647 |
#define SPR_601_HID15 (0x3FF) |
1648 |
#define SPR_604_HID15 (0x3FF) |
1649 |
#define SPR_E500_SVR (0x3FF) |
1650 |
|
1651 |
/*****************************************************************************/
|
1652 |
/* PowerPC Instructions types definitions */
|
1653 |
enum {
|
1654 |
PPC_NONE = 0x0000000000000000ULL,
|
1655 |
/* PowerPC base instructions set */
|
1656 |
PPC_INSNS_BASE = 0x0000000000000001ULL,
|
1657 |
/* integer operations instructions */
|
1658 |
#define PPC_INTEGER PPC_INSNS_BASE
|
1659 |
/* flow control instructions */
|
1660 |
#define PPC_FLOW PPC_INSNS_BASE
|
1661 |
/* virtual memory instructions */
|
1662 |
#define PPC_MEM PPC_INSNS_BASE
|
1663 |
/* ld/st with reservation instructions */
|
1664 |
#define PPC_RES PPC_INSNS_BASE
|
1665 |
/* spr/msr access instructions */
|
1666 |
#define PPC_MISC PPC_INSNS_BASE
|
1667 |
/* Deprecated instruction sets */
|
1668 |
/* Original POWER instruction set */
|
1669 |
PPC_POWER = 0x0000000000000002ULL,
|
1670 |
/* POWER2 instruction set extension */
|
1671 |
PPC_POWER2 = 0x0000000000000004ULL,
|
1672 |
/* Power RTC support */
|
1673 |
PPC_POWER_RTC = 0x0000000000000008ULL,
|
1674 |
/* Power-to-PowerPC bridge (601) */
|
1675 |
PPC_POWER_BR = 0x0000000000000010ULL,
|
1676 |
/* 64 bits PowerPC instruction set */
|
1677 |
PPC_64B = 0x0000000000000020ULL,
|
1678 |
/* New 64 bits extensions (PowerPC 2.0x) */
|
1679 |
PPC_64BX = 0x0000000000000040ULL,
|
1680 |
/* 64 bits hypervisor extensions */
|
1681 |
PPC_64H = 0x0000000000000080ULL,
|
1682 |
/* New wait instruction (PowerPC 2.0x) */
|
1683 |
PPC_WAIT = 0x0000000000000100ULL,
|
1684 |
/* Time base mftb instruction */
|
1685 |
PPC_MFTB = 0x0000000000000200ULL,
|
1686 |
|
1687 |
/* Fixed-point unit extensions */
|
1688 |
/* PowerPC 602 specific */
|
1689 |
PPC_602_SPEC = 0x0000000000000400ULL,
|
1690 |
/* isel instruction */
|
1691 |
PPC_ISEL = 0x0000000000000800ULL,
|
1692 |
/* popcntb instruction */
|
1693 |
PPC_POPCNTB = 0x0000000000001000ULL,
|
1694 |
/* string load / store */
|
1695 |
PPC_STRING = 0x0000000000002000ULL,
|
1696 |
|
1697 |
/* Floating-point unit extensions */
|
1698 |
/* Optional floating point instructions */
|
1699 |
PPC_FLOAT = 0x0000000000010000ULL,
|
1700 |
/* New floating-point extensions (PowerPC 2.0x) */
|
1701 |
PPC_FLOAT_EXT = 0x0000000000020000ULL,
|
1702 |
PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
|
1703 |
PPC_FLOAT_FRES = 0x0000000000080000ULL,
|
1704 |
PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
|
1705 |
PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
|
1706 |
PPC_FLOAT_FSEL = 0x0000000000400000ULL,
|
1707 |
PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
|
1708 |
|
1709 |
/* Vector/SIMD extensions */
|
1710 |
/* Altivec support */
|
1711 |
PPC_ALTIVEC = 0x0000000001000000ULL,
|
1712 |
/* PowerPC 2.03 SPE extension */
|
1713 |
PPC_SPE = 0x0000000002000000ULL,
|
1714 |
/* PowerPC 2.03 SPE single-precision floating-point extension */
|
1715 |
PPC_SPE_SINGLE = 0x0000000004000000ULL,
|
1716 |
/* PowerPC 2.03 SPE double-precision floating-point extension */
|
1717 |
PPC_SPE_DOUBLE = 0x0000000008000000ULL,
|
1718 |
|
1719 |
/* Optional memory control instructions */
|
1720 |
PPC_MEM_TLBIA = 0x0000000010000000ULL,
|
1721 |
PPC_MEM_TLBIE = 0x0000000020000000ULL,
|
1722 |
PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
|
1723 |
/* sync instruction */
|
1724 |
PPC_MEM_SYNC = 0x0000000080000000ULL,
|
1725 |
/* eieio instruction */
|
1726 |
PPC_MEM_EIEIO = 0x0000000100000000ULL,
|
1727 |
|
1728 |
/* Cache control instructions */
|
1729 |
PPC_CACHE = 0x0000000200000000ULL,
|
1730 |
/* icbi instruction */
|
1731 |
PPC_CACHE_ICBI = 0x0000000400000000ULL,
|
1732 |
/* dcbz instruction with fixed cache line size */
|
1733 |
PPC_CACHE_DCBZ = 0x0000000800000000ULL,
|
1734 |
/* dcbz instruction with tunable cache line size */
|
1735 |
PPC_CACHE_DCBZT = 0x0000001000000000ULL,
|
1736 |
/* dcba instruction */
|
1737 |
PPC_CACHE_DCBA = 0x0000002000000000ULL,
|
1738 |
/* Freescale cache locking instructions */
|
1739 |
PPC_CACHE_LOCK = 0x0000004000000000ULL,
|
1740 |
|
1741 |
/* MMU related extensions */
|
1742 |
/* external control instructions */
|
1743 |
PPC_EXTERN = 0x0000010000000000ULL,
|
1744 |
/* segment register access instructions */
|
1745 |
PPC_SEGMENT = 0x0000020000000000ULL,
|
1746 |
/* PowerPC 6xx TLB management instructions */
|
1747 |
PPC_6xx_TLB = 0x0000040000000000ULL,
|
1748 |
/* PowerPC 74xx TLB management instructions */
|
1749 |
PPC_74xx_TLB = 0x0000080000000000ULL,
|
1750 |
/* PowerPC 40x TLB management instructions */
|
1751 |
PPC_40x_TLB = 0x0000100000000000ULL,
|
1752 |
/* segment register access instructions for PowerPC 64 "bridge" */
|
1753 |
PPC_SEGMENT_64B = 0x0000200000000000ULL,
|
1754 |
/* SLB management */
|
1755 |
PPC_SLBI = 0x0000400000000000ULL,
|
1756 |
|
1757 |
/* Embedded PowerPC dedicated instructions */
|
1758 |
PPC_WRTEE = 0x0001000000000000ULL,
|
1759 |
/* PowerPC 40x exception model */
|
1760 |
PPC_40x_EXCP = 0x0002000000000000ULL,
|
1761 |
/* PowerPC 405 Mac instructions */
|
1762 |
PPC_405_MAC = 0x0004000000000000ULL,
|
1763 |
/* PowerPC 440 specific instructions */
|
1764 |
PPC_440_SPEC = 0x0008000000000000ULL,
|
1765 |
/* BookE (embedded) PowerPC specification */
|
1766 |
PPC_BOOKE = 0x0010000000000000ULL,
|
1767 |
/* mfapidi instruction */
|
1768 |
PPC_MFAPIDI = 0x0020000000000000ULL,
|
1769 |
/* tlbiva instruction */
|
1770 |
PPC_TLBIVA = 0x0040000000000000ULL,
|
1771 |
/* tlbivax instruction */
|
1772 |
PPC_TLBIVAX = 0x0080000000000000ULL,
|
1773 |
/* PowerPC 4xx dedicated instructions */
|
1774 |
PPC_4xx_COMMON = 0x0100000000000000ULL,
|
1775 |
/* PowerPC 40x ibct instructions */
|
1776 |
PPC_40x_ICBT = 0x0200000000000000ULL,
|
1777 |
/* rfmci is not implemented in all BookE PowerPC */
|
1778 |
PPC_RFMCI = 0x0400000000000000ULL,
|
1779 |
/* rfdi instruction */
|
1780 |
PPC_RFDI = 0x0800000000000000ULL,
|
1781 |
/* DCR accesses */
|
1782 |
PPC_DCR = 0x1000000000000000ULL,
|
1783 |
/* DCR extended accesse */
|
1784 |
PPC_DCRX = 0x2000000000000000ULL,
|
1785 |
/* user-mode DCR access, implemented in PowerPC 460 */
|
1786 |
PPC_DCRUX = 0x4000000000000000ULL,
|
1787 |
/* popcntw and popcntd instructions */
|
1788 |
PPC_POPCNTWD = 0x8000000000000000ULL,
|
1789 |
|
1790 |
/* extended type values */
|
1791 |
|
1792 |
/* BookE 2.06 PowerPC specification */
|
1793 |
PPC2_BOOKE206 = 0x0000000000000001ULL,
|
1794 |
}; |
1795 |
|
1796 |
/*****************************************************************************/
|
1797 |
/* Memory access type :
|
1798 |
* may be needed for precise access rights control and precise exceptions.
|
1799 |
*/
|
1800 |
enum {
|
1801 |
/* 1 bit to define user level / supervisor access */
|
1802 |
ACCESS_USER = 0x00,
|
1803 |
ACCESS_SUPER = 0x01,
|
1804 |
/* Type of instruction that generated the access */
|
1805 |
ACCESS_CODE = 0x10, /* Code fetch access */ |
1806 |
ACCESS_INT = 0x20, /* Integer load/store access */ |
1807 |
ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
1808 |
ACCESS_RES = 0x40, /* load/store with reservation */ |
1809 |
ACCESS_EXT = 0x50, /* external access */ |
1810 |
ACCESS_CACHE = 0x60, /* Cache manipulation */ |
1811 |
}; |
1812 |
|
1813 |
/* Hardware interruption sources:
|
1814 |
* all those exception can be raised simulteaneously
|
1815 |
*/
|
1816 |
/* Input pins definitions */
|
1817 |
enum {
|
1818 |
/* 6xx bus input pins */
|
1819 |
PPC6xx_INPUT_HRESET = 0,
|
1820 |
PPC6xx_INPUT_SRESET = 1,
|
1821 |
PPC6xx_INPUT_CKSTP_IN = 2,
|
1822 |
PPC6xx_INPUT_MCP = 3,
|
1823 |
PPC6xx_INPUT_SMI = 4,
|
1824 |
PPC6xx_INPUT_INT = 5,
|
1825 |
PPC6xx_INPUT_TBEN = 6,
|
1826 |
PPC6xx_INPUT_WAKEUP = 7,
|
1827 |
PPC6xx_INPUT_NB, |
1828 |
}; |
1829 |
|
1830 |
enum {
|
1831 |
/* Embedded PowerPC input pins */
|
1832 |
PPCBookE_INPUT_HRESET = 0,
|
1833 |
PPCBookE_INPUT_SRESET = 1,
|
1834 |
PPCBookE_INPUT_CKSTP_IN = 2,
|
1835 |
PPCBookE_INPUT_MCP = 3,
|
1836 |
PPCBookE_INPUT_SMI = 4,
|
1837 |
PPCBookE_INPUT_INT = 5,
|
1838 |
PPCBookE_INPUT_CINT = 6,
|
1839 |
PPCBookE_INPUT_NB, |
1840 |
}; |
1841 |
|
1842 |
enum {
|
1843 |
/* PowerPC E500 input pins */
|
1844 |
PPCE500_INPUT_RESET_CORE = 0,
|
1845 |
PPCE500_INPUT_MCK = 1,
|
1846 |
PPCE500_INPUT_CINT = 3,
|
1847 |
PPCE500_INPUT_INT = 4,
|
1848 |
PPCE500_INPUT_DEBUG = 6,
|
1849 |
PPCE500_INPUT_NB, |
1850 |
}; |
1851 |
|
1852 |
enum {
|
1853 |
/* PowerPC 40x input pins */
|
1854 |
PPC40x_INPUT_RESET_CORE = 0,
|
1855 |
PPC40x_INPUT_RESET_CHIP = 1,
|
1856 |
PPC40x_INPUT_RESET_SYS = 2,
|
1857 |
PPC40x_INPUT_CINT = 3,
|
1858 |
PPC40x_INPUT_INT = 4,
|
1859 |
PPC40x_INPUT_HALT = 5,
|
1860 |
PPC40x_INPUT_DEBUG = 6,
|
1861 |
PPC40x_INPUT_NB, |
1862 |
}; |
1863 |
|
1864 |
enum {
|
1865 |
/* RCPU input pins */
|
1866 |
PPCRCPU_INPUT_PORESET = 0,
|
1867 |
PPCRCPU_INPUT_HRESET = 1,
|
1868 |
PPCRCPU_INPUT_SRESET = 2,
|
1869 |
PPCRCPU_INPUT_IRQ0 = 3,
|
1870 |
PPCRCPU_INPUT_IRQ1 = 4,
|
1871 |
PPCRCPU_INPUT_IRQ2 = 5,
|
1872 |
PPCRCPU_INPUT_IRQ3 = 6,
|
1873 |
PPCRCPU_INPUT_IRQ4 = 7,
|
1874 |
PPCRCPU_INPUT_IRQ5 = 8,
|
1875 |
PPCRCPU_INPUT_IRQ6 = 9,
|
1876 |
PPCRCPU_INPUT_IRQ7 = 10,
|
1877 |
PPCRCPU_INPUT_NB, |
1878 |
}; |
1879 |
|
1880 |
#if defined(TARGET_PPC64)
|
1881 |
enum {
|
1882 |
/* PowerPC 970 input pins */
|
1883 |
PPC970_INPUT_HRESET = 0,
|
1884 |
PPC970_INPUT_SRESET = 1,
|
1885 |
PPC970_INPUT_CKSTP = 2,
|
1886 |
PPC970_INPUT_TBEN = 3,
|
1887 |
PPC970_INPUT_MCP = 4,
|
1888 |
PPC970_INPUT_INT = 5,
|
1889 |
PPC970_INPUT_THINT = 6,
|
1890 |
PPC970_INPUT_NB, |
1891 |
}; |
1892 |
|
1893 |
enum {
|
1894 |
/* POWER7 input pins */
|
1895 |
POWER7_INPUT_INT = 0,
|
1896 |
/* POWER7 probably has other inputs, but we don't care about them
|
1897 |
* for any existing machine. We can wire these up when we need
|
1898 |
* them */
|
1899 |
POWER7_INPUT_NB, |
1900 |
}; |
1901 |
#endif
|
1902 |
|
1903 |
/* Hardware exceptions definitions */
|
1904 |
enum {
|
1905 |
/* External hardware exception sources */
|
1906 |
PPC_INTERRUPT_RESET = 0, /* Reset exception */ |
1907 |
PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
|
1908 |
PPC_INTERRUPT_MCK, /* Machine check exception */
|
1909 |
PPC_INTERRUPT_EXT, /* External interrupt */
|
1910 |
PPC_INTERRUPT_SMI, /* System management interrupt */
|
1911 |
PPC_INTERRUPT_CEXT, /* Critical external interrupt */
|
1912 |
PPC_INTERRUPT_DEBUG, /* External debug exception */
|
1913 |
PPC_INTERRUPT_THERM, /* Thermal exception */
|
1914 |
/* Internal hardware exception sources */
|
1915 |
PPC_INTERRUPT_DECR, /* Decrementer exception */
|
1916 |
PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
|
1917 |
PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
|
1918 |
PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
|
1919 |
PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
|
1920 |
PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
|
1921 |
PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
|
1922 |
PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
|
1923 |
}; |
1924 |
|
1925 |
/*****************************************************************************/
|
1926 |
|
1927 |
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
1928 |
target_ulong *cs_base, int *flags)
|
1929 |
{ |
1930 |
*pc = env->nip; |
1931 |
*cs_base = 0;
|
1932 |
*flags = env->hflags; |
1933 |
} |
1934 |
|
1935 |
static inline void cpu_set_tls(CPUState *env, target_ulong newtls) |
1936 |
{ |
1937 |
#if defined(TARGET_PPC64)
|
1938 |
/* The kernel checks TIF_32BIT here; we don't support loading 32-bit
|
1939 |
binaries on PPC64 yet. */
|
1940 |
env->gpr[13] = newtls;
|
1941 |
#else
|
1942 |
env->gpr[2] = newtls;
|
1943 |
#endif
|
1944 |
} |
1945 |
|
1946 |
#if !defined(CONFIG_USER_ONLY)
|
1947 |
static inline int booke206_tlbm_id(CPUState *env, ppcmas_tlb_t *tlbm) |
1948 |
{ |
1949 |
uintptr_t tlbml = (uintptr_t)tlbm; |
1950 |
uintptr_t tlbl = (uintptr_t)env->tlb.tlbm; |
1951 |
|
1952 |
return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]); |
1953 |
} |
1954 |
|
1955 |
static inline int booke206_tlb_size(CPUState *env, int tlbn) |
1956 |
{ |
1957 |
uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; |
1958 |
int r = tlbncfg & TLBnCFG_N_ENTRY;
|
1959 |
return r;
|
1960 |
} |
1961 |
|
1962 |
static inline int booke206_tlb_ways(CPUState *env, int tlbn) |
1963 |
{ |
1964 |
uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; |
1965 |
int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
|
1966 |
return r;
|
1967 |
} |
1968 |
|
1969 |
static inline int booke206_tlbm_to_tlbn(CPUState *env, ppcmas_tlb_t *tlbm) |
1970 |
{ |
1971 |
int id = booke206_tlbm_id(env, tlbm);
|
1972 |
int end = 0; |
1973 |
int i;
|
1974 |
|
1975 |
for (i = 0; i < BOOKE206_MAX_TLBN; i++) { |
1976 |
end += booke206_tlb_size(env, i); |
1977 |
if (id < end) {
|
1978 |
return i;
|
1979 |
} |
1980 |
} |
1981 |
|
1982 |
cpu_abort(env, "Unknown TLBe: %d\n", id);
|
1983 |
return 0; |
1984 |
} |
1985 |
|
1986 |
static inline int booke206_tlbm_to_way(CPUState *env, ppcmas_tlb_t *tlb) |
1987 |
{ |
1988 |
int tlbn = booke206_tlbm_to_tlbn(env, tlb);
|
1989 |
int tlbid = booke206_tlbm_id(env, tlb);
|
1990 |
return tlbid & (booke206_tlb_ways(env, tlbn) - 1); |
1991 |
} |
1992 |
|
1993 |
static inline ppcmas_tlb_t *booke206_get_tlbm(CPUState *env, const int tlbn, |
1994 |
target_ulong ea, int way)
|
1995 |
{ |
1996 |
int r;
|
1997 |
uint32_t ways = booke206_tlb_ways(env, tlbn); |
1998 |
int ways_bits = ffs(ways) - 1; |
1999 |
int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1; |
2000 |
int i;
|
2001 |
|
2002 |
way &= ways - 1;
|
2003 |
ea >>= MAS2_EPN_SHIFT; |
2004 |
ea &= (1 << (tlb_bits - ways_bits)) - 1; |
2005 |
r = (ea << ways_bits) | way; |
2006 |
|
2007 |
/* bump up to tlbn index */
|
2008 |
for (i = 0; i < tlbn; i++) { |
2009 |
r += booke206_tlb_size(env, i); |
2010 |
} |
2011 |
|
2012 |
return &env->tlb.tlbm[r];
|
2013 |
} |
2014 |
|
2015 |
#endif
|
2016 |
|
2017 |
extern void (*cpu_ppc_hypercall)(CPUState *); |
2018 |
|
2019 |
static inline bool cpu_has_work(CPUState *env) |
2020 |
{ |
2021 |
return msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD);
|
2022 |
} |
2023 |
|
2024 |
#include "exec-all.h" |
2025 |
|
2026 |
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
2027 |
{ |
2028 |
env->nip = tb->pc; |
2029 |
} |
2030 |
|
2031 |
#endif /* !defined (__CPU_PPC_H__) */ |