Revision f6548c0a tcg/ppc64/tcg-target.c
| b/tcg/ppc64/tcg-target.c | ||
|---|---|---|
| 42 | 42 |
#define CMP_L (1<<21) |
| 43 | 43 |
#endif |
| 44 | 44 |
|
| 45 |
#ifndef GUEST_BASE |
|
| 46 |
#define GUEST_BASE 0 |
|
| 47 |
#endif |
|
| 48 |
|
|
| 49 |
#ifdef CONFIG_USE_GUEST_BASE |
|
| 50 |
#define TCG_GUEST_BASE_REG 30 |
|
| 51 |
#else |
|
| 52 |
#define TCG_GUEST_BASE_REG 0 |
|
| 53 |
#endif |
|
| 54 |
|
|
| 45 | 55 |
#ifndef NDEBUG |
| 46 | 56 |
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
|
| 47 | 57 |
"r0", |
| ... | ... | |
| 588 | 598 |
|
| 589 | 599 |
static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc) |
| 590 | 600 |
{
|
| 591 |
int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap; |
|
| 601 |
int addr_reg, data_reg, r0, r1, rbase, mem_index, s_bits, bswap;
|
|
| 592 | 602 |
#ifdef CONFIG_SOFTMMU |
| 593 | 603 |
int r2; |
| 594 | 604 |
void *label1_ptr, *label2_ptr; |
| ... | ... | |
| 603 | 613 |
r0 = 3; |
| 604 | 614 |
r1 = 4; |
| 605 | 615 |
r2 = 0; |
| 616 |
rbase = 0; |
|
| 606 | 617 |
|
| 607 | 618 |
tcg_out_tlb_read (s, r0, r1, r2, addr_reg, s_bits, |
| 608 | 619 |
offsetof (CPUState, tlb_table[mem_index][0].addr_read)); |
| ... | ... | |
| 663 | 674 |
#endif |
| 664 | 675 |
r0 = addr_reg; |
| 665 | 676 |
r1 = 3; |
| 677 |
rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0; |
|
| 666 | 678 |
#endif |
| 667 | 679 |
|
| 668 | 680 |
#ifdef TARGET_WORDS_BIGENDIAN |
| ... | ... | |
| 673 | 685 |
switch (opc) {
|
| 674 | 686 |
default: |
| 675 | 687 |
case 0: |
| 676 |
tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
|
|
| 688 |
tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
|
|
| 677 | 689 |
break; |
| 678 | 690 |
case 0|4: |
| 679 |
tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
|
|
| 691 |
tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
|
|
| 680 | 692 |
tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg)); |
| 681 | 693 |
break; |
| 682 | 694 |
case 1: |
| 683 |
if (bswap) tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0)); |
|
| 684 |
else tcg_out32 (s, LHZ | RT (data_reg) | RA (r0)); |
|
| 695 |
if (bswap) |
|
| 696 |
tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0)); |
|
| 697 |
else |
|
| 698 |
tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0)); |
|
| 685 | 699 |
break; |
| 686 | 700 |
case 1|4: |
| 687 | 701 |
if (bswap) {
|
| 688 |
tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
|
|
| 702 |
tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
|
|
| 689 | 703 |
tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg)); |
| 690 | 704 |
} |
| 691 |
else tcg_out32 (s, LHA | RT (data_reg) | RA (r0));
|
|
| 705 |
else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
|
|
| 692 | 706 |
break; |
| 693 | 707 |
case 2: |
| 694 |
if (bswap) tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0)); |
|
| 695 |
else tcg_out32 (s, LWZ | RT (data_reg)| RA (r0)); |
|
| 708 |
if (bswap) |
|
| 709 |
tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0)); |
|
| 710 |
else |
|
| 711 |
tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0)); |
|
| 696 | 712 |
break; |
| 697 | 713 |
case 2|4: |
| 698 | 714 |
if (bswap) {
|
| 699 |
tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
|
|
| 715 |
tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
|
|
| 700 | 716 |
tcg_out32 (s, EXTSW | RA (data_reg) | RS (data_reg)); |
| 701 | 717 |
} |
| 702 |
else tcg_out32 (s, LWA | RT (data_reg)| RA (r0));
|
|
| 718 |
else tcg_out32 (s, LWAX | TAB (data_reg, rbase, r0));
|
|
| 703 | 719 |
break; |
| 704 | 720 |
case 3: |
| 721 |
#ifdef CONFIG_USE_GUEST_BASE |
|
| 722 |
if (bswap) {
|
|
| 723 |
tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4); |
|
| 724 |
tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0)); |
|
| 725 |
tcg_out32 (s, LWBRX | TAB ( r1, rbase, r1)); |
|
| 726 |
tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0); |
|
| 727 |
} |
|
| 728 |
else tcg_out32 (s, LDX | TAB (data_reg, rbase, r0)); |
|
| 729 |
#else |
|
| 705 | 730 |
if (bswap) {
|
| 706 | 731 |
tcg_out_movi32 (s, 0, 4); |
| 707 | 732 |
tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0)); |
| ... | ... | |
| 709 | 734 |
tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0); |
| 710 | 735 |
} |
| 711 | 736 |
else tcg_out32 (s, LD | RT (data_reg) | RA (r0)); |
| 737 |
#endif |
|
| 712 | 738 |
break; |
| 713 | 739 |
} |
| 714 | 740 |
|
| ... | ... | |
| 719 | 745 |
|
| 720 | 746 |
static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) |
| 721 | 747 |
{
|
| 722 |
int addr_reg, r0, r1, data_reg, mem_index, bswap; |
|
| 748 |
int addr_reg, r0, r1, rbase, data_reg, mem_index, bswap;
|
|
| 723 | 749 |
#ifdef CONFIG_SOFTMMU |
| 724 | 750 |
int r2; |
| 725 | 751 |
void *label1_ptr, *label2_ptr; |
| ... | ... | |
| 733 | 759 |
r0 = 3; |
| 734 | 760 |
r1 = 4; |
| 735 | 761 |
r2 = 0; |
| 762 |
rbase = 0; |
|
| 736 | 763 |
|
| 737 | 764 |
tcg_out_tlb_read (s, r0, r1, r2, addr_reg, opc, |
| 738 | 765 |
offsetof (CPUState, tlb_table[mem_index][0].addr_write)); |
| ... | ... | |
| 775 | 802 |
#endif |
| 776 | 803 |
r1 = 3; |
| 777 | 804 |
r0 = addr_reg; |
| 805 |
rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0; |
|
| 778 | 806 |
#endif |
| 779 | 807 |
|
| 780 | 808 |
#ifdef TARGET_WORDS_BIGENDIAN |
| ... | ... | |
| 784 | 812 |
#endif |
| 785 | 813 |
switch (opc) {
|
| 786 | 814 |
case 0: |
| 787 |
tcg_out32 (s, STB | RS (data_reg) | RA (r0));
|
|
| 815 |
tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
|
|
| 788 | 816 |
break; |
| 789 | 817 |
case 1: |
| 790 |
if (bswap) tcg_out32 (s, STHBRX | RS (data_reg) | RA (0) | RB (r0)); |
|
| 791 |
else tcg_out32 (s, STH | RS (data_reg) | RA (r0)); |
|
| 818 |
if (bswap) |
|
| 819 |
tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0)); |
|
| 820 |
else |
|
| 821 |
tcg_out32 (s, STHX | SAB (data_reg, rbase, r0)); |
|
| 792 | 822 |
break; |
| 793 | 823 |
case 2: |
| 794 |
if (bswap) tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0)); |
|
| 795 |
else tcg_out32 (s, STW | RS (data_reg) | RA (r0)); |
|
| 824 |
if (bswap) |
|
| 825 |
tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0)); |
|
| 826 |
else |
|
| 827 |
tcg_out32 (s, STWX | SAB (data_reg, rbase, r0)); |
|
| 796 | 828 |
break; |
| 797 | 829 |
case 3: |
| 798 | 830 |
if (bswap) {
|
| 799 |
tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
|
|
| 831 |
tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
|
|
| 800 | 832 |
tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4); |
| 801 | 833 |
tcg_out_rld (s, RLDICL, 0, data_reg, 32, 0); |
| 802 |
tcg_out32 (s, STWBRX | RS (0) | RA (0) | RB (r1));
|
|
| 834 |
tcg_out32 (s, STWBRX | SAB (0, rbase, r1));
|
|
| 803 | 835 |
} |
| 804 |
else tcg_out32 (s, STD | RS (data_reg) | RA (r0));
|
|
| 836 |
else tcg_out32 (s, STDX | SAB (data_reg, rbase, r0));
|
|
| 805 | 837 |
break; |
| 806 | 838 |
} |
| 807 | 839 |
|
| ... | ... | |
| 844 | 876 |
); |
| 845 | 877 |
tcg_out32 (s, STD | RS (0) | RA (1) | (frame_size + 16)); |
| 846 | 878 |
|
| 879 |
#ifdef CONFIG_USE_GUEST_BASE |
|
| 880 |
tcg_out_movi (s, TCG_TYPE_I64, TCG_GUEST_BASE_REG, GUEST_BASE); |
|
| 881 |
#endif |
|
| 882 |
|
|
| 847 | 883 |
tcg_out32 (s, MTSPR | RS (3) | CTR); |
| 848 | 884 |
tcg_out32 (s, BCCTR | BO_ALWAYS); |
| 849 | 885 |
|
| ... | ... | |
| 1498 | 1534 |
tcg_regset_set_reg (s->reserved_regs, TCG_REG_R2); |
| 1499 | 1535 |
tcg_regset_set_reg (s->reserved_regs, TCG_REG_R13); |
| 1500 | 1536 |
|
| 1537 |
#ifdef CONFIG_USE_GUEST_BASE |
|
| 1538 |
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); |
|
| 1539 |
#endif |
|
| 1540 |
|
|
| 1501 | 1541 |
tcg_add_target_add_op_defs (ppc_op_defs); |
| 1502 | 1542 |
} |
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