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1
/*
2
 * QEMU KVM support
3
 *
4
 * Copyright (C) 2006-2008 Qumranet Technologies
5
 * Copyright IBM, Corp. 2008
6
 *
7
 * Authors:
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 *  Anthony Liguori   <aliguori@us.ibm.com>
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 *
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 * This work is licensed under the terms of the GNU GPL, version 2 or later.
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 * See the COPYING file in the top-level directory.
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 *
13
 */
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15
#include <sys/types.h>
16
#include <sys/ioctl.h>
17
#include <sys/mman.h>
18
#include <sys/utsname.h>
19

    
20
#include <linux/kvm.h>
21

    
22
#include "qemu-common.h"
23
#include "sysemu.h"
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#include "kvm.h"
25
#include "cpu.h"
26
#include "gdbstub.h"
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#include "host-utils.h"
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#include "hw/pc.h"
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#include "hw/apic.h"
30
#include "ioport.h"
31
#include "kvm_x86.h"
32

    
33
#ifdef CONFIG_KVM_PARA
34
#include <linux/kvm_para.h>
35
#endif
36
//
37
//#define DEBUG_KVM
38

    
39
#ifdef DEBUG_KVM
40
#define DPRINTF(fmt, ...) \
41
    do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
42
#else
43
#define DPRINTF(fmt, ...) \
44
    do { } while (0)
45
#endif
46

    
47
#define MSR_KVM_WALL_CLOCK  0x11
48
#define MSR_KVM_SYSTEM_TIME 0x12
49

    
50
#ifndef BUS_MCEERR_AR
51
#define BUS_MCEERR_AR 4
52
#endif
53
#ifndef BUS_MCEERR_AO
54
#define BUS_MCEERR_AO 5
55
#endif
56

    
57
static int lm_capable_kernel;
58

    
59
#ifdef KVM_CAP_EXT_CPUID
60

    
61
static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
62
{
63
    struct kvm_cpuid2 *cpuid;
64
    int r, size;
65

    
66
    size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
67
    cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
68
    cpuid->nent = max;
69
    r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
70
    if (r == 0 && cpuid->nent >= max) {
71
        r = -E2BIG;
72
    }
73
    if (r < 0) {
74
        if (r == -E2BIG) {
75
            qemu_free(cpuid);
76
            return NULL;
77
        } else {
78
            fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
79
                    strerror(-r));
80
            exit(1);
81
        }
82
    }
83
    return cpuid;
84
}
85

    
86
uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
87
                                      uint32_t index, int reg)
88
{
89
    struct kvm_cpuid2 *cpuid;
90
    int i, max;
91
    uint32_t ret = 0;
92
    uint32_t cpuid_1_edx;
93

    
94
    if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
95
        return -1U;
96
    }
97

    
98
    max = 1;
99
    while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
100
        max *= 2;
101
    }
102

    
103
    for (i = 0; i < cpuid->nent; ++i) {
104
        if (cpuid->entries[i].function == function &&
105
            cpuid->entries[i].index == index) {
106
            switch (reg) {
107
            case R_EAX:
108
                ret = cpuid->entries[i].eax;
109
                break;
110
            case R_EBX:
111
                ret = cpuid->entries[i].ebx;
112
                break;
113
            case R_ECX:
114
                ret = cpuid->entries[i].ecx;
115
                break;
116
            case R_EDX:
117
                ret = cpuid->entries[i].edx;
118
                switch (function) {
119
                case 1:
120
                    /* KVM before 2.6.30 misreports the following features */
121
                    ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
122
                    break;
123
                case 0x80000001:
124
                    /* On Intel, kvm returns cpuid according to the Intel spec,
125
                     * so add missing bits according to the AMD spec:
126
                     */
127
                    cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
128
                    ret |= cpuid_1_edx & 0x183f7ff;
129
                    break;
130
                }
131
                break;
132
            }
133
        }
134
    }
135

    
136
    qemu_free(cpuid);
137

    
138
    return ret;
139
}
140

    
141
#else
142

    
143
uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
144
                                      uint32_t index, int reg)
145
{
146
    return -1U;
147
}
148

    
149
#endif
150

    
151
#ifdef CONFIG_KVM_PARA
152
struct kvm_para_features {
153
        int cap;
154
        int feature;
155
} para_features[] = {
156
#ifdef KVM_CAP_CLOCKSOURCE
157
        { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
158
#endif
159
#ifdef KVM_CAP_NOP_IO_DELAY
160
        { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
161
#endif
162
#ifdef KVM_CAP_PV_MMU
163
        { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
164
#endif
165
#ifdef KVM_CAP_ASYNC_PF
166
        { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
167
#endif
168
        { -1, -1 }
169
};
170

    
171
static int get_para_features(CPUState *env)
172
{
173
        int i, features = 0;
174

    
175
        for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
176
                if (kvm_check_extension(env->kvm_state, para_features[i].cap))
177
                        features |= (1 << para_features[i].feature);
178
        }
179

    
180
        return features;
181
}
182
#endif
183

    
184
#ifdef KVM_CAP_MCE
185
static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
186
                                     int *max_banks)
187
{
188
    int r;
189

    
190
    r = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_MCE);
191
    if (r > 0) {
192
        *max_banks = r;
193
        return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
194
    }
195
    return -ENOSYS;
196
}
197

    
198
static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap)
199
{
200
    return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap);
201
}
202

    
203
static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m)
204
{
205
    return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m);
206
}
207

    
208
static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n)
209
{
210
    struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
211
    int r;
212

    
213
    kmsrs->nmsrs = n;
214
    memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
215
    r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs);
216
    memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
217
    free(kmsrs);
218
    return r;
219
}
220

    
221
/* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */
222
static int kvm_mce_in_exception(CPUState *env)
223
{
224
    struct kvm_msr_entry msr_mcg_status = {
225
        .index = MSR_MCG_STATUS,
226
    };
227
    int r;
228

    
229
    r = kvm_get_msr(env, &msr_mcg_status, 1);
230
    if (r == -1 || r == 0) {
231
        return -1;
232
    }
233
    return !!(msr_mcg_status.data & MCG_STATUS_MCIP);
234
}
235

    
236
struct kvm_x86_mce_data
237
{
238
    CPUState *env;
239
    struct kvm_x86_mce *mce;
240
    int abort_on_error;
241
};
242

    
243
static void kvm_do_inject_x86_mce(void *_data)
244
{
245
    struct kvm_x86_mce_data *data = _data;
246
    int r;
247

    
248
    /* If there is an MCE exception being processed, ignore this SRAO MCE */
249
    if ((data->env->mcg_cap & MCG_SER_P) &&
250
        !(data->mce->status & MCI_STATUS_AR)) {
251
        r = kvm_mce_in_exception(data->env);
252
        if (r == -1) {
253
            fprintf(stderr, "Failed to get MCE status\n");
254
        } else if (r) {
255
            return;
256
        }
257
    }
258

    
259
    r = kvm_set_mce(data->env, data->mce);
260
    if (r < 0) {
261
        perror("kvm_set_mce FAILED");
262
        if (data->abort_on_error) {
263
            abort();
264
        }
265
    }
266
}
267
#endif
268

    
269
void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status,
270
                        uint64_t mcg_status, uint64_t addr, uint64_t misc,
271
                        int abort_on_error)
272
{
273
#ifdef KVM_CAP_MCE
274
    struct kvm_x86_mce mce = {
275
        .bank = bank,
276
        .status = status,
277
        .mcg_status = mcg_status,
278
        .addr = addr,
279
        .misc = misc,
280
    };
281
    struct kvm_x86_mce_data data = {
282
            .env = cenv,
283
            .mce = &mce,
284
    };
285

    
286
    if (!cenv->mcg_cap) {
287
        fprintf(stderr, "MCE support is not enabled!\n");
288
        return;
289
    }
290

    
291
    run_on_cpu(cenv, kvm_do_inject_x86_mce, &data);
292
#else
293
    if (abort_on_error)
294
        abort();
295
#endif
296
}
297

    
298
int kvm_arch_init_vcpu(CPUState *env)
299
{
300
    struct {
301
        struct kvm_cpuid2 cpuid;
302
        struct kvm_cpuid_entry2 entries[100];
303
    } __attribute__((packed)) cpuid_data;
304
    uint32_t limit, i, j, cpuid_i;
305
    uint32_t unused;
306
    struct kvm_cpuid_entry2 *c;
307
#ifdef KVM_CPUID_SIGNATURE
308
    uint32_t signature[3];
309
#endif
310

    
311
    env->mp_state = KVM_MP_STATE_RUNNABLE;
312

    
313
    env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
314

    
315
    i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
316
    env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
317
    env->cpuid_ext_features |= i;
318

    
319
    env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
320
                                                             0, R_EDX);
321
    env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
322
                                                             0, R_ECX);
323
    env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
324
                                                             0, R_EDX);
325

    
326

    
327
    cpuid_i = 0;
328

    
329
#ifdef CONFIG_KVM_PARA
330
    /* Paravirtualization CPUIDs */
331
    memcpy(signature, "KVMKVMKVM\0\0\0", 12);
332
    c = &cpuid_data.entries[cpuid_i++];
333
    memset(c, 0, sizeof(*c));
334
    c->function = KVM_CPUID_SIGNATURE;
335
    c->eax = 0;
336
    c->ebx = signature[0];
337
    c->ecx = signature[1];
338
    c->edx = signature[2];
339

    
340
    c = &cpuid_data.entries[cpuid_i++];
341
    memset(c, 0, sizeof(*c));
342
    c->function = KVM_CPUID_FEATURES;
343
    c->eax = env->cpuid_kvm_features & get_para_features(env);
344
#endif
345

    
346
    cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
347

    
348
    for (i = 0; i <= limit; i++) {
349
        c = &cpuid_data.entries[cpuid_i++];
350

    
351
        switch (i) {
352
        case 2: {
353
            /* Keep reading function 2 till all the input is received */
354
            int times;
355

    
356
            c->function = i;
357
            c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
358
                       KVM_CPUID_FLAG_STATE_READ_NEXT;
359
            cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
360
            times = c->eax & 0xff;
361

    
362
            for (j = 1; j < times; ++j) {
363
                c = &cpuid_data.entries[cpuid_i++];
364
                c->function = i;
365
                c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
366
                cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
367
            }
368
            break;
369
        }
370
        case 4:
371
        case 0xb:
372
        case 0xd:
373
            for (j = 0; ; j++) {
374
                c->function = i;
375
                c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
376
                c->index = j;
377
                cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
378

    
379
                if (i == 4 && c->eax == 0)
380
                    break;
381
                if (i == 0xb && !(c->ecx & 0xff00))
382
                    break;
383
                if (i == 0xd && c->eax == 0)
384
                    break;
385

    
386
                c = &cpuid_data.entries[cpuid_i++];
387
            }
388
            break;
389
        default:
390
            c->function = i;
391
            c->flags = 0;
392
            cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
393
            break;
394
        }
395
    }
396
    cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
397

    
398
    for (i = 0x80000000; i <= limit; i++) {
399
        c = &cpuid_data.entries[cpuid_i++];
400

    
401
        c->function = i;
402
        c->flags = 0;
403
        cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
404
    }
405

    
406
    cpuid_data.cpuid.nent = cpuid_i;
407

    
408
#ifdef KVM_CAP_MCE
409
    if (((env->cpuid_version >> 8)&0xF) >= 6
410
        && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
411
        && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
412
        uint64_t mcg_cap;
413
        int banks;
414

    
415
        if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks))
416
            perror("kvm_get_mce_cap_supported FAILED");
417
        else {
418
            if (banks > MCE_BANKS_DEF)
419
                banks = MCE_BANKS_DEF;
420
            mcg_cap &= MCE_CAP_DEF;
421
            mcg_cap |= banks;
422
            if (kvm_setup_mce(env, &mcg_cap))
423
                perror("kvm_setup_mce FAILED");
424
            else
425
                env->mcg_cap = mcg_cap;
426
        }
427
    }
428
#endif
429

    
430
    return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
431
}
432

    
433
void kvm_arch_reset_vcpu(CPUState *env)
434
{
435
    env->exception_injected = -1;
436
    env->interrupt_injected = -1;
437
    env->nmi_injected = 0;
438
    env->nmi_pending = 0;
439
    if (kvm_irqchip_in_kernel()) {
440
        env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
441
                                          KVM_MP_STATE_UNINITIALIZED;
442
    } else {
443
        env->mp_state = KVM_MP_STATE_RUNNABLE;
444
    }
445
}
446

    
447
int has_msr_star;
448
int has_msr_hsave_pa;
449

    
450
static void kvm_supported_msrs(CPUState *env)
451
{
452
    static int kvm_supported_msrs;
453
    int ret;
454

    
455
    /* first time */
456
    if (kvm_supported_msrs == 0) {
457
        struct kvm_msr_list msr_list, *kvm_msr_list;
458

    
459
        kvm_supported_msrs = -1;
460

    
461
        /* Obtain MSR list from KVM.  These are the MSRs that we must
462
         * save/restore */
463
        msr_list.nmsrs = 0;
464
        ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
465
        if (ret < 0 && ret != -E2BIG) {
466
            return;
467
        }
468
        /* Old kernel modules had a bug and could write beyond the provided
469
           memory. Allocate at least a safe amount of 1K. */
470
        kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
471
                                              msr_list.nmsrs *
472
                                              sizeof(msr_list.indices[0])));
473

    
474
        kvm_msr_list->nmsrs = msr_list.nmsrs;
475
        ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
476
        if (ret >= 0) {
477
            int i;
478

    
479
            for (i = 0; i < kvm_msr_list->nmsrs; i++) {
480
                if (kvm_msr_list->indices[i] == MSR_STAR) {
481
                    has_msr_star = 1;
482
                    continue;
483
                }
484
                if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
485
                    has_msr_hsave_pa = 1;
486
                    continue;
487
                }
488
            }
489
        }
490

    
491
        free(kvm_msr_list);
492
    }
493

    
494
    return;
495
}
496

    
497
static int kvm_has_msr_hsave_pa(CPUState *env)
498
{
499
    kvm_supported_msrs(env);
500
    return has_msr_hsave_pa;
501
}
502

    
503
static int kvm_has_msr_star(CPUState *env)
504
{
505
    kvm_supported_msrs(env);
506
    return has_msr_star;
507
}
508

    
509
static int kvm_init_identity_map_page(KVMState *s)
510
{
511
#ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
512
    int ret;
513
    uint64_t addr = 0xfffbc000;
514

    
515
    if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
516
        return 0;
517
    }
518

    
519
    ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
520
    if (ret < 0) {
521
        fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
522
        return ret;
523
    }
524
#endif
525
    return 0;
526
}
527

    
528
int kvm_arch_init(KVMState *s, int smp_cpus)
529
{
530
    int ret;
531

    
532
    struct utsname utsname;
533

    
534
    uname(&utsname);
535
    lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
536

    
537
    /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
538
     * directly.  In order to use vm86 mode, a TSS is needed.  Since this
539
     * must be part of guest physical memory, we need to allocate it.  Older
540
     * versions of KVM just assumed that it would be at the end of physical
541
     * memory but that doesn't work with more than 4GB of memory.  We simply
542
     * refuse to work with those older versions of KVM. */
543
    ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
544
    if (ret <= 0) {
545
        fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
546
        return ret;
547
    }
548

    
549
    /* this address is 3 pages before the bios, and the bios should present
550
     * as unavaible memory.  FIXME, need to ensure the e820 map deals with
551
     * this?
552
     */
553
    /*
554
     * Tell fw_cfg to notify the BIOS to reserve the range.
555
     */
556
    if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
557
        perror("e820_add_entry() table is full");
558
        exit(1);
559
    }
560
    ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
561
    if (ret < 0) {
562
        return ret;
563
    }
564

    
565
    return kvm_init_identity_map_page(s);
566
}
567
                    
568
static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
569
{
570
    lhs->selector = rhs->selector;
571
    lhs->base = rhs->base;
572
    lhs->limit = rhs->limit;
573
    lhs->type = 3;
574
    lhs->present = 1;
575
    lhs->dpl = 3;
576
    lhs->db = 0;
577
    lhs->s = 1;
578
    lhs->l = 0;
579
    lhs->g = 0;
580
    lhs->avl = 0;
581
    lhs->unusable = 0;
582
}
583

    
584
static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
585
{
586
    unsigned flags = rhs->flags;
587
    lhs->selector = rhs->selector;
588
    lhs->base = rhs->base;
589
    lhs->limit = rhs->limit;
590
    lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
591
    lhs->present = (flags & DESC_P_MASK) != 0;
592
    lhs->dpl = rhs->selector & 3;
593
    lhs->db = (flags >> DESC_B_SHIFT) & 1;
594
    lhs->s = (flags & DESC_S_MASK) != 0;
595
    lhs->l = (flags >> DESC_L_SHIFT) & 1;
596
    lhs->g = (flags & DESC_G_MASK) != 0;
597
    lhs->avl = (flags & DESC_AVL_MASK) != 0;
598
    lhs->unusable = 0;
599
}
600

    
601
static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
602
{
603
    lhs->selector = rhs->selector;
604
    lhs->base = rhs->base;
605
    lhs->limit = rhs->limit;
606
    lhs->flags =
607
        (rhs->type << DESC_TYPE_SHIFT)
608
        | (rhs->present * DESC_P_MASK)
609
        | (rhs->dpl << DESC_DPL_SHIFT)
610
        | (rhs->db << DESC_B_SHIFT)
611
        | (rhs->s * DESC_S_MASK)
612
        | (rhs->l << DESC_L_SHIFT)
613
        | (rhs->g * DESC_G_MASK)
614
        | (rhs->avl * DESC_AVL_MASK);
615
}
616

    
617
static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
618
{
619
    if (set)
620
        *kvm_reg = *qemu_reg;
621
    else
622
        *qemu_reg = *kvm_reg;
623
}
624

    
625
static int kvm_getput_regs(CPUState *env, int set)
626
{
627
    struct kvm_regs regs;
628
    int ret = 0;
629

    
630
    if (!set) {
631
        ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
632
        if (ret < 0)
633
            return ret;
634
    }
635

    
636
    kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
637
    kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
638
    kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
639
    kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
640
    kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
641
    kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
642
    kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
643
    kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
644
#ifdef TARGET_X86_64
645
    kvm_getput_reg(&regs.r8, &env->regs[8], set);
646
    kvm_getput_reg(&regs.r9, &env->regs[9], set);
647
    kvm_getput_reg(&regs.r10, &env->regs[10], set);
648
    kvm_getput_reg(&regs.r11, &env->regs[11], set);
649
    kvm_getput_reg(&regs.r12, &env->regs[12], set);
650
    kvm_getput_reg(&regs.r13, &env->regs[13], set);
651
    kvm_getput_reg(&regs.r14, &env->regs[14], set);
652
    kvm_getput_reg(&regs.r15, &env->regs[15], set);
653
#endif
654

    
655
    kvm_getput_reg(&regs.rflags, &env->eflags, set);
656
    kvm_getput_reg(&regs.rip, &env->eip, set);
657

    
658
    if (set)
659
        ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
660

    
661
    return ret;
662
}
663

    
664
static int kvm_put_fpu(CPUState *env)
665
{
666
    struct kvm_fpu fpu;
667
    int i;
668

    
669
    memset(&fpu, 0, sizeof fpu);
670
    fpu.fsw = env->fpus & ~(7 << 11);
671
    fpu.fsw |= (env->fpstt & 7) << 11;
672
    fpu.fcw = env->fpuc;
673
    for (i = 0; i < 8; ++i)
674
        fpu.ftwx |= (!env->fptags[i]) << i;
675
    memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
676
    memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
677
    fpu.mxcsr = env->mxcsr;
678

    
679
    return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
680
}
681

    
682
#ifdef KVM_CAP_XSAVE
683
#define XSAVE_CWD_RIP     2
684
#define XSAVE_CWD_RDP     4
685
#define XSAVE_MXCSR       6
686
#define XSAVE_ST_SPACE    8
687
#define XSAVE_XMM_SPACE   40
688
#define XSAVE_XSTATE_BV   128
689
#define XSAVE_YMMH_SPACE  144
690
#endif
691

    
692
static int kvm_put_xsave(CPUState *env)
693
{
694
#ifdef KVM_CAP_XSAVE
695
    int i, r;
696
    struct kvm_xsave* xsave;
697
    uint16_t cwd, swd, twd, fop;
698

    
699
    if (!kvm_has_xsave())
700
        return kvm_put_fpu(env);
701

    
702
    xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
703
    memset(xsave, 0, sizeof(struct kvm_xsave));
704
    cwd = swd = twd = fop = 0;
705
    swd = env->fpus & ~(7 << 11);
706
    swd |= (env->fpstt & 7) << 11;
707
    cwd = env->fpuc;
708
    for (i = 0; i < 8; ++i)
709
        twd |= (!env->fptags[i]) << i;
710
    xsave->region[0] = (uint32_t)(swd << 16) + cwd;
711
    xsave->region[1] = (uint32_t)(fop << 16) + twd;
712
    memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
713
            sizeof env->fpregs);
714
    memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
715
            sizeof env->xmm_regs);
716
    xsave->region[XSAVE_MXCSR] = env->mxcsr;
717
    *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
718
    memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
719
            sizeof env->ymmh_regs);
720
    r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
721
    qemu_free(xsave);
722
    return r;
723
#else
724
    return kvm_put_fpu(env);
725
#endif
726
}
727

    
728
static int kvm_put_xcrs(CPUState *env)
729
{
730
#ifdef KVM_CAP_XCRS
731
    struct kvm_xcrs xcrs;
732

    
733
    if (!kvm_has_xcrs())
734
        return 0;
735

    
736
    xcrs.nr_xcrs = 1;
737
    xcrs.flags = 0;
738
    xcrs.xcrs[0].xcr = 0;
739
    xcrs.xcrs[0].value = env->xcr0;
740
    return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
741
#else
742
    return 0;
743
#endif
744
}
745

    
746
static int kvm_put_sregs(CPUState *env)
747
{
748
    struct kvm_sregs sregs;
749

    
750
    memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
751
    if (env->interrupt_injected >= 0) {
752
        sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
753
                (uint64_t)1 << (env->interrupt_injected % 64);
754
    }
755

    
756
    if ((env->eflags & VM_MASK)) {
757
            set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
758
            set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
759
            set_v8086_seg(&sregs.es, &env->segs[R_ES]);
760
            set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
761
            set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
762
            set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
763
    } else {
764
            set_seg(&sregs.cs, &env->segs[R_CS]);
765
            set_seg(&sregs.ds, &env->segs[R_DS]);
766
            set_seg(&sregs.es, &env->segs[R_ES]);
767
            set_seg(&sregs.fs, &env->segs[R_FS]);
768
            set_seg(&sregs.gs, &env->segs[R_GS]);
769
            set_seg(&sregs.ss, &env->segs[R_SS]);
770

    
771
            if (env->cr[0] & CR0_PE_MASK) {
772
                /* force ss cpl to cs cpl */
773
                sregs.ss.selector = (sregs.ss.selector & ~3) |
774
                        (sregs.cs.selector & 3);
775
                sregs.ss.dpl = sregs.ss.selector & 3;
776
            }
777
    }
778

    
779
    set_seg(&sregs.tr, &env->tr);
780
    set_seg(&sregs.ldt, &env->ldt);
781

    
782
    sregs.idt.limit = env->idt.limit;
783
    sregs.idt.base = env->idt.base;
784
    sregs.gdt.limit = env->gdt.limit;
785
    sregs.gdt.base = env->gdt.base;
786

    
787
    sregs.cr0 = env->cr[0];
788
    sregs.cr2 = env->cr[2];
789
    sregs.cr3 = env->cr[3];
790
    sregs.cr4 = env->cr[4];
791

    
792
    sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
793
    sregs.apic_base = cpu_get_apic_base(env->apic_state);
794

    
795
    sregs.efer = env->efer;
796

    
797
    return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
798
}
799

    
800
static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
801
                              uint32_t index, uint64_t value)
802
{
803
    entry->index = index;
804
    entry->data = value;
805
}
806

    
807
static int kvm_put_msrs(CPUState *env, int level)
808
{
809
    struct {
810
        struct kvm_msrs info;
811
        struct kvm_msr_entry entries[100];
812
    } msr_data;
813
    struct kvm_msr_entry *msrs = msr_data.entries;
814
    int n = 0;
815

    
816
    kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
817
    kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
818
    kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
819
    if (kvm_has_msr_star(env))
820
        kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
821
    if (kvm_has_msr_hsave_pa(env))
822
        kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
823
#ifdef TARGET_X86_64
824
    if (lm_capable_kernel) {
825
        kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
826
        kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
827
        kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
828
        kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
829
    }
830
#endif
831
    if (level == KVM_PUT_FULL_STATE) {
832
        /*
833
         * KVM is yet unable to synchronize TSC values of multiple VCPUs on
834
         * writeback. Until this is fixed, we only write the offset to SMP
835
         * guests after migration, desynchronizing the VCPUs, but avoiding
836
         * huge jump-backs that would occur without any writeback at all.
837
         */
838
        if (smp_cpus == 1 || env->tsc != 0) {
839
            kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
840
        }
841
        kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
842
                          env->system_time_msr);
843
        kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
844
#ifdef KVM_CAP_ASYNC_PF
845
        kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
846
#endif
847
    }
848
#ifdef KVM_CAP_MCE
849
    if (env->mcg_cap) {
850
        int i;
851
        if (level == KVM_PUT_RESET_STATE)
852
            kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
853
        else if (level == KVM_PUT_FULL_STATE) {
854
            kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
855
            kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
856
            for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++)
857
                kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
858
        }
859
    }
860
#endif
861

    
862
    msr_data.info.nmsrs = n;
863

    
864
    return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
865

    
866
}
867

    
868

    
869
static int kvm_get_fpu(CPUState *env)
870
{
871
    struct kvm_fpu fpu;
872
    int i, ret;
873

    
874
    ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
875
    if (ret < 0)
876
        return ret;
877

    
878
    env->fpstt = (fpu.fsw >> 11) & 7;
879
    env->fpus = fpu.fsw;
880
    env->fpuc = fpu.fcw;
881
    for (i = 0; i < 8; ++i)
882
        env->fptags[i] = !((fpu.ftwx >> i) & 1);
883
    memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
884
    memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
885
    env->mxcsr = fpu.mxcsr;
886

    
887
    return 0;
888
}
889

    
890
static int kvm_get_xsave(CPUState *env)
891
{
892
#ifdef KVM_CAP_XSAVE
893
    struct kvm_xsave* xsave;
894
    int ret, i;
895
    uint16_t cwd, swd, twd, fop;
896

    
897
    if (!kvm_has_xsave())
898
        return kvm_get_fpu(env);
899

    
900
    xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
901
    ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
902
    if (ret < 0) {
903
        qemu_free(xsave);
904
        return ret;
905
    }
906

    
907
    cwd = (uint16_t)xsave->region[0];
908
    swd = (uint16_t)(xsave->region[0] >> 16);
909
    twd = (uint16_t)xsave->region[1];
910
    fop = (uint16_t)(xsave->region[1] >> 16);
911
    env->fpstt = (swd >> 11) & 7;
912
    env->fpus = swd;
913
    env->fpuc = cwd;
914
    for (i = 0; i < 8; ++i)
915
        env->fptags[i] = !((twd >> i) & 1);
916
    env->mxcsr = xsave->region[XSAVE_MXCSR];
917
    memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
918
            sizeof env->fpregs);
919
    memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
920
            sizeof env->xmm_regs);
921
    env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
922
    memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
923
            sizeof env->ymmh_regs);
924
    qemu_free(xsave);
925
    return 0;
926
#else
927
    return kvm_get_fpu(env);
928
#endif
929
}
930

    
931
static int kvm_get_xcrs(CPUState *env)
932
{
933
#ifdef KVM_CAP_XCRS
934
    int i, ret;
935
    struct kvm_xcrs xcrs;
936

    
937
    if (!kvm_has_xcrs())
938
        return 0;
939

    
940
    ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
941
    if (ret < 0)
942
        return ret;
943

    
944
    for (i = 0; i < xcrs.nr_xcrs; i++)
945
        /* Only support xcr0 now */
946
        if (xcrs.xcrs[0].xcr == 0) {
947
            env->xcr0 = xcrs.xcrs[0].value;
948
            break;
949
        }
950
    return 0;
951
#else
952
    return 0;
953
#endif
954
}
955

    
956
static int kvm_get_sregs(CPUState *env)
957
{
958
    struct kvm_sregs sregs;
959
    uint32_t hflags;
960
    int bit, i, ret;
961

    
962
    ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
963
    if (ret < 0)
964
        return ret;
965

    
966
    /* There can only be one pending IRQ set in the bitmap at a time, so try
967
       to find it and save its number instead (-1 for none). */
968
    env->interrupt_injected = -1;
969
    for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
970
        if (sregs.interrupt_bitmap[i]) {
971
            bit = ctz64(sregs.interrupt_bitmap[i]);
972
            env->interrupt_injected = i * 64 + bit;
973
            break;
974
        }
975
    }
976

    
977
    get_seg(&env->segs[R_CS], &sregs.cs);
978
    get_seg(&env->segs[R_DS], &sregs.ds);
979
    get_seg(&env->segs[R_ES], &sregs.es);
980
    get_seg(&env->segs[R_FS], &sregs.fs);
981
    get_seg(&env->segs[R_GS], &sregs.gs);
982
    get_seg(&env->segs[R_SS], &sregs.ss);
983

    
984
    get_seg(&env->tr, &sregs.tr);
985
    get_seg(&env->ldt, &sregs.ldt);
986

    
987
    env->idt.limit = sregs.idt.limit;
988
    env->idt.base = sregs.idt.base;
989
    env->gdt.limit = sregs.gdt.limit;
990
    env->gdt.base = sregs.gdt.base;
991

    
992
    env->cr[0] = sregs.cr0;
993
    env->cr[2] = sregs.cr2;
994
    env->cr[3] = sregs.cr3;
995
    env->cr[4] = sregs.cr4;
996

    
997
    cpu_set_apic_base(env->apic_state, sregs.apic_base);
998

    
999
    env->efer = sregs.efer;
1000
    //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
1001

    
1002
#define HFLAG_COPY_MASK ~( \
1003
                        HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1004
                        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1005
                        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1006
                        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1007

    
1008

    
1009

    
1010
    hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1011
    hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1012
    hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1013
            (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1014
    hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1015
    hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1016
            (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1017

    
1018
    if (env->efer & MSR_EFER_LMA) {
1019
        hflags |= HF_LMA_MASK;
1020
    }
1021

    
1022
    if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1023
        hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1024
    } else {
1025
        hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1026
                (DESC_B_SHIFT - HF_CS32_SHIFT);
1027
        hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1028
                (DESC_B_SHIFT - HF_SS32_SHIFT);
1029
        if (!(env->cr[0] & CR0_PE_MASK) ||
1030
                   (env->eflags & VM_MASK) ||
1031
                   !(hflags & HF_CS32_MASK)) {
1032
                hflags |= HF_ADDSEG_MASK;
1033
            } else {
1034
                hflags |= ((env->segs[R_DS].base |
1035
                                env->segs[R_ES].base |
1036
                                env->segs[R_SS].base) != 0) <<
1037
                    HF_ADDSEG_SHIFT;
1038
            }
1039
    }
1040
    env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1041

    
1042
    return 0;
1043
}
1044

    
1045
static int kvm_get_msrs(CPUState *env)
1046
{
1047
    struct {
1048
        struct kvm_msrs info;
1049
        struct kvm_msr_entry entries[100];
1050
    } msr_data;
1051
    struct kvm_msr_entry *msrs = msr_data.entries;
1052
    int ret, i, n;
1053

    
1054
    n = 0;
1055
    msrs[n++].index = MSR_IA32_SYSENTER_CS;
1056
    msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1057
    msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1058
    if (kvm_has_msr_star(env))
1059
        msrs[n++].index = MSR_STAR;
1060
    if (kvm_has_msr_hsave_pa(env))
1061
        msrs[n++].index = MSR_VM_HSAVE_PA;
1062
    msrs[n++].index = MSR_IA32_TSC;
1063
#ifdef TARGET_X86_64
1064
    if (lm_capable_kernel) {
1065
        msrs[n++].index = MSR_CSTAR;
1066
        msrs[n++].index = MSR_KERNELGSBASE;
1067
        msrs[n++].index = MSR_FMASK;
1068
        msrs[n++].index = MSR_LSTAR;
1069
    }
1070
#endif
1071
    msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1072
    msrs[n++].index = MSR_KVM_WALL_CLOCK;
1073
#ifdef KVM_CAP_ASYNC_PF
1074
    msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1075
#endif
1076

    
1077
#ifdef KVM_CAP_MCE
1078
    if (env->mcg_cap) {
1079
        msrs[n++].index = MSR_MCG_STATUS;
1080
        msrs[n++].index = MSR_MCG_CTL;
1081
        for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++)
1082
            msrs[n++].index = MSR_MC0_CTL + i;
1083
    }
1084
#endif
1085

    
1086
    msr_data.info.nmsrs = n;
1087
    ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1088
    if (ret < 0)
1089
        return ret;
1090

    
1091
    for (i = 0; i < ret; i++) {
1092
        switch (msrs[i].index) {
1093
        case MSR_IA32_SYSENTER_CS:
1094
            env->sysenter_cs = msrs[i].data;
1095
            break;
1096
        case MSR_IA32_SYSENTER_ESP:
1097
            env->sysenter_esp = msrs[i].data;
1098
            break;
1099
        case MSR_IA32_SYSENTER_EIP:
1100
            env->sysenter_eip = msrs[i].data;
1101
            break;
1102
        case MSR_STAR:
1103
            env->star = msrs[i].data;
1104
            break;
1105
#ifdef TARGET_X86_64
1106
        case MSR_CSTAR:
1107
            env->cstar = msrs[i].data;
1108
            break;
1109
        case MSR_KERNELGSBASE:
1110
            env->kernelgsbase = msrs[i].data;
1111
            break;
1112
        case MSR_FMASK:
1113
            env->fmask = msrs[i].data;
1114
            break;
1115
        case MSR_LSTAR:
1116
            env->lstar = msrs[i].data;
1117
            break;
1118
#endif
1119
        case MSR_IA32_TSC:
1120
            env->tsc = msrs[i].data;
1121
            break;
1122
        case MSR_VM_HSAVE_PA:
1123
            env->vm_hsave = msrs[i].data;
1124
            break;
1125
        case MSR_KVM_SYSTEM_TIME:
1126
            env->system_time_msr = msrs[i].data;
1127
            break;
1128
        case MSR_KVM_WALL_CLOCK:
1129
            env->wall_clock_msr = msrs[i].data;
1130
            break;
1131
#ifdef KVM_CAP_MCE
1132
        case MSR_MCG_STATUS:
1133
            env->mcg_status = msrs[i].data;
1134
            break;
1135
        case MSR_MCG_CTL:
1136
            env->mcg_ctl = msrs[i].data;
1137
            break;
1138
#endif
1139
        default:
1140
#ifdef KVM_CAP_MCE
1141
            if (msrs[i].index >= MSR_MC0_CTL &&
1142
                msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1143
                env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1144
            }
1145
#endif
1146
            break;
1147
#ifdef KVM_CAP_ASYNC_PF
1148
        case MSR_KVM_ASYNC_PF_EN:
1149
            env->async_pf_en_msr = msrs[i].data;
1150
            break;
1151
#endif
1152
        }
1153
    }
1154

    
1155
    return 0;
1156
}
1157

    
1158
static int kvm_put_mp_state(CPUState *env)
1159
{
1160
    struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1161

    
1162
    return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1163
}
1164

    
1165
static int kvm_get_mp_state(CPUState *env)
1166
{
1167
    struct kvm_mp_state mp_state;
1168
    int ret;
1169

    
1170
    ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1171
    if (ret < 0) {
1172
        return ret;
1173
    }
1174
    env->mp_state = mp_state.mp_state;
1175
    return 0;
1176
}
1177

    
1178
static int kvm_put_vcpu_events(CPUState *env, int level)
1179
{
1180
#ifdef KVM_CAP_VCPU_EVENTS
1181
    struct kvm_vcpu_events events;
1182

    
1183
    if (!kvm_has_vcpu_events()) {
1184
        return 0;
1185
    }
1186

    
1187
    events.exception.injected = (env->exception_injected >= 0);
1188
    events.exception.nr = env->exception_injected;
1189
    events.exception.has_error_code = env->has_error_code;
1190
    events.exception.error_code = env->error_code;
1191

    
1192
    events.interrupt.injected = (env->interrupt_injected >= 0);
1193
    events.interrupt.nr = env->interrupt_injected;
1194
    events.interrupt.soft = env->soft_interrupt;
1195

    
1196
    events.nmi.injected = env->nmi_injected;
1197
    events.nmi.pending = env->nmi_pending;
1198
    events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1199

    
1200
    events.sipi_vector = env->sipi_vector;
1201

    
1202
    events.flags = 0;
1203
    if (level >= KVM_PUT_RESET_STATE) {
1204
        events.flags |=
1205
            KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1206
    }
1207

    
1208
    return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1209
#else
1210
    return 0;
1211
#endif
1212
}
1213

    
1214
static int kvm_get_vcpu_events(CPUState *env)
1215
{
1216
#ifdef KVM_CAP_VCPU_EVENTS
1217
    struct kvm_vcpu_events events;
1218
    int ret;
1219

    
1220
    if (!kvm_has_vcpu_events()) {
1221
        return 0;
1222
    }
1223

    
1224
    ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1225
    if (ret < 0) {
1226
       return ret;
1227
    }
1228
    env->exception_injected =
1229
       events.exception.injected ? events.exception.nr : -1;
1230
    env->has_error_code = events.exception.has_error_code;
1231
    env->error_code = events.exception.error_code;
1232

    
1233
    env->interrupt_injected =
1234
        events.interrupt.injected ? events.interrupt.nr : -1;
1235
    env->soft_interrupt = events.interrupt.soft;
1236

    
1237
    env->nmi_injected = events.nmi.injected;
1238
    env->nmi_pending = events.nmi.pending;
1239
    if (events.nmi.masked) {
1240
        env->hflags2 |= HF2_NMI_MASK;
1241
    } else {
1242
        env->hflags2 &= ~HF2_NMI_MASK;
1243
    }
1244

    
1245
    env->sipi_vector = events.sipi_vector;
1246
#endif
1247

    
1248
    return 0;
1249
}
1250

    
1251
static int kvm_guest_debug_workarounds(CPUState *env)
1252
{
1253
    int ret = 0;
1254
#ifdef KVM_CAP_SET_GUEST_DEBUG
1255
    unsigned long reinject_trap = 0;
1256

    
1257
    if (!kvm_has_vcpu_events()) {
1258
        if (env->exception_injected == 1) {
1259
            reinject_trap = KVM_GUESTDBG_INJECT_DB;
1260
        } else if (env->exception_injected == 3) {
1261
            reinject_trap = KVM_GUESTDBG_INJECT_BP;
1262
        }
1263
        env->exception_injected = -1;
1264
    }
1265

    
1266
    /*
1267
     * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1268
     * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1269
     * by updating the debug state once again if single-stepping is on.
1270
     * Another reason to call kvm_update_guest_debug here is a pending debug
1271
     * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1272
     * reinject them via SET_GUEST_DEBUG.
1273
     */
1274
    if (reinject_trap ||
1275
        (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1276
        ret = kvm_update_guest_debug(env, reinject_trap);
1277
    }
1278
#endif /* KVM_CAP_SET_GUEST_DEBUG */
1279
    return ret;
1280
}
1281

    
1282
static int kvm_put_debugregs(CPUState *env)
1283
{
1284
#ifdef KVM_CAP_DEBUGREGS
1285
    struct kvm_debugregs dbgregs;
1286
    int i;
1287

    
1288
    if (!kvm_has_debugregs()) {
1289
        return 0;
1290
    }
1291

    
1292
    for (i = 0; i < 4; i++) {
1293
        dbgregs.db[i] = env->dr[i];
1294
    }
1295
    dbgregs.dr6 = env->dr[6];
1296
    dbgregs.dr7 = env->dr[7];
1297
    dbgregs.flags = 0;
1298

    
1299
    return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1300
#else
1301
    return 0;
1302
#endif
1303
}
1304

    
1305
static int kvm_get_debugregs(CPUState *env)
1306
{
1307
#ifdef KVM_CAP_DEBUGREGS
1308
    struct kvm_debugregs dbgregs;
1309
    int i, ret;
1310

    
1311
    if (!kvm_has_debugregs()) {
1312
        return 0;
1313
    }
1314

    
1315
    ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1316
    if (ret < 0) {
1317
       return ret;
1318
    }
1319
    for (i = 0; i < 4; i++) {
1320
        env->dr[i] = dbgregs.db[i];
1321
    }
1322
    env->dr[4] = env->dr[6] = dbgregs.dr6;
1323
    env->dr[5] = env->dr[7] = dbgregs.dr7;
1324
#endif
1325

    
1326
    return 0;
1327
}
1328

    
1329
int kvm_arch_put_registers(CPUState *env, int level)
1330
{
1331
    int ret;
1332

    
1333
    assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1334

    
1335
    ret = kvm_getput_regs(env, 1);
1336
    if (ret < 0)
1337
        return ret;
1338

    
1339
    ret = kvm_put_xsave(env);
1340
    if (ret < 0)
1341
        return ret;
1342

    
1343
    ret = kvm_put_xcrs(env);
1344
    if (ret < 0)
1345
        return ret;
1346

    
1347
    ret = kvm_put_sregs(env);
1348
    if (ret < 0)
1349
        return ret;
1350

    
1351
    ret = kvm_put_msrs(env, level);
1352
    if (ret < 0)
1353
        return ret;
1354

    
1355
    if (level >= KVM_PUT_RESET_STATE) {
1356
        ret = kvm_put_mp_state(env);
1357
        if (ret < 0)
1358
            return ret;
1359
    }
1360

    
1361
    ret = kvm_put_vcpu_events(env, level);
1362
    if (ret < 0)
1363
        return ret;
1364

    
1365
    /* must be last */
1366
    ret = kvm_guest_debug_workarounds(env);
1367
    if (ret < 0)
1368
        return ret;
1369

    
1370
    ret = kvm_put_debugregs(env);
1371
    if (ret < 0)
1372
        return ret;
1373

    
1374
    return 0;
1375
}
1376

    
1377
int kvm_arch_get_registers(CPUState *env)
1378
{
1379
    int ret;
1380

    
1381
    assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1382

    
1383
    ret = kvm_getput_regs(env, 0);
1384
    if (ret < 0)
1385
        return ret;
1386

    
1387
    ret = kvm_get_xsave(env);
1388
    if (ret < 0)
1389
        return ret;
1390

    
1391
    ret = kvm_get_xcrs(env);
1392
    if (ret < 0)
1393
        return ret;
1394

    
1395
    ret = kvm_get_sregs(env);
1396
    if (ret < 0)
1397
        return ret;
1398

    
1399
    ret = kvm_get_msrs(env);
1400
    if (ret < 0)
1401
        return ret;
1402

    
1403
    ret = kvm_get_mp_state(env);
1404
    if (ret < 0)
1405
        return ret;
1406

    
1407
    ret = kvm_get_vcpu_events(env);
1408
    if (ret < 0)
1409
        return ret;
1410

    
1411
    ret = kvm_get_debugregs(env);
1412
    if (ret < 0)
1413
        return ret;
1414

    
1415
    return 0;
1416
}
1417

    
1418
int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1419
{
1420
    /* Try to inject an interrupt if the guest can accept it */
1421
    if (run->ready_for_interrupt_injection &&
1422
        (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1423
        (env->eflags & IF_MASK)) {
1424
        int irq;
1425

    
1426
        env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1427
        irq = cpu_get_pic_interrupt(env);
1428
        if (irq >= 0) {
1429
            struct kvm_interrupt intr;
1430
            intr.irq = irq;
1431
            /* FIXME: errors */
1432
            DPRINTF("injected interrupt %d\n", irq);
1433
            kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1434
        }
1435
    }
1436

    
1437
    /* If we have an interrupt but the guest is not ready to receive an
1438
     * interrupt, request an interrupt window exit.  This will
1439
     * cause a return to userspace as soon as the guest is ready to
1440
     * receive interrupts. */
1441
    if ((env->interrupt_request & CPU_INTERRUPT_HARD))
1442
        run->request_interrupt_window = 1;
1443
    else
1444
        run->request_interrupt_window = 0;
1445

    
1446
    DPRINTF("setting tpr\n");
1447
    run->cr8 = cpu_get_apic_tpr(env->apic_state);
1448

    
1449
    return 0;
1450
}
1451

    
1452
int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1453
{
1454
    if (run->if_flag)
1455
        env->eflags |= IF_MASK;
1456
    else
1457
        env->eflags &= ~IF_MASK;
1458
    
1459
    cpu_set_apic_tpr(env->apic_state, run->cr8);
1460
    cpu_set_apic_base(env->apic_state, run->apic_base);
1461

    
1462
    return 0;
1463
}
1464

    
1465
int kvm_arch_process_irqchip_events(CPUState *env)
1466
{
1467
    if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1468
        kvm_cpu_synchronize_state(env);
1469
        do_cpu_init(env);
1470
        env->exception_index = EXCP_HALTED;
1471
    }
1472

    
1473
    if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1474
        kvm_cpu_synchronize_state(env);
1475
        do_cpu_sipi(env);
1476
    }
1477

    
1478
    return env->halted;
1479
}
1480

    
1481
static int kvm_handle_halt(CPUState *env)
1482
{
1483
    if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1484
          (env->eflags & IF_MASK)) &&
1485
        !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1486
        env->halted = 1;
1487
        env->exception_index = EXCP_HLT;
1488
        return 0;
1489
    }
1490

    
1491
    return 1;
1492
}
1493

    
1494
int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1495
{
1496
    int ret = 0;
1497

    
1498
    switch (run->exit_reason) {
1499
    case KVM_EXIT_HLT:
1500
        DPRINTF("handle_hlt\n");
1501
        ret = kvm_handle_halt(env);
1502
        break;
1503
    }
1504

    
1505
    return ret;
1506
}
1507

    
1508
#ifdef KVM_CAP_SET_GUEST_DEBUG
1509
int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1510
{
1511
    static const uint8_t int3 = 0xcc;
1512

    
1513
    if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1514
        cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
1515
        return -EINVAL;
1516
    return 0;
1517
}
1518

    
1519
int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1520
{
1521
    uint8_t int3;
1522

    
1523
    if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1524
        cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1525
        return -EINVAL;
1526
    return 0;
1527
}
1528

    
1529
static struct {
1530
    target_ulong addr;
1531
    int len;
1532
    int type;
1533
} hw_breakpoint[4];
1534

    
1535
static int nb_hw_breakpoint;
1536

    
1537
static int find_hw_breakpoint(target_ulong addr, int len, int type)
1538
{
1539
    int n;
1540

    
1541
    for (n = 0; n < nb_hw_breakpoint; n++)
1542
        if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1543
            (hw_breakpoint[n].len == len || len == -1))
1544
            return n;
1545
    return -1;
1546
}
1547

    
1548
int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1549
                                  target_ulong len, int type)
1550
{
1551
    switch (type) {
1552
    case GDB_BREAKPOINT_HW:
1553
        len = 1;
1554
        break;
1555
    case GDB_WATCHPOINT_WRITE:
1556
    case GDB_WATCHPOINT_ACCESS:
1557
        switch (len) {
1558
        case 1:
1559
            break;
1560
        case 2:
1561
        case 4:
1562
        case 8:
1563
            if (addr & (len - 1))
1564
                return -EINVAL;
1565
            break;
1566
        default:
1567
            return -EINVAL;
1568
        }
1569
        break;
1570
    default:
1571
        return -ENOSYS;
1572
    }
1573

    
1574
    if (nb_hw_breakpoint == 4)
1575
        return -ENOBUFS;
1576

    
1577
    if (find_hw_breakpoint(addr, len, type) >= 0)
1578
        return -EEXIST;
1579

    
1580
    hw_breakpoint[nb_hw_breakpoint].addr = addr;
1581
    hw_breakpoint[nb_hw_breakpoint].len = len;
1582
    hw_breakpoint[nb_hw_breakpoint].type = type;
1583
    nb_hw_breakpoint++;
1584

    
1585
    return 0;
1586
}
1587

    
1588
int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1589
                                  target_ulong len, int type)
1590
{
1591
    int n;
1592

    
1593
    n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1594
    if (n < 0)
1595
        return -ENOENT;
1596

    
1597
    nb_hw_breakpoint--;
1598
    hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1599

    
1600
    return 0;
1601
}
1602

    
1603
void kvm_arch_remove_all_hw_breakpoints(void)
1604
{
1605
    nb_hw_breakpoint = 0;
1606
}
1607

    
1608
static CPUWatchpoint hw_watchpoint;
1609

    
1610
int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1611
{
1612
    int handle = 0;
1613
    int n;
1614

    
1615
    if (arch_info->exception == 1) {
1616
        if (arch_info->dr6 & (1 << 14)) {
1617
            if (cpu_single_env->singlestep_enabled)
1618
                handle = 1;
1619
        } else {
1620
            for (n = 0; n < 4; n++)
1621
                if (arch_info->dr6 & (1 << n))
1622
                    switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1623
                    case 0x0:
1624
                        handle = 1;
1625
                        break;
1626
                    case 0x1:
1627
                        handle = 1;
1628
                        cpu_single_env->watchpoint_hit = &hw_watchpoint;
1629
                        hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1630
                        hw_watchpoint.flags = BP_MEM_WRITE;
1631
                        break;
1632
                    case 0x3:
1633
                        handle = 1;
1634
                        cpu_single_env->watchpoint_hit = &hw_watchpoint;
1635
                        hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1636
                        hw_watchpoint.flags = BP_MEM_ACCESS;
1637
                        break;
1638
                    }
1639
        }
1640
    } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1641
        handle = 1;
1642

    
1643
    if (!handle) {
1644
        cpu_synchronize_state(cpu_single_env);
1645
        assert(cpu_single_env->exception_injected == -1);
1646

    
1647
        cpu_single_env->exception_injected = arch_info->exception;
1648
        cpu_single_env->has_error_code = 0;
1649
    }
1650

    
1651
    return handle;
1652
}
1653

    
1654
void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1655
{
1656
    const uint8_t type_code[] = {
1657
        [GDB_BREAKPOINT_HW] = 0x0,
1658
        [GDB_WATCHPOINT_WRITE] = 0x1,
1659
        [GDB_WATCHPOINT_ACCESS] = 0x3
1660
    };
1661
    const uint8_t len_code[] = {
1662
        [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1663
    };
1664
    int n;
1665

    
1666
    if (kvm_sw_breakpoints_active(env))
1667
        dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1668

    
1669
    if (nb_hw_breakpoint > 0) {
1670
        dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1671
        dbg->arch.debugreg[7] = 0x0600;
1672
        for (n = 0; n < nb_hw_breakpoint; n++) {
1673
            dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1674
            dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1675
                (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1676
                (len_code[hw_breakpoint[n].len] << (18 + n*4));
1677
        }
1678
    }
1679
    /* Legal xcr0 for loading */
1680
    env->xcr0 = 1;
1681
}
1682
#endif /* KVM_CAP_SET_GUEST_DEBUG */
1683

    
1684
bool kvm_arch_stop_on_emulation_error(CPUState *env)
1685
{
1686
      return !(env->cr[0] & CR0_PE_MASK) ||
1687
              ((env->segs[R_CS].selector  & 3) != 3);
1688
}
1689

    
1690
static void hardware_memory_error(void)
1691
{
1692
    fprintf(stderr, "Hardware memory error!\n");
1693
    exit(1);
1694
}
1695

    
1696
#ifdef KVM_CAP_MCE
1697
static void kvm_mce_broadcast_rest(CPUState *env)
1698
{
1699
    CPUState *cenv;
1700
    int family, model, cpuver = env->cpuid_version;
1701

    
1702
    family = (cpuver >> 8) & 0xf;
1703
    model = ((cpuver >> 12) & 0xf0) + ((cpuver >> 4) & 0xf);
1704

    
1705
    /* Broadcast MCA signal for processor version 06H_EH and above */
1706
    if ((family == 6 && model >= 14) || family > 6) {
1707
        for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) {
1708
            if (cenv == env) {
1709
                continue;
1710
            }
1711
            kvm_inject_x86_mce(cenv, 1, MCI_STATUS_VAL | MCI_STATUS_UC,
1712
                               MCG_STATUS_MCIP | MCG_STATUS_RIPV, 0, 0, 1);
1713
        }
1714
    }
1715
}
1716
#endif
1717

    
1718
int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr)
1719
{
1720
#if defined(KVM_CAP_MCE)
1721
    struct kvm_x86_mce mce = {
1722
            .bank = 9,
1723
    };
1724
    void *vaddr;
1725
    ram_addr_t ram_addr;
1726
    target_phys_addr_t paddr;
1727
    int r;
1728

    
1729
    if ((env->mcg_cap & MCG_SER_P) && addr
1730
        && (code == BUS_MCEERR_AR
1731
            || code == BUS_MCEERR_AO)) {
1732
        if (code == BUS_MCEERR_AR) {
1733
            /* Fake an Intel architectural Data Load SRAR UCR */
1734
            mce.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1735
                | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1736
                | MCI_STATUS_AR | 0x134;
1737
            mce.misc = (MCM_ADDR_PHYS << 6) | 0xc;
1738
            mce.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV;
1739
        } else {
1740
            /*
1741
             * If there is an MCE excpetion being processed, ignore
1742
             * this SRAO MCE
1743
             */
1744
            r = kvm_mce_in_exception(env);
1745
            if (r == -1) {
1746
                fprintf(stderr, "Failed to get MCE status\n");
1747
            } else if (r) {
1748
                return 0;
1749
            }
1750
            /* Fake an Intel architectural Memory scrubbing UCR */
1751
            mce.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1752
                | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1753
                | 0xc0;
1754
            mce.misc = (MCM_ADDR_PHYS << 6) | 0xc;
1755
            mce.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
1756
        }
1757
        vaddr = (void *)addr;
1758
        if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1759
            !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) {
1760
            fprintf(stderr, "Hardware memory error for memory used by "
1761
                    "QEMU itself instead of guest system!\n");
1762
            /* Hope we are lucky for AO MCE */
1763
            if (code == BUS_MCEERR_AO) {
1764
                return 0;
1765
            } else {
1766
                hardware_memory_error();
1767
            }
1768
        }
1769
        mce.addr = paddr;
1770
        r = kvm_set_mce(env, &mce);
1771
        if (r < 0) {
1772
            fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1773
            abort();
1774
        }
1775
        kvm_mce_broadcast_rest(env);
1776
    } else
1777
#endif
1778
    {
1779
        if (code == BUS_MCEERR_AO) {
1780
            return 0;
1781
        } else if (code == BUS_MCEERR_AR) {
1782
            hardware_memory_error();
1783
        } else {
1784
            return 1;
1785
        }
1786
    }
1787
    return 0;
1788
}
1789

    
1790
int kvm_on_sigbus(int code, void *addr)
1791
{
1792
#if defined(KVM_CAP_MCE)
1793
    if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
1794
        uint64_t status;
1795
        void *vaddr;
1796
        ram_addr_t ram_addr;
1797
        target_phys_addr_t paddr;
1798

    
1799
        /* Hope we are lucky for AO MCE */
1800
        vaddr = addr;
1801
        if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1802
            !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, &paddr)) {
1803
            fprintf(stderr, "Hardware memory error for memory used by "
1804
                    "QEMU itself instead of guest system!: %p\n", addr);
1805
            return 0;
1806
        }
1807
        status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1808
            | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1809
            | 0xc0;
1810
        kvm_inject_x86_mce(first_cpu, 9, status,
1811
                           MCG_STATUS_MCIP | MCG_STATUS_RIPV, paddr,
1812
                           (MCM_ADDR_PHYS << 6) | 0xc, 1);
1813
        kvm_mce_broadcast_rest(first_cpu);
1814
    } else
1815
#endif
1816
    {
1817
        if (code == BUS_MCEERR_AO) {
1818
            return 0;
1819
        } else if (code == BUS_MCEERR_AR) {
1820
            hardware_memory_error();
1821
        } else {
1822
            return 1;
1823
        }
1824
    }
1825
    return 0;
1826
}