Revision f669df27 target-arm/translate.c
| b/target-arm/translate.c | ||
|---|---|---|
| 405 | 405 |
dead_tmp(tmp); |
| 406 | 406 |
} |
| 407 | 407 |
|
| 408 |
/* T0 &= ~T1. Clobbers T1. */ |
|
| 409 |
/* FIXME: Implement bic natively. */ |
|
| 410 |
static inline void tcg_gen_bic_i32(TCGv dest, TCGv t0, TCGv t1) |
|
| 411 |
{
|
|
| 412 |
TCGv tmp = new_tmp(); |
|
| 413 |
tcg_gen_not_i32(tmp, t1); |
|
| 414 |
tcg_gen_and_i32(dest, t0, tmp); |
|
| 415 |
dead_tmp(tmp); |
|
| 416 |
} |
|
| 417 |
|
|
| 418 | 408 |
/* FIXME: Implement this natively. */ |
| 419 | 409 |
#define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1) |
| 420 | 410 |
|
| 421 |
/* FIXME: Implement this natively. */ |
|
| 422 |
static void tcg_gen_rori_i32(TCGv t0, TCGv t1, int i) |
|
| 423 |
{
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| 424 |
TCGv tmp; |
|
| 425 |
|
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| 426 |
if (i == 0) |
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| 427 |
return; |
|
| 428 |
|
|
| 429 |
tmp = new_tmp(); |
|
| 430 |
tcg_gen_shri_i32(tmp, t1, i); |
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| 431 |
tcg_gen_shli_i32(t1, t1, 32 - i); |
|
| 432 |
tcg_gen_or_i32(t0, t1, tmp); |
|
| 433 |
dead_tmp(tmp); |
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| 434 |
} |
|
| 435 |
|
|
| 436 | 411 |
static void shifter_out_im(TCGv var, int shift) |
| 437 | 412 |
{
|
| 438 | 413 |
TCGv tmp = new_tmp(); |
| ... | ... | |
| 484 | 459 |
if (shift != 0) {
|
| 485 | 460 |
if (flags) |
| 486 | 461 |
shifter_out_im(var, shift - 1); |
| 487 |
tcg_gen_rori_i32(var, var, shift); break; |
|
| 462 |
tcg_gen_rotri_i32(var, var, shift); break;
|
|
| 488 | 463 |
} else {
|
| 489 | 464 |
TCGv tmp = load_cpu_field(CF); |
| 490 | 465 |
if (flags) |
| ... | ... | |
| 512 | 487 |
case 0: gen_helper_shl(var, var, shift); break; |
| 513 | 488 |
case 1: gen_helper_shr(var, var, shift); break; |
| 514 | 489 |
case 2: gen_helper_sar(var, var, shift); break; |
| 515 |
case 3: gen_helper_ror(var, var, shift); break; |
|
| 490 |
case 3: tcg_gen_andi_i32(shift, shift, 0x1f); |
|
| 491 |
tcg_gen_rotr_i32(var, var, shift); break; |
|
| 516 | 492 |
} |
| 517 | 493 |
} |
| 518 | 494 |
dead_tmp(shift); |
| ... | ... | |
| 1453 | 1429 |
case ARM_IWMMXT_wCSSF: |
| 1454 | 1430 |
tmp = iwmmxt_load_creg(wrd); |
| 1455 | 1431 |
tmp2 = load_reg(s, rd); |
| 1456 |
tcg_gen_bic_i32(tmp, tmp, tmp2);
|
|
| 1432 |
tcg_gen_andc_i32(tmp, tmp, tmp2);
|
|
| 1457 | 1433 |
dead_tmp(tmp2); |
| 1458 | 1434 |
iwmmxt_store_creg(wrd, tmp); |
| 1459 | 1435 |
break; |
| ... | ... | |
| 3931 | 3907 |
static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c) |
| 3932 | 3908 |
{
|
| 3933 | 3909 |
tcg_gen_and_i32(t, t, c); |
| 3934 |
tcg_gen_bic_i32(f, f, c);
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|
| 3910 |
tcg_gen_andc_i32(f, f, c);
|
|
| 3935 | 3911 |
tcg_gen_or_i32(dest, t, f); |
| 3936 | 3912 |
} |
| 3937 | 3913 |
|
| ... | ... | |
| 4244 | 4220 |
tcg_gen_and_i32(tmp, tmp, tmp2); |
| 4245 | 4221 |
break; |
| 4246 | 4222 |
case 1: /* BIC */ |
| 4247 |
tcg_gen_bic_i32(tmp, tmp, tmp2);
|
|
| 4223 |
tcg_gen_andc_i32(tmp, tmp, tmp2);
|
|
| 4248 | 4224 |
break; |
| 4249 | 4225 |
case 2: /* VORR */ |
| 4250 | 4226 |
tcg_gen_or_i32(tmp, tmp, tmp2); |
| 4251 | 4227 |
break; |
| 4252 | 4228 |
case 3: /* VORN */ |
| 4253 |
tcg_gen_not_i32(tmp2, tmp2); |
|
| 4254 |
tcg_gen_or_i32(tmp, tmp, tmp2); |
|
| 4229 |
tcg_gen_orc_i32(tmp, tmp, tmp2); |
|
| 4255 | 4230 |
break; |
| 4256 | 4231 |
case 4: /* VEOR */ |
| 4257 | 4232 |
tcg_gen_xor_i32(tmp, tmp, tmp2); |
| ... | ... | |
| 6304 | 6279 |
} |
| 6305 | 6280 |
break; |
| 6306 | 6281 |
case 0x0e: |
| 6307 |
tcg_gen_bic_i32(tmp, tmp, tmp2);
|
|
| 6282 |
tcg_gen_andc_i32(tmp, tmp, tmp2);
|
|
| 6308 | 6283 |
if (logic_cc) {
|
| 6309 | 6284 |
gen_logic_CC(tmp); |
| 6310 | 6285 |
} |
| ... | ... | |
| 6635 | 6610 |
/* ??? In many cases it's not neccessary to do a |
| 6636 | 6611 |
rotate, a shift is sufficient. */ |
| 6637 | 6612 |
if (shift != 0) |
| 6638 |
tcg_gen_rori_i32(tmp, tmp, shift * 8); |
|
| 6613 |
tcg_gen_rotri_i32(tmp, tmp, shift * 8);
|
|
| 6639 | 6614 |
op1 = (insn >> 20) & 7; |
| 6640 | 6615 |
switch (op1) {
|
| 6641 | 6616 |
case 0: gen_sxtb16(tmp); break; |
| ... | ... | |
| 7023 | 6998 |
logic_cc = conds; |
| 7024 | 6999 |
break; |
| 7025 | 7000 |
case 1: /* bic */ |
| 7026 |
tcg_gen_bic_i32(t0, t0, t1);
|
|
| 7001 |
tcg_gen_andc_i32(t0, t0, t1);
|
|
| 7027 | 7002 |
logic_cc = conds; |
| 7028 | 7003 |
break; |
| 7029 | 7004 |
case 2: /* orr */ |
| ... | ... | |
| 7449 | 7424 |
/* ??? In many cases it's not neccessary to do a |
| 7450 | 7425 |
rotate, a shift is sufficient. */ |
| 7451 | 7426 |
if (shift != 0) |
| 7452 |
tcg_gen_rori_i32(tmp, tmp, shift * 8); |
|
| 7427 |
tcg_gen_rotri_i32(tmp, tmp, shift * 8);
|
|
| 7453 | 7428 |
op = (insn >> 20) & 7; |
| 7454 | 7429 |
switch (op) {
|
| 7455 | 7430 |
case 0: gen_sxth(tmp); break; |
| ... | ... | |
| 8346 | 8321 |
break; |
| 8347 | 8322 |
case 0x7: /* ror */ |
| 8348 | 8323 |
if (s->condexec_mask) {
|
| 8349 |
gen_helper_ror(tmp2, tmp2, tmp); |
|
| 8324 |
tcg_gen_andi_i32(tmp, tmp, 0x1f); |
|
| 8325 |
tcg_gen_rotr_i32(tmp2, tmp2, tmp); |
|
| 8350 | 8326 |
} else {
|
| 8351 | 8327 |
gen_helper_ror_cc(tmp2, tmp2, tmp); |
| 8352 | 8328 |
gen_logic_CC(tmp2); |
| ... | ... | |
| 8382 | 8358 |
gen_logic_CC(tmp); |
| 8383 | 8359 |
break; |
| 8384 | 8360 |
case 0xe: /* bic */ |
| 8385 |
tcg_gen_bic_i32(tmp, tmp, tmp2);
|
|
| 8361 |
tcg_gen_andc_i32(tmp, tmp, tmp2);
|
|
| 8386 | 8362 |
if (!s->condexec_mask) |
| 8387 | 8363 |
gen_logic_CC(tmp); |
| 8388 | 8364 |
break; |
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