Archipelago » qemu

/*

   SPARC translation

   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>

   Copyright (C) 2003-2005 Fabrice Bellard

   This library is free software; you can redistribute it and/or

   modify it under the terms of the GNU Lesser General Public

   License as published by the Free Software Foundation; either

   version 2 of the License, or (at your option) any later version.

   This library is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

   Lesser General Public License for more details.

   You should have received a copy of the GNU Lesser General Public

   License along with this library; if not, see <http://www.gnu.org/licenses/>.

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include "cpu.h"

#include "disas.h"

#include "helper.h"

#include "tcg-op.h"

#define GEN_HELPER 1

#include "helper.h"

#define DEBUG_DISAS

#define DYNAMIC_PC  1 /* dynamic pc value */

#define JUMP_PC     2 /* dynamic pc value which takes only two values

                         according to jump_pc[T2] */

/* global register indexes */

static TCGv_ptr cpu_env, cpu_regwptr;

static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;

static TCGv_i32 cpu_cc_op;

static TCGv_i32 cpu_psr;

static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];

static TCGv cpu_y;

#ifndef CONFIG_USER_ONLY

static TCGv cpu_tbr;

#endif

static TCGv cpu_cond, cpu_dst, cpu_addr, cpu_val;

#ifdef TARGET_SPARC64

static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;

static TCGv cpu_gsr;

static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;

static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;

static TCGv_i32 cpu_softint;

#else

static TCGv cpu_wim;

#endif

/* local register indexes (only used inside old micro ops) */

static TCGv cpu_tmp0;

static TCGv_i32 cpu_tmp32;

static TCGv_i64 cpu_tmp64;

/* Floating point registers */

static TCGv_i32 cpu_fpr[TARGET_FPREGS];

static target_ulong gen_opc_npc[OPC_BUF_SIZE];

static target_ulong gen_opc_jump_pc[2];

#include "gen-icount.h"

typedef struct DisasContext {

    target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */

    target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */

    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */

    int is_br;

    int mem_idx;

    int fpu_enabled;

    int address_mask_32bit;

    int singlestep;

    uint32_t cc_op;  /* current CC operation */

    struct TranslationBlock *tb;

    sparc_def_t *def;

} DisasContext;

// This function uses non-native bit order

#define GET_FIELD(X, FROM, TO)                                  \

    ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))

// This function uses the order in the manuals, i.e. bit 0 is 2^0

#define GET_FIELD_SP(X, FROM, TO)               \

    GET_FIELD(X, 31 - (TO), 31 - (FROM))

#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)

#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))

#ifdef TARGET_SPARC64

#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))

#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))

#else

#define DFPREG(r) (r & 0x1e)

#define QFPREG(r) (r & 0x1c)

#endif

#define UA2005_HTRAP_MASK 0xff

#define V8_TRAP_MASK 0x7f

static int sign_extend(int x, int len)

{

    len = 32 - len;

    return (x << len) >> len;

}

#define IS_IMM (insn & (1<<13))

/* floating point registers moves */

static void gen_op_load_fpr_DT0(unsigned int src)

{

    tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) +

                   offsetof(CPU_DoubleU, l.upper));

    tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) +

                   offsetof(CPU_DoubleU, l.lower));

}

static void gen_op_load_fpr_DT1(unsigned int src)

{

    tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) +

                   offsetof(CPU_DoubleU, l.upper));

    tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) +

                   offsetof(CPU_DoubleU, l.lower));

}

static void gen_op_store_DT0_fpr(unsigned int dst)

{

    tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) +

                   offsetof(CPU_DoubleU, l.upper));

    tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) +

                   offsetof(CPU_DoubleU, l.lower));

}

static void gen_op_load_fpr_QT0(unsigned int src)

{

    tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) +

                   offsetof(CPU_QuadU, l.upmost));

    tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +

                   offsetof(CPU_QuadU, l.upper));

    tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +

                   offsetof(CPU_QuadU, l.lower));

    tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +

                   offsetof(CPU_QuadU, l.lowest));

}

static void gen_op_load_fpr_QT1(unsigned int src)

{

    tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) +

                   offsetof(CPU_QuadU, l.upmost));

    tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +

                   offsetof(CPU_QuadU, l.upper));

    tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +

                   offsetof(CPU_QuadU, l.lower));

    tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +

                   offsetof(CPU_QuadU, l.lowest));

}

static void gen_op_store_QT0_fpr(unsigned int dst)

{

    tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) +

                   offsetof(CPU_QuadU, l.upmost));

    tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +

                   offsetof(CPU_QuadU, l.upper));

    tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +

                   offsetof(CPU_QuadU, l.lower));

    tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +

                   offsetof(CPU_QuadU, l.lowest));

}

/* moves */

#ifdef CONFIG_USER_ONLY

#define supervisor(dc) 0

#ifdef TARGET_SPARC64

#define hypervisor(dc) 0

#endif

#else

#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)

#ifdef TARGET_SPARC64

#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)

#else

#endif

#endif

#ifdef TARGET_SPARC64

#ifndef TARGET_ABI32

#define AM_CHECK(dc) ((dc)->address_mask_32bit)

#else

#define AM_CHECK(dc) (1)

#endif

#endif

static inline void gen_address_mask(DisasContext *dc, TCGv addr)

{

#ifdef TARGET_SPARC64

    if (AM_CHECK(dc))

        tcg_gen_andi_tl(addr, addr, 0xffffffffULL);

#endif

}

static inline void gen_movl_reg_TN(int reg, TCGv tn)

{

    if (reg == 0)

        tcg_gen_movi_tl(tn, 0);

    else if (reg < 8)

        tcg_gen_mov_tl(tn, cpu_gregs[reg]);

    else {

        tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));

    }

}

static inline void gen_movl_TN_reg(int reg, TCGv tn)

{

    if (reg == 0)

        return;

    else if (reg < 8)

        tcg_gen_mov_tl(cpu_gregs[reg], tn);

    else {

        tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));

    }

}

static inline void gen_goto_tb(DisasContext *s, int tb_num,

                               target_ulong pc, target_ulong npc)

{

    TranslationBlock *tb;

    tb = s->tb;

    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&

        (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&

        !s->singlestep)  {

        /* jump to same page: we can use a direct jump */

        tcg_gen_goto_tb(tb_num);

        tcg_gen_movi_tl(cpu_pc, pc);

        tcg_gen_movi_tl(cpu_npc, npc);

        tcg_gen_exit_tb((tcg_target_long)tb + tb_num);

    } else {

        /* jump to another page: currently not optimized */

        tcg_gen_movi_tl(cpu_pc, pc);

        tcg_gen_movi_tl(cpu_npc, npc);

        tcg_gen_exit_tb(0);

    }

}

// XXX suboptimal

static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)

{

    tcg_gen_extu_i32_tl(reg, src);

    tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);

    tcg_gen_andi_tl(reg, reg, 0x1);

}

static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)

{

    tcg_gen_extu_i32_tl(reg, src);

    tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);

    tcg_gen_andi_tl(reg, reg, 0x1);

}

static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)

{

    tcg_gen_extu_i32_tl(reg, src);

    tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);

    tcg_gen_andi_tl(reg, reg, 0x1);

}

static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)

{

    tcg_gen_extu_i32_tl(reg, src);

    tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);

    tcg_gen_andi_tl(reg, reg, 0x1);

}

static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)

{

    TCGv r_temp;

    TCGv_i32 r_const;

    int l1;

    l1 = gen_new_label();

    r_temp = tcg_temp_new();

    tcg_gen_xor_tl(r_temp, src1, src2);

    tcg_gen_not_tl(r_temp, r_temp);

    tcg_gen_xor_tl(cpu_tmp0, src1, dst);

    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);

    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));

    tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);

    r_const = tcg_const_i32(TT_TOVF);

    gen_helper_raise_exception(r_const);

    tcg_temp_free_i32(r_const);

    gen_set_label(l1);

    tcg_temp_free(r_temp);

}

static inline void gen_tag_tv(TCGv src1, TCGv src2)

{

    int l1;

    TCGv_i32 r_const;

    l1 = gen_new_label();

    tcg_gen_or_tl(cpu_tmp0, src1, src2);

    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);

    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);

    r_const = tcg_const_i32(TT_TOVF);

    gen_helper_raise_exception(r_const);

    tcg_temp_free_i32(r_const);

    gen_set_label(l1);

}

static inline void gen_op_addi_cc(TCGv dst, TCGv src1, target_long src2)

{

    tcg_gen_mov_tl(cpu_cc_src, src1);

    tcg_gen_movi_tl(cpu_cc_src2, src2);

    tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_src, src2);

    tcg_gen_mov_tl(dst, cpu_cc_dst);

}

static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)

{

    tcg_gen_mov_tl(cpu_cc_src, src1);

    tcg_gen_mov_tl(cpu_cc_src2, src2);

    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

    tcg_gen_mov_tl(dst, cpu_cc_dst);

}

static TCGv_i32 gen_add32_carry32(void)

{

    TCGv_i32 carry_32, cc_src1_32, cc_src2_32;

    /* Carry is computed from a previous add: (dst < src)  */

#if TARGET_LONG_BITS == 64

    cc_src1_32 = tcg_temp_new_i32();

    cc_src2_32 = tcg_temp_new_i32();

    tcg_gen_trunc_i64_i32(cc_src1_32, cpu_cc_dst);

    tcg_gen_trunc_i64_i32(cc_src2_32, cpu_cc_src);

#else

    cc_src1_32 = cpu_cc_dst;

    cc_src2_32 = cpu_cc_src;

#endif

    carry_32 = tcg_temp_new_i32();

    tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);

#if TARGET_LONG_BITS == 64

    tcg_temp_free_i32(cc_src1_32);

    tcg_temp_free_i32(cc_src2_32);

#endif

    return carry_32;

}

static TCGv_i32 gen_sub32_carry32(void)

{

    TCGv_i32 carry_32, cc_src1_32, cc_src2_32;

    /* Carry is computed from a previous borrow: (src1 < src2)  */

#if TARGET_LONG_BITS == 64

    cc_src1_32 = tcg_temp_new_i32();

    cc_src2_32 = tcg_temp_new_i32();

    tcg_gen_trunc_i64_i32(cc_src1_32, cpu_cc_src);

    tcg_gen_trunc_i64_i32(cc_src2_32, cpu_cc_src2);

#else

    cc_src1_32 = cpu_cc_src;

    cc_src2_32 = cpu_cc_src2;

#endif

    carry_32 = tcg_temp_new_i32();

    tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);

#if TARGET_LONG_BITS == 64

    tcg_temp_free_i32(cc_src1_32);

    tcg_temp_free_i32(cc_src2_32);

#endif

    return carry_32;

}

static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,

                            TCGv src2, int update_cc)

{

    TCGv_i32 carry_32;

    TCGv carry;

    switch (dc->cc_op) {

    case CC_OP_DIV:

    case CC_OP_LOGIC:

        /* Carry is known to be zero.  Fall back to plain ADD.  */

        if (update_cc) {

            gen_op_add_cc(dst, src1, src2);

        } else {

            tcg_gen_add_tl(dst, src1, src2);

        }

        return;

    case CC_OP_ADD:

    case CC_OP_TADD:

    case CC_OP_TADDTV:

#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32

        {

            /* For 32-bit hosts, we can re-use the host's hardware carry

               generation by using an ADD2 opcode.  We discard the low

               part of the output.  Ideally we'd combine this operation

               with the add that generated the carry in the first place.  */

            TCGv dst_low = tcg_temp_new();

            tcg_gen_op6_i32(INDEX_op_add2_i32, dst_low, dst,

                            cpu_cc_src, src1, cpu_cc_src2, src2);

            tcg_temp_free(dst_low);

            goto add_done;

        }

#endif

        carry_32 = gen_add32_carry32();

        break;

    case CC_OP_SUB:

    case CC_OP_TSUB:

    case CC_OP_TSUBTV:

        carry_32 = gen_sub32_carry32();

        break;

    default:

        /* We need external help to produce the carry.  */

        carry_32 = tcg_temp_new_i32();

        gen_helper_compute_C_icc(carry_32);

        break;

    }

#if TARGET_LONG_BITS == 64

    carry = tcg_temp_new();

    tcg_gen_extu_i32_i64(carry, carry_32);

#else

    carry = carry_32;

#endif

    tcg_gen_add_tl(dst, src1, src2);

    tcg_gen_add_tl(dst, dst, carry);

    tcg_temp_free_i32(carry_32);

#if TARGET_LONG_BITS == 64

    tcg_temp_free(carry);

#endif

#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32

 add_done:

#endif

    if (update_cc) {

        tcg_gen_mov_tl(cpu_cc_src, src1);

        tcg_gen_mov_tl(cpu_cc_src2, src2);

        tcg_gen_mov_tl(cpu_cc_dst, dst);

        tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);

        dc->cc_op = CC_OP_ADDX;

    }

}

static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)

{

    tcg_gen_mov_tl(cpu_cc_src, src1);

    tcg_gen_mov_tl(cpu_cc_src2, src2);

    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

    tcg_gen_mov_tl(dst, cpu_cc_dst);

}

static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)

{

    tcg_gen_mov_tl(cpu_cc_src, src1);

    tcg_gen_mov_tl(cpu_cc_src2, src2);

    gen_tag_tv(cpu_cc_src, cpu_cc_src2);

    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

    gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

    tcg_gen_mov_tl(dst, cpu_cc_dst);

}

static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)

{

    TCGv r_temp;

    TCGv_i32 r_const;

    int l1;

    l1 = gen_new_label();

    r_temp = tcg_temp_new();

    tcg_gen_xor_tl(r_temp, src1, src2);

    tcg_gen_xor_tl(cpu_tmp0, src1, dst);

    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);

    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));

    tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);

    r_const = tcg_const_i32(TT_TOVF);

    gen_helper_raise_exception(r_const);

    tcg_temp_free_i32(r_const);

    gen_set_label(l1);

    tcg_temp_free(r_temp);

}

static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2, DisasContext *dc)

{

    tcg_gen_mov_tl(cpu_cc_src, src1);

    tcg_gen_movi_tl(cpu_cc_src2, src2);

    if (src2 == 0) {

        tcg_gen_mov_tl(cpu_cc_dst, src1);

        tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);

        dc->cc_op = CC_OP_LOGIC;

    } else {

        tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2);

        tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);

        dc->cc_op = CC_OP_SUB;

    }

    tcg_gen_mov_tl(dst, cpu_cc_dst);

}

static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)

{

    tcg_gen_mov_tl(cpu_cc_src, src1);

    tcg_gen_mov_tl(cpu_cc_src2, src2);

    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

    tcg_gen_mov_tl(dst, cpu_cc_dst);

}

static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,

                            TCGv src2, int update_cc)

{

    TCGv_i32 carry_32;

    TCGv carry;

    switch (dc->cc_op) {

    case CC_OP_DIV:

    case CC_OP_LOGIC:

        /* Carry is known to be zero.  Fall back to plain SUB.  */

        if (update_cc) {

            gen_op_sub_cc(dst, src1, src2);

        } else {

            tcg_gen_sub_tl(dst, src1, src2);

        }

        return;

    case CC_OP_ADD:

    case CC_OP_TADD:

    case CC_OP_TADDTV:

        carry_32 = gen_add32_carry32();

        break;

    case CC_OP_SUB:

    case CC_OP_TSUB:

    case CC_OP_TSUBTV:

#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32

        {

            /* For 32-bit hosts, we can re-use the host's hardware carry

               generation by using a SUB2 opcode.  We discard the low

               part of the output.  Ideally we'd combine this operation

               with the add that generated the carry in the first place.  */

            TCGv dst_low = tcg_temp_new();

            tcg_gen_op6_i32(INDEX_op_sub2_i32, dst_low, dst,

                            cpu_cc_src, src1, cpu_cc_src2, src2);

            tcg_temp_free(dst_low);

            goto sub_done;

        }

#endif

        carry_32 = gen_sub32_carry32();

        break;

    default:

        /* We need external help to produce the carry.  */

        carry_32 = tcg_temp_new_i32();

        gen_helper_compute_C_icc(carry_32);

        break;

    }

#if TARGET_LONG_BITS == 64

    carry = tcg_temp_new();

    tcg_gen_extu_i32_i64(carry, carry_32);

#else

    carry = carry_32;

#endif

    tcg_gen_sub_tl(dst, src1, src2);

    tcg_gen_sub_tl(dst, dst, carry);

    tcg_temp_free_i32(carry_32);

#if TARGET_LONG_BITS == 64

    tcg_temp_free(carry);

#endif

#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32

 sub_done:

#endif

    if (update_cc) {

        tcg_gen_mov_tl(cpu_cc_src, src1);

        tcg_gen_mov_tl(cpu_cc_src2, src2);

        tcg_gen_mov_tl(cpu_cc_dst, dst);

        tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);

        dc->cc_op = CC_OP_SUBX;

    }

}

static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)

{

    tcg_gen_mov_tl(cpu_cc_src, src1);

    tcg_gen_mov_tl(cpu_cc_src2, src2);

    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

    tcg_gen_mov_tl(dst, cpu_cc_dst);

}

static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)

{

    tcg_gen_mov_tl(cpu_cc_src, src1);

    tcg_gen_mov_tl(cpu_cc_src2, src2);

    gen_tag_tv(cpu_cc_src, cpu_cc_src2);

    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

    gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

    tcg_gen_mov_tl(dst, cpu_cc_dst);

}

static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)

{

    TCGv r_temp;

    int l1;

    l1 = gen_new_label();

    r_temp = tcg_temp_new();

    /* old op:

    if (!(env->y & 1))

        T1 = 0;

    */

    tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);

    tcg_gen_andi_tl(r_temp, cpu_y, 0x1);

    tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);

    tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);

    tcg_gen_movi_tl(cpu_cc_src2, 0);

    gen_set_label(l1);

    // b2 = T0 & 1;

    // env->y = (b2 << 31) | (env->y >> 1);

    tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);

    tcg_gen_shli_tl(r_temp, r_temp, 31);

    tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);

    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x7fffffff);

    tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp);

    tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);

    // b1 = N ^ V;

    gen_mov_reg_N(cpu_tmp0, cpu_psr);

    gen_mov_reg_V(r_temp, cpu_psr);

    tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);

    tcg_temp_free(r_temp);

    // T0 = (b1 << 31) | (T0 >> 1);

    // src1 = T0;

    tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);

    tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);

    tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);

    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

    tcg_gen_mov_tl(dst, cpu_cc_dst);

}

static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)

{

    TCGv_i32 r_src1, r_src2;

    TCGv_i64 r_temp, r_temp2;

    r_src1 = tcg_temp_new_i32();

    r_src2 = tcg_temp_new_i32();

    tcg_gen_trunc_tl_i32(r_src1, src1);

    tcg_gen_trunc_tl_i32(r_src2, src2);

    r_temp = tcg_temp_new_i64();

    r_temp2 = tcg_temp_new_i64();

    if (sign_ext) {

        tcg_gen_ext_i32_i64(r_temp, r_src2);

        tcg_gen_ext_i32_i64(r_temp2, r_src1);

    } else {

        tcg_gen_extu_i32_i64(r_temp, r_src2);

        tcg_gen_extu_i32_i64(r_temp2, r_src1);

    }

    tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);

    tcg_gen_shri_i64(r_temp, r_temp2, 32);

    tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);

    tcg_temp_free_i64(r_temp);

    tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);

    tcg_gen_trunc_i64_tl(dst, r_temp2);

    tcg_temp_free_i64(r_temp2);

    tcg_temp_free_i32(r_src1);

    tcg_temp_free_i32(r_src2);

}

static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)

{

    /* zero-extend truncated operands before multiplication */

    gen_op_multiply(dst, src1, src2, 0);

}

static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)

{

    /* sign-extend truncated operands before multiplication */

    gen_op_multiply(dst, src1, src2, 1);

}

#ifdef TARGET_SPARC64

static inline void gen_trap_ifdivzero_tl(TCGv divisor)

{

    TCGv_i32 r_const;

    int l1;

    l1 = gen_new_label();

    tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);

    r_const = tcg_const_i32(TT_DIV_ZERO);

    gen_helper_raise_exception(r_const);

    tcg_temp_free_i32(r_const);

    gen_set_label(l1);

}

static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)

{

    int l1, l2;

    TCGv r_temp1, r_temp2;

    l1 = gen_new_label();

    l2 = gen_new_label();

    r_temp1 = tcg_temp_local_new();

    r_temp2 = tcg_temp_local_new();

    tcg_gen_mov_tl(r_temp1, src1);

    tcg_gen_mov_tl(r_temp2, src2);

    gen_trap_ifdivzero_tl(r_temp2);

    tcg_gen_brcondi_tl(TCG_COND_NE, r_temp1, INT64_MIN, l1);

    tcg_gen_brcondi_tl(TCG_COND_NE, r_temp2, -1, l1);

    tcg_gen_movi_i64(dst, INT64_MIN);

    tcg_gen_br(l2);

    gen_set_label(l1);

    tcg_gen_div_i64(dst, r_temp1, r_temp2);

    gen_set_label(l2);

    tcg_temp_free(r_temp1);

    tcg_temp_free(r_temp2);

}

#endif

// 1

static inline void gen_op_eval_ba(TCGv dst)

{

    tcg_gen_movi_tl(dst, 1);

}

// Z

static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)

{

    gen_mov_reg_Z(dst, src);

}

// Z | (N ^ V)

static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)

{

    gen_mov_reg_N(cpu_tmp0, src);

    gen_mov_reg_V(dst, src);

    tcg_gen_xor_tl(dst, dst, cpu_tmp0);

    gen_mov_reg_Z(cpu_tmp0, src);

    tcg_gen_or_tl(dst, dst, cpu_tmp0);

}

// N ^ V

static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)

{

    gen_mov_reg_V(cpu_tmp0, src);

    gen_mov_reg_N(dst, src);

    tcg_gen_xor_tl(dst, dst, cpu_tmp0);

}

// C | Z

static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)

{

    gen_mov_reg_Z(cpu_tmp0, src);

    gen_mov_reg_C(dst, src);

    tcg_gen_or_tl(dst, dst, cpu_tmp0);

}

// C

static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)

{

    gen_mov_reg_C(dst, src);

}

// V

static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)

{

    gen_mov_reg_V(dst, src);

}

// 0

static inline void gen_op_eval_bn(TCGv dst)

{

    tcg_gen_movi_tl(dst, 0);

}

// N

static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)

{

    gen_mov_reg_N(dst, src);

}

// !Z

static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)

{

    gen_mov_reg_Z(dst, src);

    tcg_gen_xori_tl(dst, dst, 0x1);

}

// !(Z | (N ^ V))

static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)

{

    gen_mov_reg_N(cpu_tmp0, src);

    gen_mov_reg_V(dst, src);

    tcg_gen_xor_tl(dst, dst, cpu_tmp0);

    gen_mov_reg_Z(cpu_tmp0, src);

    tcg_gen_or_tl(dst, dst, cpu_tmp0);

    tcg_gen_xori_tl(dst, dst, 0x1);

}

// !(N ^ V)

static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)

{

    gen_mov_reg_V(cpu_tmp0, src);

    gen_mov_reg_N(dst, src);

    tcg_gen_xor_tl(dst, dst, cpu_tmp0);

    tcg_gen_xori_tl(dst, dst, 0x1);

}

// !(C | Z)

static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)

{

    gen_mov_reg_Z(cpu_tmp0, src);

    gen_mov_reg_C(dst, src);

    tcg_gen_or_tl(dst, dst, cpu_tmp0);

    tcg_gen_xori_tl(dst, dst, 0x1);

}

// !C

static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)

{

    gen_mov_reg_C(dst, src);

    tcg_gen_xori_tl(dst, dst, 0x1);

}

// !N

static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)

{

    gen_mov_reg_N(dst, src);

    tcg_gen_xori_tl(dst, dst, 0x1);

}

// !V

static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)

{

    gen_mov_reg_V(dst, src);

    tcg_gen_xori_tl(dst, dst, 0x1);

}

/*

  FPSR bit field FCC1 | FCC0:

   0 =

   1 <

   2 >

   3 unordered

*/

static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,

                                    unsigned int fcc_offset)

{

    tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);

    tcg_gen_andi_tl(reg, reg, 0x1);

}

static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,

                                    unsigned int fcc_offset)

{

    tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);

    tcg_gen_andi_tl(reg, reg, 0x1);

}

// !0: FCC0 | FCC1

static inline void gen_op_eval_fbne(TCGv dst, TCGv src,

                                    unsigned int fcc_offset)

{

    gen_mov_reg_FCC0(dst, src, fcc_offset);

    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);

    tcg_gen_or_tl(dst, dst, cpu_tmp0);

}

// 1 or 2: FCC0 ^ FCC1

static inline void gen_op_eval_fblg(TCGv dst, TCGv src,

                                    unsigned int fcc_offset)

{

    gen_mov_reg_FCC0(dst, src, fcc_offset);

    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);

    tcg_gen_xor_tl(dst, dst, cpu_tmp0);

}

// 1 or 3: FCC0

static inline void gen_op_eval_fbul(TCGv dst, TCGv src,

                                    unsigned int fcc_offset)

{

    gen_mov_reg_FCC0(dst, src, fcc_offset);

}

// 1: FCC0 & !FCC1

static inline void gen_op_eval_fbl(TCGv dst, TCGv src,

                                    unsigned int fcc_offset)