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SPARC64: C99 comment fix for block-transfer ASIs
Fixed C99 comments on block-tranfer ASIs.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
SPARC64: Add JPS1 ASI_BLK_AIU[PS]L ASIs for ldfa and stfa
Support JPS1 little endian block transfer ASIs.
SPARC64: Add UA2007 ASI_BLK_AIU[PS]L? ASIs for stfa
Support UA2007 block store ASIs for stfa instructions.
SPARC64: Add UA2007 ASI_BLK_AIU[PS]L? ASIs for ldfa
Support UA2007 block load ASIs for ldfa instructions.
SPARC64: Implement stfa/stdfa/stqfa instrcutions properly
This patch implements sparcv9 stfa/stdfa/stqfa instructionswith non block-store ASIs.
SPARC64: Implement ldfa/lddfa/ldqfa instructions properly
This patch implements sparcv9 ldfa/lddfa/ldqfa instructionswith non block-load ASIs.
sparc: move do_interrupt to helper.c
do_interrupt() was mixing CPUState pointer passed from callerand global env (AREG0).
Fix by moving the function to helper.c. Introduce a helper for callingchange_pstate() safely from outside of execution context.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc: fix coding style of the area to be moved
Before the next patch, fix coding style of the areas affected.
cpu_loop_exit: avoid using AREG0
Make cpu_loop_exit() take a parameter for CPUState instead of relyingon global env.
Sparc32: dummy implementation of MXCC MMU breakpoint registers
Add dummy registers for SuperSPARC MXCC MMU counter breakpoints, saveand load all MXCC registers.
Delete unused tb_invalidate_page_range
tb_invalidate_page_range() was intended to be used to invalidate anarea of a TB which the guest explicitly flushes from i-cache. However,QEMU detects writes to code areas where TBs have been generated, sohis has never been useful....
Remove unused function parameter from cpu_restore_state
The previous patch removed the need for parameter puc.Is is now unused, so remove it.
Cc: Aurelien Jarno <aurelien@aurel32.net>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Weil <weil@mail.berlios.de>
SPARC: Fix Leon3 cache control
The "leon3_cache_control_int" (op_helper.c) function is called within leon3.cwhich leads to segfault error with the global "env".
Now cache control is a CPU feature and everything is handled in op_helper.c.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>...
SPARC: Emulation of Leon3
Leon3 is an open-source VHDL System-On-Chip, well known in space industry (moreinformation on http://www.gaisler.com).
Leon3 is made of multiple components available in the GrLib VHDL library.Three devices are implemented: uart, timers and IRQ manager....
sparc: fix NaN handling
Fix several bugs in NaN handling: * e in fcmpe* only changes qNaN handling * FCC is unchanged if an exception is raised * clear previous FTT before setting it
Reported-by: Mateusz Loskot <mateusz@loskot.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sparc: fix udiv(cc) and sdiv(cc)
Since commit 5a4bb580cdb10b066f9fd67658b31cac4a4ea5e5, Xorg crashes ona Debian Etch image. The commit itself is fine, but it triggers a bugdue to wrong computation of flags for udiv(cc) and sdiv(cc).
This patch only compute cc_src2 for the cc version of udiv/sdiv. It...
Sparc: implement monitor command 'info tlb'
Use existing dump_mmu() to implement monitor command 'info tlb'.
sparc64: fix udiv and sdiv insns
- truncate second operand to 32bit
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc64: improve ldf and stf insns
- implemented block load/store primary/secondary with user privilege
sparc64: use symbolic name for MMU index v1
- use symbolic name for MMU indexv0->v1:- change debug traces to DPRINTF_MMU- fix debug trace function names
sparc64: fix missing address masking v1
- address masking for ldqf and stqf insns- address masking for lddf and stdf insns- address masking for translating ASI (Ultrasparc IIi)v0->v1:- move arch-specific code to helpers and drop more ifdefs at call sites...
sparc32 SuperSPARC MMU Breakpoint Action register (SS-20 OBP fix)
SuperSPARC MMU Breakpoint Action register is used by OBP at boot
The patch allows booting Solaris and some other OS withSPARCStation-20 OBP.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>...
sparc64: fix user emulator build
Accesses with _nucleus prefix are not available when building useremulators: CC sparc64-linux-user/op_helper.occ1: warnings being treated as errors/src/qemu/target-sparc/op_helper.c: In function 'helper_ldda_asi':...
sparc64: fix 128-bit atomic load from nucleus context v1
- change 128-bit atomic loads to reference nucleus contextv0->v1: dropped disassembler changeSigned-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc64: flush translations on mmu context change
- two pairs of softmmu indexes bind softmmu tlb to cpu tlb in fault handlers using value of DMMU primary and secondary context registers, so we need to flush softmmu translations when context registers are changed...
sparc64: fix pstate privilege bits
- refactor code to handle hpstate only if available for current cpu- conditionally set hypervisor bit in hpstate register- reorder softmmu indices so user accessable ones go first, translation context macros supervisor() and hypervisor() adjusted as well...
target-sparc: Inline some generation of carry for ADDX/SUBX.
Computing carry is trivial for some inputs. By avoiding anexternal function call, we generate near-optimal code forthe common cases of add+addx (double-word arithmetic) andcmp+addx (a setcc pattern)....
target-sparc: Simplify ICC generation.
Use int32 types instead of target_ulong when computing ICC. Thissimplifies the generated code for 32-bit host and 64-bit guest.Use the same simplified expressions for ICC as were already usedfor XCC in carry flag generation....
target-sparc: Fix compilation with --enable-debug.
Return a target_ulong from compute_C_icc to match the width of the users.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc: move DT and QT defines to op_helper.c
sparc64: fix mmu demap operand typo
- must use store address operand to demap, not store value
sparc: Fix lazy flag calculation on interrupts, refactor
Recalculate Sparc64 CPU flags on interrupts, otherwise some earlierflags could be stored to pstate.
Refactor PSR/CCR/CWP handling: concentrate the actualfunctions to op_helper.c.
Thanks to Igor Kovalenko for reporting....
sparc64: handle asi referencing nucleus and secondary MMU contexts
- increase max supported MMU modes to 6- handle nucleus context asi- handle secondary context asi- handle non-faulting loads from secondary context
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>...
sparc64: implement global translation table entries v1
- match global tte against any context- show global tte in MMU dump
v0->v1: added default case to switch statement in demap_tlb- should fix gcc warning about uninitialized context variable
target-sparc: Fix address masking in ldqf and stqf.
Use address_mask on both addr and addr+8 in both these routines,rather than explicit masking with 0xffffffff.
Reformulate address_mask to return a result, rather than maskinga pass-by-reference argument....
Target specific usermode cleanup
Disable various target specific code that is only relevant to system emulation.
Signed-off-by: Paul Brook <paul@codesourcery.com>
sparc32 fix np dereference in do_unassigned_access
fix a potential null pointer dereference introduced incommit 576c2cdc767ab9e2dc038fa4c99f22e53287a3de
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc32 do_unassigned_access overhaul v2
According to pages 9-31 - 9-34 of "SuperSPARC & MultiCache ControllerUser's Manual":
1. "A lower priority fault may not overwrite the MFSR status of a higher priority fault." 2. The MFAR is overwritten according to the policy defined for the MFSR...
sparc64: check for pending irq when pil, pstate or softint is changed
sparc64: use helper_wrpil to check pending irq on write
sparc64: trace pstate and global register set changes
sparc64: change_pstate should have 32bit argument
- pstate is 32bit variable, no need to pass 64bit value around
Sparc32: clear exception_index with -1 value
See also 821b19fe923ac49a24cdb4af902584fdd019cee6.
Spotted by Artyom Tarasenko and Igor Kovalenko.
sparc64: clear exception_index with -1 value
pass env to raise_exception if called outside of op_helper code
- this fixes stepping with gdb, where do_unassigned_access may be called from gdb handler, outside of generated code
sparc64: switch to MMU global registers in more MMU related traps
- extended range of MMU related traps which use MMU global registers, as listed in Ultrasparc-IIi document- no visible changes, since emulation do not cause added traps
Sparc: fix carry flag handling (Solaris bootblk fix)
The page 108 of the SPARC Version 8 Architecture Manual describesthat addcc and addxcc shall compute carry flag the same way.The page 110 claims the same about subcc and subxcc instructions.This patch fixes carry computation in corner cases and removes redundant code....
sparc64: fix done instruction pc
Fix done instruction to resume with pc=tnpc, npc=tnpc+4
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
sparc64-8bit-asi
Sparc64 alternate space load/store helpers expect 8 bit ASI value,while wrasi implementation sign-extends ASI operand causingfor example 0x80 to appear as 0xFFFFFF80. Resulting value fallsout of switch in helpers and causes obscure load/store faults....
Sparc64: replace tsptr with helper routine
tl and tsptr of members sparc64 cpu state must be changedsimultaneously to keep trap state window in sync with currenttrap level. Currently translation of store to tl does not changetsptr, which leads to corrupt trap state on corresponding...
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
sparc64 really implement itlb/dtlb automatic replacement writes
- implement "used" bit in tlb translation entry- mark tlb entry used if qemu code/data translation succeeds- fold i/d mmu replacement writes code into replace_tlb_1bit_lru whichadds 1bit lru replacement algorithm; previously code tried to replace...
sparc64 name mmu registers and general cleanup
- add names to mmu registers, this helps understanding the code whichuses/modifies them.- fold i/d mmu tlb entries tag and tte arrays into arrays of tlb entries- extract demap_tlb routine (code duplication)...
Fix most warnings (errors with -Werror) when debugging is enabled
I used the following command to enable debugging:perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * /* *//*
sparc64: trap handling corrections
On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote:
On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote: Good trap handling is required to process interrupts. This patch fixes the following:...
On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
Good trap handling is required to process interrupts. This patch fixes the following:...
sparc64: fix helper_st_asi little endian case typo
On Sun, Jul 12, 2009 at 12:43 AM, Stuart Brady<sdbrady@ntlworld.com> wrote:
On Sat, Jul 11, 2009 at 10:22:18PM +0400, Igor Kovalenko wrote: It is clear that intention is to byte-swap value to be written, not...
On Sat, Jul 11, 2009 at 10:22:18PM +0400, Igor Kovalenko wrote:
It is clear that intention is to byte-swap value to be written, not...
Replace gcc variadic macro extension with C99 version
Convert udiv/sdiv
Convert tagged ops
Convert logical operations and umul/smul
Convert sub
Convert subx
Convert addx
Convert add
Use dynamical computation for condition codes
Fix a warning in sparc64-linux-user build
sparc64 support TSB related MMU registers
Posting updated patch to the list...
On Fri, Apr 24, 2009 at 9:42 PM, Blue Swirl <blauwirbel@gmail.com> wrote: > > Nice, though I didn't notice any visible improvement in my tests. This early in boot process there is not much to output; and I test...
On Fri, Apr 24, 2009 at 9:42 PM, Blue Swirl <blauwirbel@gmail.com> wrote: > > Nice, though I didn't notice any visible improvement in my tests.
This early in boot process there is not much to output; and I test...
Delete some unused macros detected with -Wp,-Wunused-macros use
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6856 c046a42c-6fe2-441c-8c8c-71466251a162
global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &X) qemu_log()' statement.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevelglobal variables to use the new qemu_log*() macros.
Add SuperSPARC MMU breakpoint registers (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6125 c046a42c-6fe2-441c-8c8c-71466251a162
Add missing "static"
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5977 c046a42c-6fe2-441c-8c8c-71466251a162
TCG variable type checking.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
Fix error in fexpand (spotted by sparse)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5438 c046a42c-6fe2-441c-8c8c-71466251a162
Show size for unassigned accesses (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5436 c046a42c-6fe2-441c-8c8c-71466251a162
Rearrange tick functions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5408 c046a42c-6fe2-441c-8c8c-71466251a162
Fix MXCC printf warning (based on patch by Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5393 c046a42c-6fe2-441c-8c8c-71466251a162
Add mmu tlb demap support (Igor Kovalenko)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5332 c046a42c-6fe2-441c-8c8c-71466251a162
Implement some UA2007 block ASIs
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5328 c046a42c-6fe2-441c-8c8c-71466251a162
Implement UA2005 hypervisor traps
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5327 c046a42c-6fe2-441c-8c8c-71466251a162
Move also DEBUG_PCALL (see r5085)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5326 c046a42c-6fe2-441c-8c8c-71466251a162
Add software and timer interrupt support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5299 c046a42c-6fe2-441c-8c8c-71466251a162
Fix arguments used in cas/casx, thanks to Igor Kovalenko for spotting
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5296 c046a42c-6fe2-441c-8c8c-71466251a162
Use the new concat_i32_i64 op for std and stda
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5281 c046a42c-6fe2-441c-8c8c-71466251a162
Fix array subscript above array bounds error
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5219 c046a42c-6fe2-441c-8c8c-71466251a162
Convert rest of ops using float32 to TCG, remove FT0 and FT1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5193 c046a42c-6fe2-441c-8c8c-71466251a162
Partially convert float128 conversion ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5192 c046a42c-6fe2-441c-8c8c-71466251a162
Convert basic 64 bit VIS ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5191 c046a42c-6fe2-441c-8c8c-71466251a162
Convert basic 32 bit VIS ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5190 c046a42c-6fe2-441c-8c8c-71466251a162
Convert basic float32 ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5189 c046a42c-6fe2-441c-8c8c-71466251a162
Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5185 c046a42c-6fe2-441c-8c8c-71466251a162
Implement no-fault loads
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5148 c046a42c-6fe2-441c-8c8c-71466251a162
Fix Sparc64 boot on i386 host: - move do_interrupt() back to op_helper.c - move non-helper prototypes from helper.h to exec.h - move some prototypes from cpu.h to exec.h - do not export either set_cwp() or cpu_set_cwp() from op_helper.c, but instead provide inline functions...
Fix udiv and sdiv on Sparc64 (Vince Weaver)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5085 c046a42c-6fe2-441c-8c8c-71466251a162
Use initial CPU definition structure for some CPU fields instead of copyingthem around, based on patch by Luis Pureza.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5042 c046a42c-6fe2-441c-8c8c-71466251a162
Fix faligndata (Vince Weaver)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4992 c046a42c-6fe2-441c-8c8c-71466251a162
Fix I/D MMU tag reads
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4991 c046a42c-6fe2-441c-8c8c-71466251a162
Make MAXTL dynamic, bounds check tl when indexing
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4942 c046a42c-6fe2-441c-8c8c-71466251a162