Revision f838e2c5

b/target-sparc/cpu.h
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#endif
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}
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static inline int cpu_fpu_enabled(CPUState *env1)
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{
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#if defined(CONFIG_USER_ONLY)
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    return 1;
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#elif !defined(TARGET_SPARC64)
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    return env1->psref;
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#else
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    return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
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#endif
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}
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#if defined(CONFIG_USER_ONLY)
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static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
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{
......
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trap_state* cpu_tsptr(CPUState* env);
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#endif
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#define TB_FLAG_FPU_ENABLED (1 << 4)
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#define TB_FLAG_AM_ENABLED (1 << 5)
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static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
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                                        target_ulong *cs_base, int *flags)
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{
......
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    *cs_base = env->npc;
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#ifdef TARGET_SPARC64
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    // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
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    *flags = ((env->pstate & PS_AM) << 2)          /* 5 */
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        | (((env->pstate & PS_PEF) >> 1)           /* 3 */
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        | ((env->fprs & FPRS_FEF) << 2))           /* 4 */
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        | (env->pstate & PS_PRIV)                  /* 2 */
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    *flags = (env->pstate & PS_PRIV)               /* 2 */
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        | ((env->lsu & (DMMU_E | IMMU_E)) >> 2)    /* 1, 0 */
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        | ((env->tl & 0xff) << 8)
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        | (env->dmmu.mmu_primary_context << 16);   /* 16... */
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    if (env->pstate & PS_AM) {
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        *flags |= TB_FLAG_AM_ENABLED;
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    }
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    if ((env->def->features & CPU_FEATURE_FLOAT) && (env->pstate & PS_PEF)
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        && (env->fprs & FPRS_FEF)) {
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        *flags |= TB_FLAG_FPU_ENABLED;
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    }
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#else
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    // FPU enable . Supervisor
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    *flags = (env->psref << 4) | env->psrs;
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    *flags = env->psrs;
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    if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
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        *flags |= TB_FLAG_FPU_ENABLED;
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    }
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#endif
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}
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static inline bool tb_fpu_enabled(int tb_flags)
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{
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#if defined(CONFIG_USER_ONLY)
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    return true;
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#else
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    return tb_flags & TB_FLAG_FPU_ENABLED;
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#endif
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}
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static inline bool tb_am_enabled(int tb_flags)
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{
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#ifndef TARGET_SPARC64
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    return false;
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#else
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    return tb_flags & TB_FLAG_AM_ENABLED;
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#endif
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}
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b/target-sparc/translate.c
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    dc->cc_op = CC_OP_DYNAMIC;
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    dc->mem_idx = cpu_mmu_index(env);
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    dc->def = env->def;
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    if ((dc->def->features & CPU_FEATURE_FLOAT))
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        dc->fpu_enabled = cpu_fpu_enabled(env);
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    else
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        dc->fpu_enabled = 0;
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#ifdef TARGET_SPARC64
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    dc->address_mask_32bit = env->pstate & PS_AM;
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#endif
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    dc->fpu_enabled = tb_fpu_enabled(tb->flags);
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    dc->address_mask_32bit = tb_am_enabled(tb->flags);
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    dc->singlestep = (env->singlestep_enabled || singlestep);
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    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
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