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1
/*
2
   SPARC translation
3

4
   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5
   Copyright (C) 2003-2005 Fabrice Bellard
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7
   This library is free software; you can redistribute it and/or
8
   modify it under the terms of the GNU Lesser General Public
9
   License as published by the Free Software Foundation; either
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   version 2 of the License, or (at your option) any later version.
11

12
   This library is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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   Lesser General Public License for more details.
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   You should have received a copy of the GNU Lesser General Public
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   License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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21
#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
26

    
27
#include "cpu.h"
28
#include "disas.h"
29
#include "helper.h"
30
#include "tcg-op.h"
31

    
32
#define GEN_HELPER 1
33
#include "helper.h"
34

    
35
#define DEBUG_DISAS
36

    
37
#define DYNAMIC_PC  1 /* dynamic pc value */
38
#define JUMP_PC     2 /* dynamic pc value which takes only two values
39
                         according to jump_pc[T2] */
40

    
41
/* global register indexes */
42
static TCGv_ptr cpu_env, cpu_regwptr;
43
static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
44
static TCGv_i32 cpu_cc_op;
45
static TCGv_i32 cpu_psr;
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static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
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static TCGv cpu_y;
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#ifndef CONFIG_USER_ONLY
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static TCGv cpu_tbr;
50
#endif
51
static TCGv cpu_cond, cpu_dst, cpu_addr, cpu_val;
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#ifdef TARGET_SPARC64
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static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
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static TCGv cpu_gsr;
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static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
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static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
57
static TCGv_i32 cpu_softint;
58
#else
59
static TCGv cpu_wim;
60
#endif
61
/* local register indexes (only used inside old micro ops) */
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static TCGv cpu_tmp0;
63
static TCGv_i32 cpu_tmp32;
64
static TCGv_i64 cpu_tmp64;
65
/* Floating point registers */
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static TCGv_i32 cpu_fpr[TARGET_FPREGS];
67

    
68
static target_ulong gen_opc_npc[OPC_BUF_SIZE];
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static target_ulong gen_opc_jump_pc[2];
70

    
71
#include "gen-icount.h"
72

    
73
typedef struct DisasContext {
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    target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
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    target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
77
    int is_br;
78
    int mem_idx;
79
    int fpu_enabled;
80
    int address_mask_32bit;
81
    int singlestep;
82
    uint32_t cc_op;  /* current CC operation */
83
    struct TranslationBlock *tb;
84
    sparc_def_t *def;
85
} DisasContext;
86

    
87
// This function uses non-native bit order
88
#define GET_FIELD(X, FROM, TO)                                  \
89
    ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
90

    
91
// This function uses the order in the manuals, i.e. bit 0 is 2^0
92
#define GET_FIELD_SP(X, FROM, TO)               \
93
    GET_FIELD(X, 31 - (TO), 31 - (FROM))
94

    
95
#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
96
#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
97

    
98
#ifdef TARGET_SPARC64
99
#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
100
#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
101
#else
102
#define DFPREG(r) (r & 0x1e)
103
#define QFPREG(r) (r & 0x1c)
104
#endif
105

    
106
#define UA2005_HTRAP_MASK 0xff
107
#define V8_TRAP_MASK 0x7f
108

    
109
static int sign_extend(int x, int len)
110
{
111
    len = 32 - len;
112
    return (x << len) >> len;
113
}
114

    
115
#define IS_IMM (insn & (1<<13))
116

    
117
/* floating point registers moves */
118
static void gen_op_load_fpr_DT0(unsigned int src)
119
{
120
    tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) +
121
                   offsetof(CPU_DoubleU, l.upper));
122
    tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
123
                   offsetof(CPU_DoubleU, l.lower));
124
}
125

    
126
static void gen_op_load_fpr_DT1(unsigned int src)
127
{
128
    tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) +
129
                   offsetof(CPU_DoubleU, l.upper));
130
    tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) +
131
                   offsetof(CPU_DoubleU, l.lower));
132
}
133

    
134
static void gen_op_store_DT0_fpr(unsigned int dst)
135
{
136
    tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) +
137
                   offsetof(CPU_DoubleU, l.upper));
138
    tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
139
                   offsetof(CPU_DoubleU, l.lower));
140
}
141

    
142
static void gen_op_load_fpr_QT0(unsigned int src)
143
{
144
    tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) +
145
                   offsetof(CPU_QuadU, l.upmost));
146
    tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
147
                   offsetof(CPU_QuadU, l.upper));
148
    tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
149
                   offsetof(CPU_QuadU, l.lower));
150
    tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
151
                   offsetof(CPU_QuadU, l.lowest));
152
}
153

    
154
static void gen_op_load_fpr_QT1(unsigned int src)
155
{
156
    tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) +
157
                   offsetof(CPU_QuadU, l.upmost));
158
    tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
159
                   offsetof(CPU_QuadU, l.upper));
160
    tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +
161
                   offsetof(CPU_QuadU, l.lower));
162
    tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +
163
                   offsetof(CPU_QuadU, l.lowest));
164
}
165

    
166
static void gen_op_store_QT0_fpr(unsigned int dst)
167
{
168
    tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) +
169
                   offsetof(CPU_QuadU, l.upmost));
170
    tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
171
                   offsetof(CPU_QuadU, l.upper));
172
    tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
173
                   offsetof(CPU_QuadU, l.lower));
174
    tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
175
                   offsetof(CPU_QuadU, l.lowest));
176
}
177

    
178
/* moves */
179
#ifdef CONFIG_USER_ONLY
180
#define supervisor(dc) 0
181
#ifdef TARGET_SPARC64
182
#define hypervisor(dc) 0
183
#endif
184
#else
185
#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
186
#ifdef TARGET_SPARC64
187
#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
188
#else
189
#endif
190
#endif
191

    
192
#ifdef TARGET_SPARC64
193
#ifndef TARGET_ABI32
194
#define AM_CHECK(dc) ((dc)->address_mask_32bit)
195
#else
196
#define AM_CHECK(dc) (1)
197
#endif
198
#endif
199

    
200
static inline void gen_address_mask(DisasContext *dc, TCGv addr)
201
{
202
#ifdef TARGET_SPARC64
203
    if (AM_CHECK(dc))
204
        tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
205
#endif
206
}
207

    
208
static inline void gen_movl_reg_TN(int reg, TCGv tn)
209
{
210
    if (reg == 0)
211
        tcg_gen_movi_tl(tn, 0);
212
    else if (reg < 8)
213
        tcg_gen_mov_tl(tn, cpu_gregs[reg]);
214
    else {
215
        tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
216
    }
217
}
218

    
219
static inline void gen_movl_TN_reg(int reg, TCGv tn)
220
{
221
    if (reg == 0)
222
        return;
223
    else if (reg < 8)
224
        tcg_gen_mov_tl(cpu_gregs[reg], tn);
225
    else {
226
        tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
227
    }
228
}
229

    
230
static inline void gen_goto_tb(DisasContext *s, int tb_num,
231
                               target_ulong pc, target_ulong npc)
232
{
233
    TranslationBlock *tb;
234

    
235
    tb = s->tb;
236
    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
237
        (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
238
        !s->singlestep)  {
239
        /* jump to same page: we can use a direct jump */
240
        tcg_gen_goto_tb(tb_num);
241
        tcg_gen_movi_tl(cpu_pc, pc);
242
        tcg_gen_movi_tl(cpu_npc, npc);
243
        tcg_gen_exit_tb((tcg_target_long)tb + tb_num);
244
    } else {
245
        /* jump to another page: currently not optimized */
246
        tcg_gen_movi_tl(cpu_pc, pc);
247
        tcg_gen_movi_tl(cpu_npc, npc);
248
        tcg_gen_exit_tb(0);
249
    }
250
}
251

    
252
// XXX suboptimal
253
static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
254
{
255
    tcg_gen_extu_i32_tl(reg, src);
256
    tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
257
    tcg_gen_andi_tl(reg, reg, 0x1);
258
}
259

    
260
static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
261
{
262
    tcg_gen_extu_i32_tl(reg, src);
263
    tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
264
    tcg_gen_andi_tl(reg, reg, 0x1);
265
}
266

    
267
static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
268
{
269
    tcg_gen_extu_i32_tl(reg, src);
270
    tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
271
    tcg_gen_andi_tl(reg, reg, 0x1);
272
}
273

    
274
static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
275
{
276
    tcg_gen_extu_i32_tl(reg, src);
277
    tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
278
    tcg_gen_andi_tl(reg, reg, 0x1);
279
}
280

    
281
static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
282
{
283
    TCGv r_temp;
284
    TCGv_i32 r_const;
285
    int l1;
286

    
287
    l1 = gen_new_label();
288

    
289
    r_temp = tcg_temp_new();
290
    tcg_gen_xor_tl(r_temp, src1, src2);
291
    tcg_gen_not_tl(r_temp, r_temp);
292
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
293
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
294
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
295
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
296
    r_const = tcg_const_i32(TT_TOVF);
297
    gen_helper_raise_exception(r_const);
298
    tcg_temp_free_i32(r_const);
299
    gen_set_label(l1);
300
    tcg_temp_free(r_temp);
301
}
302

    
303
static inline void gen_tag_tv(TCGv src1, TCGv src2)
304
{
305
    int l1;
306
    TCGv_i32 r_const;
307

    
308
    l1 = gen_new_label();
309
    tcg_gen_or_tl(cpu_tmp0, src1, src2);
310
    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
311
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
312
    r_const = tcg_const_i32(TT_TOVF);
313
    gen_helper_raise_exception(r_const);
314
    tcg_temp_free_i32(r_const);
315
    gen_set_label(l1);
316
}
317

    
318
static inline void gen_op_addi_cc(TCGv dst, TCGv src1, target_long src2)
319
{
320
    tcg_gen_mov_tl(cpu_cc_src, src1);
321
    tcg_gen_movi_tl(cpu_cc_src2, src2);
322
    tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_src, src2);
323
    tcg_gen_mov_tl(dst, cpu_cc_dst);
324
}
325

    
326
static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
327
{
328
    tcg_gen_mov_tl(cpu_cc_src, src1);
329
    tcg_gen_mov_tl(cpu_cc_src2, src2);
330
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
331
    tcg_gen_mov_tl(dst, cpu_cc_dst);
332
}
333

    
334
static TCGv_i32 gen_add32_carry32(void)
335
{
336
    TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
337

    
338
    /* Carry is computed from a previous add: (dst < src)  */
339
#if TARGET_LONG_BITS == 64
340
    cc_src1_32 = tcg_temp_new_i32();
341
    cc_src2_32 = tcg_temp_new_i32();
342
    tcg_gen_trunc_i64_i32(cc_src1_32, cpu_cc_dst);
343
    tcg_gen_trunc_i64_i32(cc_src2_32, cpu_cc_src);
344
#else
345
    cc_src1_32 = cpu_cc_dst;
346
    cc_src2_32 = cpu_cc_src;
347
#endif
348

    
349
    carry_32 = tcg_temp_new_i32();
350
    tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
351

    
352
#if TARGET_LONG_BITS == 64
353
    tcg_temp_free_i32(cc_src1_32);
354
    tcg_temp_free_i32(cc_src2_32);
355
#endif
356

    
357
    return carry_32;
358
}
359

    
360
static TCGv_i32 gen_sub32_carry32(void)
361
{
362
    TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
363

    
364
    /* Carry is computed from a previous borrow: (src1 < src2)  */
365
#if TARGET_LONG_BITS == 64
366
    cc_src1_32 = tcg_temp_new_i32();
367
    cc_src2_32 = tcg_temp_new_i32();
368
    tcg_gen_trunc_i64_i32(cc_src1_32, cpu_cc_src);
369
    tcg_gen_trunc_i64_i32(cc_src2_32, cpu_cc_src2);
370
#else
371
    cc_src1_32 = cpu_cc_src;
372
    cc_src2_32 = cpu_cc_src2;
373
#endif
374

    
375
    carry_32 = tcg_temp_new_i32();
376
    tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
377

    
378
#if TARGET_LONG_BITS == 64
379
    tcg_temp_free_i32(cc_src1_32);
380
    tcg_temp_free_i32(cc_src2_32);
381
#endif
382

    
383
    return carry_32;
384
}
385

    
386
static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
387
                            TCGv src2, int update_cc)
388
{
389
    TCGv_i32 carry_32;
390
    TCGv carry;
391

    
392
    switch (dc->cc_op) {
393
    case CC_OP_DIV:
394
    case CC_OP_LOGIC:
395
        /* Carry is known to be zero.  Fall back to plain ADD.  */
396
        if (update_cc) {
397
            gen_op_add_cc(dst, src1, src2);
398
        } else {
399
            tcg_gen_add_tl(dst, src1, src2);
400
        }
401
        return;
402

    
403
    case CC_OP_ADD:
404
    case CC_OP_TADD:
405
    case CC_OP_TADDTV:
406
#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
407
        {
408
            /* For 32-bit hosts, we can re-use the host's hardware carry
409
               generation by using an ADD2 opcode.  We discard the low
410
               part of the output.  Ideally we'd combine this operation
411
               with the add that generated the carry in the first place.  */
412
            TCGv dst_low = tcg_temp_new();
413
            tcg_gen_op6_i32(INDEX_op_add2_i32, dst_low, dst,
414
                            cpu_cc_src, src1, cpu_cc_src2, src2);
415
            tcg_temp_free(dst_low);
416
            goto add_done;
417
        }
418
#endif
419
        carry_32 = gen_add32_carry32();
420
        break;
421

    
422
    case CC_OP_SUB:
423
    case CC_OP_TSUB:
424
    case CC_OP_TSUBTV:
425
        carry_32 = gen_sub32_carry32();
426
        break;
427

    
428
    default:
429
        /* We need external help to produce the carry.  */
430
        carry_32 = tcg_temp_new_i32();
431
        gen_helper_compute_C_icc(carry_32);
432
        break;
433
    }
434

    
435
#if TARGET_LONG_BITS == 64
436
    carry = tcg_temp_new();
437
    tcg_gen_extu_i32_i64(carry, carry_32);
438
#else
439
    carry = carry_32;
440
#endif
441

    
442
    tcg_gen_add_tl(dst, src1, src2);
443
    tcg_gen_add_tl(dst, dst, carry);
444

    
445
    tcg_temp_free_i32(carry_32);
446
#if TARGET_LONG_BITS == 64
447
    tcg_temp_free(carry);
448
#endif
449

    
450
#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
451
 add_done:
452
#endif
453
    if (update_cc) {
454
        tcg_gen_mov_tl(cpu_cc_src, src1);
455
        tcg_gen_mov_tl(cpu_cc_src2, src2);
456
        tcg_gen_mov_tl(cpu_cc_dst, dst);
457
        tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
458
        dc->cc_op = CC_OP_ADDX;
459
    }
460
}
461

    
462
static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
463
{
464
    tcg_gen_mov_tl(cpu_cc_src, src1);
465
    tcg_gen_mov_tl(cpu_cc_src2, src2);
466
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
467
    tcg_gen_mov_tl(dst, cpu_cc_dst);
468
}
469

    
470
static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
471
{
472
    tcg_gen_mov_tl(cpu_cc_src, src1);
473
    tcg_gen_mov_tl(cpu_cc_src2, src2);
474
    gen_tag_tv(cpu_cc_src, cpu_cc_src2);
475
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
476
    gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
477
    tcg_gen_mov_tl(dst, cpu_cc_dst);
478
}
479

    
480
static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
481
{
482
    TCGv r_temp;
483
    TCGv_i32 r_const;
484
    int l1;
485

    
486
    l1 = gen_new_label();
487

    
488
    r_temp = tcg_temp_new();
489
    tcg_gen_xor_tl(r_temp, src1, src2);
490
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
491
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
492
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
493
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
494
    r_const = tcg_const_i32(TT_TOVF);
495
    gen_helper_raise_exception(r_const);
496
    tcg_temp_free_i32(r_const);
497
    gen_set_label(l1);
498
    tcg_temp_free(r_temp);
499
}
500

    
501
static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2, DisasContext *dc)
502
{
503
    tcg_gen_mov_tl(cpu_cc_src, src1);
504
    tcg_gen_movi_tl(cpu_cc_src2, src2);
505
    if (src2 == 0) {
506
        tcg_gen_mov_tl(cpu_cc_dst, src1);
507
        tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
508
        dc->cc_op = CC_OP_LOGIC;
509
    } else {
510
        tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2);
511
        tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
512
        dc->cc_op = CC_OP_SUB;
513
    }
514
    tcg_gen_mov_tl(dst, cpu_cc_dst);
515
}
516

    
517
static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
518
{
519
    tcg_gen_mov_tl(cpu_cc_src, src1);
520
    tcg_gen_mov_tl(cpu_cc_src2, src2);
521
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
522
    tcg_gen_mov_tl(dst, cpu_cc_dst);
523
}
524

    
525
static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
526
                            TCGv src2, int update_cc)
527
{
528
    TCGv_i32 carry_32;
529
    TCGv carry;
530

    
531
    switch (dc->cc_op) {
532
    case CC_OP_DIV:
533
    case CC_OP_LOGIC:
534
        /* Carry is known to be zero.  Fall back to plain SUB.  */
535
        if (update_cc) {
536
            gen_op_sub_cc(dst, src1, src2);
537
        } else {
538
            tcg_gen_sub_tl(dst, src1, src2);
539
        }
540
        return;
541

    
542
    case CC_OP_ADD:
543
    case CC_OP_TADD:
544
    case CC_OP_TADDTV:
545
        carry_32 = gen_add32_carry32();
546
        break;
547

    
548
    case CC_OP_SUB:
549
    case CC_OP_TSUB:
550
    case CC_OP_TSUBTV:
551
#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
552
        {
553
            /* For 32-bit hosts, we can re-use the host's hardware carry
554
               generation by using a SUB2 opcode.  We discard the low
555
               part of the output.  Ideally we'd combine this operation
556
               with the add that generated the carry in the first place.  */
557
            TCGv dst_low = tcg_temp_new();
558
            tcg_gen_op6_i32(INDEX_op_sub2_i32, dst_low, dst,
559
                            cpu_cc_src, src1, cpu_cc_src2, src2);
560
            tcg_temp_free(dst_low);
561
            goto sub_done;
562
        }
563
#endif
564
        carry_32 = gen_sub32_carry32();
565
        break;
566

    
567
    default:
568
        /* We need external help to produce the carry.  */
569
        carry_32 = tcg_temp_new_i32();
570
        gen_helper_compute_C_icc(carry_32);
571
        break;
572
    }
573

    
574
#if TARGET_LONG_BITS == 64
575
    carry = tcg_temp_new();
576
    tcg_gen_extu_i32_i64(carry, carry_32);
577
#else
578
    carry = carry_32;
579
#endif
580

    
581
    tcg_gen_sub_tl(dst, src1, src2);
582
    tcg_gen_sub_tl(dst, dst, carry);
583

    
584
    tcg_temp_free_i32(carry_32);
585
#if TARGET_LONG_BITS == 64
586
    tcg_temp_free(carry);
587
#endif
588

    
589
#if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32
590
 sub_done:
591
#endif
592
    if (update_cc) {
593
        tcg_gen_mov_tl(cpu_cc_src, src1);
594
        tcg_gen_mov_tl(cpu_cc_src2, src2);
595
        tcg_gen_mov_tl(cpu_cc_dst, dst);
596
        tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
597
        dc->cc_op = CC_OP_SUBX;
598
    }
599
}
600

    
601
static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
602
{
603
    tcg_gen_mov_tl(cpu_cc_src, src1);
604
    tcg_gen_mov_tl(cpu_cc_src2, src2);
605
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
606
    tcg_gen_mov_tl(dst, cpu_cc_dst);
607
}
608

    
609
static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
610
{
611
    tcg_gen_mov_tl(cpu_cc_src, src1);
612
    tcg_gen_mov_tl(cpu_cc_src2, src2);
613
    gen_tag_tv(cpu_cc_src, cpu_cc_src2);
614
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
615
    gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
616
    tcg_gen_mov_tl(dst, cpu_cc_dst);
617
}
618

    
619
static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
620
{
621
    TCGv r_temp;
622
    int l1;
623

    
624
    l1 = gen_new_label();
625
    r_temp = tcg_temp_new();
626

    
627
    /* old op:
628
    if (!(env->y & 1))
629
        T1 = 0;
630
    */
631
    tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
632
    tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
633
    tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
634
    tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
635
    tcg_gen_movi_tl(cpu_cc_src2, 0);
636
    gen_set_label(l1);
637

    
638
    // b2 = T0 & 1;
639
    // env->y = (b2 << 31) | (env->y >> 1);
640
    tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
641
    tcg_gen_shli_tl(r_temp, r_temp, 31);
642
    tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
643
    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x7fffffff);
644
    tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp);
645
    tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
646

    
647
    // b1 = N ^ V;
648
    gen_mov_reg_N(cpu_tmp0, cpu_psr);
649
    gen_mov_reg_V(r_temp, cpu_psr);
650
    tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
651
    tcg_temp_free(r_temp);
652

    
653
    // T0 = (b1 << 31) | (T0 >> 1);
654
    // src1 = T0;
655
    tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
656
    tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
657
    tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
658

    
659
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
660

    
661
    tcg_gen_mov_tl(dst, cpu_cc_dst);
662
}
663

    
664
static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
665
{
666
    TCGv_i32 r_src1, r_src2;
667
    TCGv_i64 r_temp, r_temp2;
668

    
669
    r_src1 = tcg_temp_new_i32();
670
    r_src2 = tcg_temp_new_i32();
671

    
672
    tcg_gen_trunc_tl_i32(r_src1, src1);
673
    tcg_gen_trunc_tl_i32(r_src2, src2);
674

    
675
    r_temp = tcg_temp_new_i64();
676
    r_temp2 = tcg_temp_new_i64();
677

    
678
    if (sign_ext) {
679
        tcg_gen_ext_i32_i64(r_temp, r_src2);
680
        tcg_gen_ext_i32_i64(r_temp2, r_src1);
681
    } else {
682
        tcg_gen_extu_i32_i64(r_temp, r_src2);
683
        tcg_gen_extu_i32_i64(r_temp2, r_src1);
684
    }
685

    
686
    tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
687

    
688
    tcg_gen_shri_i64(r_temp, r_temp2, 32);
689
    tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
690
    tcg_temp_free_i64(r_temp);
691
    tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
692

    
693
    tcg_gen_trunc_i64_tl(dst, r_temp2);
694

    
695
    tcg_temp_free_i64(r_temp2);
696

    
697
    tcg_temp_free_i32(r_src1);
698
    tcg_temp_free_i32(r_src2);
699
}
700

    
701
static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
702
{
703
    /* zero-extend truncated operands before multiplication */
704
    gen_op_multiply(dst, src1, src2, 0);
705
}
706

    
707
static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
708
{
709
    /* sign-extend truncated operands before multiplication */
710
    gen_op_multiply(dst, src1, src2, 1);
711
}
712

    
713
#ifdef TARGET_SPARC64
714
static inline void gen_trap_ifdivzero_tl(TCGv divisor)
715
{
716
    TCGv_i32 r_const;
717
    int l1;
718

    
719
    l1 = gen_new_label();
720
    tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
721
    r_const = tcg_const_i32(TT_DIV_ZERO);
722
    gen_helper_raise_exception(r_const);
723
    tcg_temp_free_i32(r_const);
724
    gen_set_label(l1);
725
}
726

    
727
static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
728
{
729
    int l1, l2;
730
    TCGv r_temp1, r_temp2;
731

    
732
    l1 = gen_new_label();
733
    l2 = gen_new_label();
734
    r_temp1 = tcg_temp_local_new();
735
    r_temp2 = tcg_temp_local_new();
736
    tcg_gen_mov_tl(r_temp1, src1);
737
    tcg_gen_mov_tl(r_temp2, src2);
738
    gen_trap_ifdivzero_tl(r_temp2);
739
    tcg_gen_brcondi_tl(TCG_COND_NE, r_temp1, INT64_MIN, l1);
740
    tcg_gen_brcondi_tl(TCG_COND_NE, r_temp2, -1, l1);
741
    tcg_gen_movi_i64(dst, INT64_MIN);
742
    tcg_gen_br(l2);
743
    gen_set_label(l1);
744
    tcg_gen_div_i64(dst, r_temp1, r_temp2);
745
    gen_set_label(l2);
746
    tcg_temp_free(r_temp1);
747
    tcg_temp_free(r_temp2);
748
}
749
#endif
750

    
751
// 1
752
static inline void gen_op_eval_ba(TCGv dst)
753
{
754
    tcg_gen_movi_tl(dst, 1);
755
}
756

    
757
// Z
758
static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
759
{
760
    gen_mov_reg_Z(dst, src);
761
}
762

    
763
// Z | (N ^ V)
764
static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
765
{
766
    gen_mov_reg_N(cpu_tmp0, src);
767
    gen_mov_reg_V(dst, src);
768
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
769
    gen_mov_reg_Z(cpu_tmp0, src);
770
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
771
}
772

    
773
// N ^ V
774
static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
775
{
776
    gen_mov_reg_V(cpu_tmp0, src);
777
    gen_mov_reg_N(dst, src);
778
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
779
}
780

    
781
// C | Z
782
static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
783
{
784
    gen_mov_reg_Z(cpu_tmp0, src);
785
    gen_mov_reg_C(dst, src);
786
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
787
}
788

    
789
// C
790
static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
791
{
792
    gen_mov_reg_C(dst, src);
793
}
794

    
795
// V
796
static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
797
{
798
    gen_mov_reg_V(dst, src);
799
}
800

    
801
// 0
802
static inline void gen_op_eval_bn(TCGv dst)
803
{
804
    tcg_gen_movi_tl(dst, 0);
805
}
806

    
807
// N
808
static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
809
{
810
    gen_mov_reg_N(dst, src);
811
}
812

    
813
// !Z
814
static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
815
{
816
    gen_mov_reg_Z(dst, src);
817
    tcg_gen_xori_tl(dst, dst, 0x1);
818
}
819

    
820
// !(Z | (N ^ V))
821
static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
822
{
823
    gen_mov_reg_N(cpu_tmp0, src);
824
    gen_mov_reg_V(dst, src);
825
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
826
    gen_mov_reg_Z(cpu_tmp0, src);
827
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
828
    tcg_gen_xori_tl(dst, dst, 0x1);
829
}
830

    
831
// !(N ^ V)
832
static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
833
{
834
    gen_mov_reg_V(cpu_tmp0, src);
835
    gen_mov_reg_N(dst, src);
836
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
837
    tcg_gen_xori_tl(dst, dst, 0x1);
838
}
839

    
840
// !(C | Z)
841
static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
842
{
843
    gen_mov_reg_Z(cpu_tmp0, src);
844
    gen_mov_reg_C(dst, src);
845
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
846
    tcg_gen_xori_tl(dst, dst, 0x1);
847
}
848

    
849
// !C
850
static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
851
{
852
    gen_mov_reg_C(dst, src);
853
    tcg_gen_xori_tl(dst, dst, 0x1);
854
}
855

    
856
// !N
857
static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
858
{
859
    gen_mov_reg_N(dst, src);
860
    tcg_gen_xori_tl(dst, dst, 0x1);
861
}
862

    
863
// !V
864
static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
865
{
866
    gen_mov_reg_V(dst, src);
867
    tcg_gen_xori_tl(dst, dst, 0x1);
868
}
869

    
870
/*
871
  FPSR bit field FCC1 | FCC0:
872
   0 =
873
   1 <
874
   2 >
875
   3 unordered
876
*/
877
static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
878
                                    unsigned int fcc_offset)
879
{
880
    tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
881
    tcg_gen_andi_tl(reg, reg, 0x1);
882
}
883

    
884
static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
885
                                    unsigned int fcc_offset)
886
{
887
    tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
888
    tcg_gen_andi_tl(reg, reg, 0x1);
889
}
890

    
891
// !0: FCC0 | FCC1
892
static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
893
                                    unsigned int fcc_offset)
894
{
895
    gen_mov_reg_FCC0(dst, src, fcc_offset);
896
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
897
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
898
}
899

    
900
// 1 or 2: FCC0 ^ FCC1
901
static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
902
                                    unsigned int fcc_offset)
903
{
904
    gen_mov_reg_FCC0(dst, src, fcc_offset);
905
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
906
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
907
}
908

    
909
// 1 or 3: FCC0
910
static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
911
                                    unsigned int fcc_offset)
912
{
913
    gen_mov_reg_FCC0(dst, src, fcc_offset);
914
}
915

    
916
// 1: FCC0 & !FCC1
917
static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
918
                                    unsigned int fcc_offset)
919
{
920
    gen_mov_reg_FCC0(dst, src, fcc_offset);
921
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
922
    tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
923
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
924
}
925

    
926
// 2 or 3: FCC1
927
static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
928
                                    unsigned int fcc_offset)
929
{
930
    gen_mov_reg_FCC1(dst, src, fcc_offset);
931
}
932

    
933
// 2: !FCC0 & FCC1
934
static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
935
                                    unsigned int fcc_offset)
936
{
937
    gen_mov_reg_FCC0(dst, src, fcc_offset);
938
    tcg_gen_xori_tl(dst, dst, 0x1);
939
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
940
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
941
}
942

    
943
// 3: FCC0 & FCC1
944
static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
945
                                    unsigned int fcc_offset)
946
{
947
    gen_mov_reg_FCC0(dst, src, fcc_offset);
948
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
949
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
950
}
951

    
952
// 0: !(FCC0 | FCC1)
953
static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
954
                                    unsigned int fcc_offset)
955
{
956
    gen_mov_reg_FCC0(dst, src, fcc_offset);
957
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
958
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
959
    tcg_gen_xori_tl(dst, dst, 0x1);
960
}
961

    
962
// 0 or 3: !(FCC0 ^ FCC1)
963
static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
964
                                    unsigned int fcc_offset)
965
{
966
    gen_mov_reg_FCC0(dst, src, fcc_offset);
967
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
968
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
969
    tcg_gen_xori_tl(dst, dst, 0x1);
970
}
971

    
972
// 0 or 2: !FCC0
973
static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
974
                                    unsigned int fcc_offset)
975
{
976
    gen_mov_reg_FCC0(dst, src, fcc_offset);
977
    tcg_gen_xori_tl(dst, dst, 0x1);
978
}
979

    
980
// !1: !(FCC0 & !FCC1)
981
static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
982
                                    unsigned int fcc_offset)
983
{
984
    gen_mov_reg_FCC0(dst, src, fcc_offset);
985
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
986
    tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
987
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
988
    tcg_gen_xori_tl(dst, dst, 0x1);
989
}
990

    
991
// 0 or 1: !FCC1
992
static inline void gen_op_eval_fble(TCGv dst, TCGv src,
993
                                    unsigned int fcc_offset)
994
{
995
    gen_mov_reg_FCC1(dst, src, fcc_offset);
996
    tcg_gen_xori_tl(dst, dst, 0x1);
997
}
998

    
999
// !2: !(!FCC0 & FCC1)
1000
static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1001
                                    unsigned int fcc_offset)
1002
{
1003
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1004
    tcg_gen_xori_tl(dst, dst, 0x1);
1005
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1006
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1007
    tcg_gen_xori_tl(dst, dst, 0x1);
1008
}
1009

    
1010
// !3: !(FCC0 & FCC1)
1011
static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1012
                                    unsigned int fcc_offset)
1013
{
1014
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1015
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1016
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1017
    tcg_gen_xori_tl(dst, dst, 0x1);
1018
}
1019

    
1020
static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1021
                               target_ulong pc2, TCGv r_cond)
1022
{
1023
    int l1;
1024

    
1025
    l1 = gen_new_label();
1026

    
1027
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1028

    
1029
    gen_goto_tb(dc, 0, pc1, pc1 + 4);
1030

    
1031
    gen_set_label(l1);
1032
    gen_goto_tb(dc, 1, pc2, pc2 + 4);
1033
}
1034

    
1035
static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1036
                                target_ulong pc2, TCGv r_cond)
1037
{
1038
    int l1;
1039

    
1040
    l1 = gen_new_label();
1041

    
1042
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1043

    
1044
    gen_goto_tb(dc, 0, pc2, pc1);
1045

    
1046
    gen_set_label(l1);
1047
    gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1048
}
1049

    
1050
static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1051
                                      TCGv r_cond)
1052
{
1053
    int l1, l2;
1054

    
1055
    l1 = gen_new_label();
1056
    l2 = gen_new_label();
1057

    
1058
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1059

    
1060
    tcg_gen_movi_tl(cpu_npc, npc1);
1061
    tcg_gen_br(l2);
1062

    
1063
    gen_set_label(l1);
1064
    tcg_gen_movi_tl(cpu_npc, npc2);
1065
    gen_set_label(l2);
1066
}
1067

    
1068
/* call this function before using the condition register as it may
1069
   have been set for a jump */
1070
static inline void flush_cond(DisasContext *dc, TCGv cond)
1071
{
1072
    if (dc->npc == JUMP_PC) {
1073
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1074
        dc->npc = DYNAMIC_PC;
1075
    }
1076
}
1077

    
1078
static inline void save_npc(DisasContext *dc, TCGv cond)
1079
{
1080
    if (dc->npc == JUMP_PC) {
1081
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1082
        dc->npc = DYNAMIC_PC;
1083
    } else if (dc->npc != DYNAMIC_PC) {
1084
        tcg_gen_movi_tl(cpu_npc, dc->npc);
1085
    }
1086
}
1087

    
1088
static inline void save_state(DisasContext *dc, TCGv cond)
1089
{
1090
    tcg_gen_movi_tl(cpu_pc, dc->pc);
1091
    /* flush pending conditional evaluations before exposing cpu state */
1092
    if (dc->cc_op != CC_OP_FLAGS) {
1093
        dc->cc_op = CC_OP_FLAGS;
1094
        gen_helper_compute_psr();
1095
    }
1096
    save_npc(dc, cond);
1097
}
1098

    
1099
static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1100
{
1101
    if (dc->npc == JUMP_PC) {
1102
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1103
        tcg_gen_mov_tl(cpu_pc, cpu_npc);
1104
        dc->pc = DYNAMIC_PC;
1105
    } else if (dc->npc == DYNAMIC_PC) {
1106
        tcg_gen_mov_tl(cpu_pc, cpu_npc);
1107
        dc->pc = DYNAMIC_PC;
1108
    } else {
1109
        dc->pc = dc->npc;
1110
    }
1111
}
1112

    
1113
static inline void gen_op_next_insn(void)
1114
{
1115
    tcg_gen_mov_tl(cpu_pc, cpu_npc);
1116
    tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1117
}
1118

    
1119
static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
1120
                            DisasContext *dc)
1121
{
1122
    TCGv_i32 r_src;
1123

    
1124
#ifdef TARGET_SPARC64
1125
    if (cc)
1126
        r_src = cpu_xcc;
1127
    else
1128
        r_src = cpu_psr;
1129
#else
1130
    r_src = cpu_psr;
1131
#endif
1132
    switch (dc->cc_op) {
1133
    case CC_OP_FLAGS:
1134
        break;
1135
    default:
1136
        gen_helper_compute_psr();
1137
        dc->cc_op = CC_OP_FLAGS;
1138
        break;
1139
    }
1140
    switch (cond) {
1141
    case 0x0:
1142
        gen_op_eval_bn(r_dst);
1143
        break;
1144
    case 0x1:
1145
        gen_op_eval_be(r_dst, r_src);
1146
        break;
1147
    case 0x2:
1148
        gen_op_eval_ble(r_dst, r_src);
1149
        break;
1150
    case 0x3:
1151
        gen_op_eval_bl(r_dst, r_src);
1152
        break;
1153
    case 0x4:
1154
        gen_op_eval_bleu(r_dst, r_src);
1155
        break;
1156
    case 0x5:
1157
        gen_op_eval_bcs(r_dst, r_src);
1158
        break;
1159
    case 0x6:
1160
        gen_op_eval_bneg(r_dst, r_src);
1161
        break;
1162
    case 0x7:
1163
        gen_op_eval_bvs(r_dst, r_src);
1164
        break;
1165
    case 0x8:
1166
        gen_op_eval_ba(r_dst);
1167
        break;
1168
    case 0x9:
1169
        gen_op_eval_bne(r_dst, r_src);
1170
        break;
1171
    case 0xa:
1172
        gen_op_eval_bg(r_dst, r_src);
1173
        break;
1174
    case 0xb:
1175
        gen_op_eval_bge(r_dst, r_src);
1176
        break;
1177
    case 0xc:
1178
        gen_op_eval_bgu(r_dst, r_src);
1179
        break;
1180
    case 0xd:
1181
        gen_op_eval_bcc(r_dst, r_src);
1182
        break;
1183
    case 0xe:
1184
        gen_op_eval_bpos(r_dst, r_src);
1185
        break;
1186
    case 0xf:
1187
        gen_op_eval_bvc(r_dst, r_src);
1188
        break;
1189
    }
1190
}
1191

    
1192
static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1193
{
1194
    unsigned int offset;
1195

    
1196
    switch (cc) {
1197
    default:
1198
    case 0x0:
1199
        offset = 0;
1200
        break;
1201
    case 0x1:
1202
        offset = 32 - 10;
1203
        break;
1204
    case 0x2:
1205
        offset = 34 - 10;
1206
        break;
1207
    case 0x3:
1208
        offset = 36 - 10;
1209
        break;
1210
    }
1211

    
1212
    switch (cond) {
1213
    case 0x0:
1214
        gen_op_eval_bn(r_dst);
1215
        break;
1216
    case 0x1:
1217
        gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1218
        break;
1219
    case 0x2:
1220
        gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1221
        break;
1222
    case 0x3:
1223
        gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1224
        break;
1225
    case 0x4:
1226
        gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1227
        break;
1228
    case 0x5:
1229
        gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1230
        break;
1231
    case 0x6:
1232
        gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1233
        break;
1234
    case 0x7:
1235
        gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1236
        break;
1237
    case 0x8:
1238
        gen_op_eval_ba(r_dst);
1239
        break;
1240
    case 0x9:
1241
        gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1242
        break;
1243
    case 0xa:
1244
        gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1245
        break;
1246
    case 0xb:
1247
        gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1248
        break;
1249
    case 0xc:
1250
        gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1251
        break;
1252
    case 0xd:
1253
        gen_op_eval_fble(r_dst, cpu_fsr, offset);
1254
        break;
1255
    case 0xe:
1256
        gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1257
        break;
1258
    case 0xf:
1259
        gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1260
        break;
1261
    }
1262
}
1263

    
1264
#ifdef TARGET_SPARC64
1265
// Inverted logic
1266
static const int gen_tcg_cond_reg[8] = {
1267
    -1,
1268
    TCG_COND_NE,
1269
    TCG_COND_GT,
1270
    TCG_COND_GE,
1271
    -1,
1272
    TCG_COND_EQ,
1273
    TCG_COND_LE,
1274
    TCG_COND_LT,
1275
};
1276

    
1277
static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1278
{
1279
    int l1;
1280

    
1281
    l1 = gen_new_label();
1282
    tcg_gen_movi_tl(r_dst, 0);
1283
    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1284
    tcg_gen_movi_tl(r_dst, 1);
1285
    gen_set_label(l1);
1286
}
1287
#endif
1288

    
1289
/* XXX: potentially incorrect if dynamic npc */
1290
static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1291
                      TCGv r_cond)
1292
{
1293
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1294
    target_ulong target = dc->pc + offset;
1295

    
1296
    if (cond == 0x0) {
1297
        /* unconditional not taken */
1298
        if (a) {
1299
            dc->pc = dc->npc + 4;
1300
            dc->npc = dc->pc + 4;
1301
        } else {
1302
            dc->pc = dc->npc;
1303
            dc->npc = dc->pc + 4;
1304
        }
1305
    } else if (cond == 0x8) {
1306
        /* unconditional taken */
1307
        if (a) {
1308
            dc->pc = target;
1309
            dc->npc = dc->pc + 4;
1310
        } else {
1311
            dc->pc = dc->npc;
1312
            dc->npc = target;
1313
            tcg_gen_mov_tl(cpu_pc, cpu_npc);
1314
        }
1315
    } else {
1316
        flush_cond(dc, r_cond);
1317
        gen_cond(r_cond, cc, cond, dc);
1318
        if (a) {
1319
            gen_branch_a(dc, target, dc->npc, r_cond);
1320
            dc->is_br = 1;
1321
        } else {
1322
            dc->pc = dc->npc;
1323
            dc->jump_pc[0] = target;
1324
            dc->jump_pc[1] = dc->npc + 4;
1325
            dc->npc = JUMP_PC;
1326
        }
1327
    }
1328
}
1329

    
1330
/* XXX: potentially incorrect if dynamic npc */
1331
static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1332
                      TCGv r_cond)
1333
{
1334
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1335
    target_ulong target = dc->pc + offset;
1336

    
1337
    if (cond == 0x0) {
1338
        /* unconditional not taken */
1339
        if (a) {
1340
            dc->pc = dc->npc + 4;
1341
            dc->npc = dc->pc + 4;
1342
        } else {
1343
            dc->pc = dc->npc;
1344
            dc->npc = dc->pc + 4;
1345
        }
1346
    } else if (cond == 0x8) {
1347
        /* unconditional taken */
1348
        if (a) {
1349
            dc->pc = target;
1350
            dc->npc = dc->pc + 4;
1351
        } else {
1352
            dc->pc = dc->npc;
1353
            dc->npc = target;
1354
            tcg_gen_mov_tl(cpu_pc, cpu_npc);
1355
        }
1356
    } else {
1357
        flush_cond(dc, r_cond);
1358
        gen_fcond(r_cond, cc, cond);
1359
        if (a) {
1360
            gen_branch_a(dc, target, dc->npc, r_cond);
1361
            dc->is_br = 1;
1362
        } else {
1363
            dc->pc = dc->npc;
1364
            dc->jump_pc[0] = target;
1365
            dc->jump_pc[1] = dc->npc + 4;
1366
            dc->npc = JUMP_PC;
1367
        }
1368
    }
1369
}
1370

    
1371
#ifdef TARGET_SPARC64
1372
/* XXX: potentially incorrect if dynamic npc */
1373
static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1374
                          TCGv r_cond, TCGv r_reg)
1375
{
1376
    unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1377
    target_ulong target = dc->pc + offset;
1378

    
1379
    flush_cond(dc, r_cond);
1380
    gen_cond_reg(r_cond, cond, r_reg);
1381
    if (a) {
1382
        gen_branch_a(dc, target, dc->npc, r_cond);
1383
        dc->is_br = 1;
1384
    } else {
1385
        dc->pc = dc->npc;
1386
        dc->jump_pc[0] = target;
1387
        dc->jump_pc[1] = dc->npc + 4;
1388
        dc->npc = JUMP_PC;
1389
    }
1390
}
1391

    
1392
static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
1393
{
1394
    switch (fccno) {
1395
    case 0:
1396
        gen_helper_fcmps(r_rs1, r_rs2);
1397
        break;
1398
    case 1:
1399
        gen_helper_fcmps_fcc1(r_rs1, r_rs2);
1400
        break;
1401
    case 2:
1402
        gen_helper_fcmps_fcc2(r_rs1, r_rs2);
1403
        break;
1404
    case 3:
1405
        gen_helper_fcmps_fcc3(r_rs1, r_rs2);
1406
        break;
1407
    }
1408
}
1409

    
1410
static inline void gen_op_fcmpd(int fccno)
1411
{
1412
    switch (fccno) {
1413
    case 0:
1414
        gen_helper_fcmpd();
1415
        break;
1416
    case 1:
1417
        gen_helper_fcmpd_fcc1();
1418
        break;
1419
    case 2:
1420
        gen_helper_fcmpd_fcc2();
1421
        break;
1422
    case 3:
1423
        gen_helper_fcmpd_fcc3();
1424
        break;
1425
    }
1426
}
1427

    
1428
static inline void gen_op_fcmpq(int fccno)
1429
{
1430
    switch (fccno) {
1431
    case 0:
1432
        gen_helper_fcmpq();
1433
        break;
1434
    case 1:
1435
        gen_helper_fcmpq_fcc1();
1436
        break;
1437
    case 2:
1438
        gen_helper_fcmpq_fcc2();
1439
        break;
1440
    case 3:
1441
        gen_helper_fcmpq_fcc3();
1442
        break;
1443
    }
1444
}
1445

    
1446
static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
1447
{
1448
    switch (fccno) {
1449
    case 0:
1450
        gen_helper_fcmpes(r_rs1, r_rs2);
1451
        break;
1452
    case 1:
1453
        gen_helper_fcmpes_fcc1(r_rs1, r_rs2);
1454
        break;
1455
    case 2:
1456
        gen_helper_fcmpes_fcc2(r_rs1, r_rs2);
1457
        break;
1458
    case 3:
1459
        gen_helper_fcmpes_fcc3(r_rs1, r_rs2);
1460
        break;
1461
    }
1462
}
1463

    
1464
static inline void gen_op_fcmped(int fccno)
1465
{
1466
    switch (fccno) {
1467
    case 0:
1468
        gen_helper_fcmped();
1469
        break;
1470
    case 1:
1471
        gen_helper_fcmped_fcc1();
1472
        break;
1473
    case 2:
1474
        gen_helper_fcmped_fcc2();
1475
        break;
1476
    case 3:
1477
        gen_helper_fcmped_fcc3();
1478
        break;
1479
    }
1480
}
1481

    
1482
static inline void gen_op_fcmpeq(int fccno)
1483
{
1484
    switch (fccno) {
1485
    case 0:
1486
        gen_helper_fcmpeq();
1487
        break;
1488
    case 1:
1489
        gen_helper_fcmpeq_fcc1();
1490
        break;
1491
    case 2:
1492
        gen_helper_fcmpeq_fcc2();
1493
        break;
1494
    case 3:
1495
        gen_helper_fcmpeq_fcc3();
1496
        break;
1497
    }
1498
}
1499

    
1500
#else
1501

    
1502
static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
1503
{
1504
    gen_helper_fcmps(r_rs1, r_rs2);
1505
}
1506

    
1507
static inline void gen_op_fcmpd(int fccno)
1508
{
1509
    gen_helper_fcmpd();
1510
}
1511

    
1512
static inline void gen_op_fcmpq(int fccno)
1513
{
1514
    gen_helper_fcmpq();
1515
}
1516

    
1517
static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
1518
{
1519
    gen_helper_fcmpes(r_rs1, r_rs2);
1520
}
1521

    
1522
static inline void gen_op_fcmped(int fccno)
1523
{
1524
    gen_helper_fcmped();
1525
}
1526

    
1527
static inline void gen_op_fcmpeq(int fccno)
1528
{
1529
    gen_helper_fcmpeq();
1530
}
1531
#endif
1532

    
1533
static inline void gen_op_fpexception_im(int fsr_flags)
1534
{
1535
    TCGv_i32 r_const;
1536

    
1537
    tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
1538
    tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1539
    r_const = tcg_const_i32(TT_FP_EXCP);
1540
    gen_helper_raise_exception(r_const);
1541
    tcg_temp_free_i32(r_const);
1542
}
1543

    
1544
static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1545
{
1546
#if !defined(CONFIG_USER_ONLY)
1547
    if (!dc->fpu_enabled) {
1548
        TCGv_i32 r_const;
1549

    
1550
        save_state(dc, r_cond);
1551
        r_const = tcg_const_i32(TT_NFPU_INSN);
1552
        gen_helper_raise_exception(r_const);
1553
        tcg_temp_free_i32(r_const);
1554
        dc->is_br = 1;
1555
        return 1;
1556
    }
1557
#endif
1558
    return 0;
1559
}
1560

    
1561
static inline void gen_op_clear_ieee_excp_and_FTT(void)
1562
{
1563
    tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
1564
}
1565

    
1566
static inline void gen_clear_float_exceptions(void)
1567
{
1568
    gen_helper_clear_float_exceptions();
1569
}
1570

    
1571
/* asi moves */
1572
#ifdef TARGET_SPARC64
1573
static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr)
1574
{
1575
    int asi;
1576
    TCGv_i32 r_asi;
1577

    
1578
    if (IS_IMM) {
1579
        r_asi = tcg_temp_new_i32();
1580
        tcg_gen_mov_i32(r_asi, cpu_asi);
1581
    } else {
1582
        asi = GET_FIELD(insn, 19, 26);
1583
        r_asi = tcg_const_i32(asi);
1584
    }
1585
    return r_asi;
1586
}
1587

    
1588
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1589
                              int sign)
1590
{
1591
    TCGv_i32 r_asi, r_size, r_sign;
1592

    
1593
    r_asi = gen_get_asi(insn, addr);
1594
    r_size = tcg_const_i32(size);
1595
    r_sign = tcg_const_i32(sign);
1596
    gen_helper_ld_asi(dst, addr, r_asi, r_size, r_sign);
1597
    tcg_temp_free_i32(r_sign);
1598
    tcg_temp_free_i32(r_size);
1599
    tcg_temp_free_i32(r_asi);
1600
}
1601

    
1602
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1603
{
1604
    TCGv_i32 r_asi, r_size;
1605

    
1606
    r_asi = gen_get_asi(insn, addr);
1607
    r_size = tcg_const_i32(size);
1608
    gen_helper_st_asi(addr, src, r_asi, r_size);
1609
    tcg_temp_free_i32(r_size);
1610
    tcg_temp_free_i32(r_asi);
1611
}
1612

    
1613
static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1614
{
1615
    TCGv_i32 r_asi, r_size, r_rd;
1616

    
1617
    r_asi = gen_get_asi(insn, addr);
1618
    r_size = tcg_const_i32(size);
1619
    r_rd = tcg_const_i32(rd);
1620
    gen_helper_ldf_asi(addr, r_asi, r_size, r_rd);
1621
    tcg_temp_free_i32(r_rd);
1622
    tcg_temp_free_i32(r_size);
1623
    tcg_temp_free_i32(r_asi);
1624
}
1625

    
1626
static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1627
{
1628
    TCGv_i32 r_asi, r_size, r_rd;
1629

    
1630
    r_asi = gen_get_asi(insn, addr);
1631
    r_size = tcg_const_i32(size);
1632
    r_rd = tcg_const_i32(rd);
1633
    gen_helper_stf_asi(addr, r_asi, r_size, r_rd);
1634
    tcg_temp_free_i32(r_rd);
1635
    tcg_temp_free_i32(r_size);
1636
    tcg_temp_free_i32(r_asi);
1637
}
1638

    
1639
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1640
{
1641
    TCGv_i32 r_asi, r_size, r_sign;
1642

    
1643
    r_asi = gen_get_asi(insn, addr);
1644
    r_size = tcg_const_i32(4);
1645
    r_sign = tcg_const_i32(0);
1646
    gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
1647
    tcg_temp_free_i32(r_sign);
1648
    gen_helper_st_asi(addr, dst, r_asi, r_size);
1649
    tcg_temp_free_i32(r_size);
1650
    tcg_temp_free_i32(r_asi);
1651
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1652
}
1653

    
1654
static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1655
{
1656
    TCGv_i32 r_asi, r_rd;
1657

    
1658
    r_asi = gen_get_asi(insn, addr);
1659
    r_rd = tcg_const_i32(rd);
1660
    gen_helper_ldda_asi(addr, r_asi, r_rd);
1661
    tcg_temp_free_i32(r_rd);
1662
    tcg_temp_free_i32(r_asi);
1663
}
1664

    
1665
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1666
{
1667
    TCGv_i32 r_asi, r_size;
1668

    
1669
    gen_movl_reg_TN(rd + 1, cpu_tmp0);
1670
    tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi);
1671
    r_asi = gen_get_asi(insn, addr);
1672
    r_size = tcg_const_i32(8);
1673
    gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size);
1674
    tcg_temp_free_i32(r_size);
1675
    tcg_temp_free_i32(r_asi);
1676
}
1677

    
1678
static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1679
                               int rd)
1680
{
1681
    TCGv r_val1;
1682
    TCGv_i32 r_asi;
1683

    
1684
    r_val1 = tcg_temp_new();
1685
    gen_movl_reg_TN(rd, r_val1);
1686
    r_asi = gen_get_asi(insn, addr);
1687
    gen_helper_cas_asi(dst, addr, r_val1, val2, r_asi);
1688
    tcg_temp_free_i32(r_asi);
1689
    tcg_temp_free(r_val1);
1690
}
1691

    
1692
static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1693
                                int rd)
1694
{
1695
    TCGv_i32 r_asi;
1696

    
1697
    gen_movl_reg_TN(rd, cpu_tmp64);
1698
    r_asi = gen_get_asi(insn, addr);
1699
    gen_helper_casx_asi(dst, addr, cpu_tmp64, val2, r_asi);
1700
    tcg_temp_free_i32(r_asi);
1701
}
1702

    
1703
#elif !defined(CONFIG_USER_ONLY)
1704

    
1705
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1706
                              int sign)
1707
{
1708
    TCGv_i32 r_asi, r_size, r_sign;
1709

    
1710
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1711
    r_size = tcg_const_i32(size);
1712
    r_sign = tcg_const_i32(sign);
1713
    gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
1714
    tcg_temp_free(r_sign);
1715
    tcg_temp_free(r_size);
1716
    tcg_temp_free(r_asi);
1717
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1718
}
1719

    
1720
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1721
{
1722
    TCGv_i32 r_asi, r_size;
1723

    
1724
    tcg_gen_extu_tl_i64(cpu_tmp64, src);
1725
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1726
    r_size = tcg_const_i32(size);
1727
    gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size);
1728
    tcg_temp_free(r_size);
1729
    tcg_temp_free(r_asi);
1730
}
1731

    
1732
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1733
{
1734
    TCGv_i32 r_asi, r_size, r_sign;
1735
    TCGv_i64 r_val;
1736

    
1737
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1738
    r_size = tcg_const_i32(4);
1739
    r_sign = tcg_const_i32(0);
1740
    gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
1741
    tcg_temp_free(r_sign);
1742
    r_val = tcg_temp_new_i64();
1743
    tcg_gen_extu_tl_i64(r_val, dst);
1744
    gen_helper_st_asi(addr, r_val, r_asi, r_size);
1745
    tcg_temp_free_i64(r_val);
1746
    tcg_temp_free(r_size);
1747
    tcg_temp_free(r_asi);
1748
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1749
}
1750

    
1751
static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1752
{
1753
    TCGv_i32 r_asi, r_size, r_sign;
1754

    
1755
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1756
    r_size = tcg_const_i32(8);
1757
    r_sign = tcg_const_i32(0);
1758
    gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
1759
    tcg_temp_free(r_sign);
1760
    tcg_temp_free(r_size);
1761
    tcg_temp_free(r_asi);
1762
    tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
1763
    gen_movl_TN_reg(rd + 1, cpu_tmp0);
1764
    tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1765
    tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1766
    gen_movl_TN_reg(rd, hi);
1767
}
1768

    
1769
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1770
{
1771
    TCGv_i32 r_asi, r_size;
1772

    
1773
    gen_movl_reg_TN(rd + 1, cpu_tmp0);
1774
    tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi);
1775
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1776
    r_size = tcg_const_i32(8);
1777
    gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size);
1778
    tcg_temp_free(r_size);
1779
    tcg_temp_free(r_asi);
1780
}
1781
#endif
1782

    
1783
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1784
static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1785
{
1786
    TCGv_i64 r_val;
1787
    TCGv_i32 r_asi, r_size;
1788

    
1789
    gen_ld_asi(dst, addr, insn, 1, 0);
1790

    
1791
    r_val = tcg_const_i64(0xffULL);
1792
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1793
    r_size = tcg_const_i32(1);
1794
    gen_helper_st_asi(addr, r_val, r_asi, r_size);
1795
    tcg_temp_free_i32(r_size);
1796
    tcg_temp_free_i32(r_asi);
1797
    tcg_temp_free_i64(r_val);
1798
}
1799
#endif
1800

    
1801
static inline TCGv get_src1(unsigned int insn, TCGv def)
1802
{
1803
    TCGv r_rs1 = def;
1804
    unsigned int rs1;
1805

    
1806
    rs1 = GET_FIELD(insn, 13, 17);
1807
    if (rs1 == 0) {
1808
        tcg_gen_movi_tl(def, 0);
1809
    } else if (rs1 < 8) {
1810
        r_rs1 = cpu_gregs[rs1];
1811
    } else {
1812
        tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1813
    }
1814
    return r_rs1;
1815
}
1816

    
1817
static inline TCGv get_src2(unsigned int insn, TCGv def)
1818
{
1819
    TCGv r_rs2 = def;
1820

    
1821
    if (IS_IMM) { /* immediate */
1822
        target_long simm = GET_FIELDs(insn, 19, 31);
1823
        tcg_gen_movi_tl(def, simm);
1824
    } else { /* register */
1825
        unsigned int rs2 = GET_FIELD(insn, 27, 31);
1826
        if (rs2 == 0) {
1827
            tcg_gen_movi_tl(def, 0);
1828
        } else if (rs2 < 8) {
1829
            r_rs2 = cpu_gregs[rs2];
1830
        } else {
1831
            tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1832
        }
1833
    }
1834
    return r_rs2;
1835
}
1836

    
1837
#ifdef TARGET_SPARC64
1838
static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env)
1839
{
1840
    TCGv_i32 r_tl = tcg_temp_new_i32();
1841

    
1842
    /* load env->tl into r_tl */
1843
    tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
1844

    
1845
    /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
1846
    tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
1847

    
1848
    /* calculate offset to current trap state from env->ts, reuse r_tl */
1849
    tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
1850
    tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUState, ts));
1851

    
1852
    /* tsptr = env->ts[env->tl & MAXTL_MASK] */
1853
    {
1854
        TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
1855
        tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
1856
        tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
1857
        tcg_temp_free_ptr(r_tl_tmp);
1858
    }
1859

    
1860
    tcg_temp_free_i32(r_tl);
1861
}
1862
#endif
1863

    
1864
#define CHECK_IU_FEATURE(dc, FEATURE)                      \
1865
    if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE))  \
1866
        goto illegal_insn;
1867
#define CHECK_FPU_FEATURE(dc, FEATURE)                     \
1868
    if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE))  \
1869
        goto nfpu_insn;
1870

    
1871
/* before an instruction, dc->pc must be static */
1872
static void disas_sparc_insn(DisasContext * dc)
1873
{
1874
    unsigned int insn, opc, rs1, rs2, rd;
1875
    TCGv cpu_src1, cpu_src2, cpu_tmp1, cpu_tmp2;
1876
    target_long simm;
1877

    
1878
    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
1879
        tcg_gen_debug_insn_start(dc->pc);
1880
    insn = ldl_code(dc->pc);
1881
    opc = GET_FIELD(insn, 0, 1);
1882

    
1883
    rd = GET_FIELD(insn, 2, 6);
1884

    
1885
    cpu_tmp1 = cpu_src1 = tcg_temp_new();
1886
    cpu_tmp2 = cpu_src2 = tcg_temp_new();
1887

    
1888
    switch (opc) {
1889
    case 0:                     /* branches/sethi */
1890
        {
1891
            unsigned int xop = GET_FIELD(insn, 7, 9);
1892
            int32_t target;
1893
            switch (xop) {
1894
#ifdef TARGET_SPARC64
1895
            case 0x1:           /* V9 BPcc */
1896
                {
1897
                    int cc;
1898

    
1899
                    target = GET_FIELD_SP(insn, 0, 18);
1900
                    target = sign_extend(target, 19);
1901
                    target <<= 2;
1902
                    cc = GET_FIELD_SP(insn, 20, 21);
1903
                    if (cc == 0)
1904
                        do_branch(dc, target, insn, 0, cpu_cond);
1905
                    else if (cc == 2)
1906
                        do_branch(dc, target, insn, 1, cpu_cond);
1907
                    else
1908
                        goto illegal_insn;
1909
                    goto jmp_insn;
1910
                }
1911
            case 0x3:           /* V9 BPr */
1912
                {
1913
                    target = GET_FIELD_SP(insn, 0, 13) |
1914
                        (GET_FIELD_SP(insn, 20, 21) << 14);
1915
                    target = sign_extend(target, 16);
1916
                    target <<= 2;
1917
                    cpu_src1 = get_src1(insn, cpu_src1);
1918
                    do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1919
                    goto jmp_insn;
1920
                }
1921
            case 0x5:           /* V9 FBPcc */
1922
                {
1923
                    int cc = GET_FIELD_SP(insn, 20, 21);
1924
                    if (gen_trap_ifnofpu(dc, cpu_cond))
1925
                        goto jmp_insn;
1926
                    target = GET_FIELD_SP(insn, 0, 18);
1927
                    target = sign_extend(target, 19);
1928
                    target <<= 2;
1929
                    do_fbranch(dc, target, insn, cc, cpu_cond);
1930
                    goto jmp_insn;
1931
                }
1932
#else
1933
            case 0x7:           /* CBN+x */
1934
                {
1935
                    goto ncp_insn;
1936
                }
1937
#endif
1938
            case 0x2:           /* BN+x */
1939
                {
1940
                    target = GET_FIELD(insn, 10, 31);
1941
                    target = sign_extend(target, 22);
1942
                    target <<= 2;
1943
                    do_branch(dc, target, insn, 0, cpu_cond);
1944
                    goto jmp_insn;
1945
                }
1946
            case 0x6:           /* FBN+x */
1947
                {
1948
                    if (gen_trap_ifnofpu(dc, cpu_cond))
1949
                        goto jmp_insn;
1950
                    target = GET_FIELD(insn, 10, 31);
1951
                    target = sign_extend(target, 22);
1952
                    target <<= 2;
1953
                    do_fbranch(dc, target, insn, 0, cpu_cond);
1954
                    goto jmp_insn;
1955
                }
1956
            case 0x4:           /* SETHI */
1957
                if (rd) { // nop
1958
                    uint32_t value = GET_FIELD(insn, 10, 31);
1959
                    TCGv r_const;
1960

    
1961
                    r_const = tcg_const_tl(value << 10);
1962
                    gen_movl_TN_reg(rd, r_const);
1963
                    tcg_temp_free(r_const);
1964
                }
1965
                break;
1966
            case 0x0:           /* UNIMPL */
1967
            default:
1968
                goto illegal_insn;
1969
            }
1970
            break;
1971
        }
1972
        break;
1973
    case 1:                     /*CALL*/
1974
        {
1975
            target_long target = GET_FIELDs(insn, 2, 31) << 2;
1976
            TCGv r_const;
1977

    
1978
            r_const = tcg_const_tl(dc->pc);
1979
            gen_movl_TN_reg(15, r_const);
1980
            tcg_temp_free(r_const);
1981
            target += dc->pc;
1982
            gen_mov_pc_npc(dc, cpu_cond);
1983
            dc->npc = target;
1984
        }
1985
        goto jmp_insn;
1986
    case 2:                     /* FPU & Logical Operations */
1987
        {
1988
            unsigned int xop = GET_FIELD(insn, 7, 12);
1989
            if (xop == 0x3a) {  /* generate trap */
1990
                int cond;
1991

    
1992
                cpu_src1 = get_src1(insn, cpu_src1);
1993
                if (IS_IMM) {
1994
                    rs2 = GET_FIELD(insn, 25, 31);
1995
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
1996
                } else {
1997
                    rs2 = GET_FIELD(insn, 27, 31);
1998
                    if (rs2 != 0) {
1999
                        gen_movl_reg_TN(rs2, cpu_src2);
2000
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2001
                    } else
2002
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
2003
                }
2004

    
2005
                cond = GET_FIELD(insn, 3, 6);
2006
                if (cond == 0x8) { /* Trap Always */
2007
                    save_state(dc, cpu_cond);
2008
                    if ((dc->def->features & CPU_FEATURE_HYPV) &&
2009
                        supervisor(dc))
2010
                        tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK);
2011
                    else
2012
                        tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK);
2013
                    tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP);
2014
                    tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2015

    
2016
                    if (rs2 == 0 &&
2017
                        dc->def->features & CPU_FEATURE_TA0_SHUTDOWN) {
2018

    
2019
                        gen_helper_shutdown();
2020

    
2021
                    } else {
2022
                        gen_helper_raise_exception(cpu_tmp32);
2023
                    }
2024
                } else if (cond != 0) {
2025
                    TCGv r_cond = tcg_temp_new();
2026
                    int l1;
2027
#ifdef TARGET_SPARC64
2028
                    /* V9 icc/xcc */
2029
                    int cc = GET_FIELD_SP(insn, 11, 12);
2030

    
2031
                    save_state(dc, cpu_cond);
2032
                    if (cc == 0)
2033
                        gen_cond(r_cond, 0, cond, dc);
2034
                    else if (cc == 2)
2035
                        gen_cond(r_cond, 1, cond, dc);
2036
                    else
2037
                        goto illegal_insn;
2038
#else
2039
                    save_state(dc, cpu_cond);
2040
                    gen_cond(r_cond, 0, cond, dc);
2041
#endif
2042
                    l1 = gen_new_label();
2043
                    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
2044

    
2045
                    if ((dc->def->features & CPU_FEATURE_HYPV) &&
2046
                        supervisor(dc))
2047
                        tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK);
2048
                    else
2049
                        tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK);
2050
                    tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP);
2051
                    tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2052
                    gen_helper_raise_exception(cpu_tmp32);
2053

    
2054
                    gen_set_label(l1);
2055
                    tcg_temp_free(r_cond);
2056
                }
2057
                gen_op_next_insn();
2058
                tcg_gen_exit_tb(0);
2059
                dc->is_br = 1;
2060
                goto jmp_insn;
2061
            } else if (xop == 0x28) {
2062
                rs1 = GET_FIELD(insn, 13, 17);
2063
                switch(rs1) {
2064
                case 0: /* rdy */
2065
#ifndef TARGET_SPARC64
2066
                case 0x01 ... 0x0e: /* undefined in the SPARCv8
2067
                                       manual, rdy on the microSPARC
2068
                                       II */
2069
                case 0x0f:          /* stbar in the SPARCv8 manual,
2070
                                       rdy on the microSPARC II */
2071
                case 0x10 ... 0x1f: /* implementation-dependent in the
2072
                                       SPARCv8 manual, rdy on the
2073
                                       microSPARC II */
2074
                    /* Read Asr17 */
2075
                    if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
2076
                        TCGv r_const;
2077

    
2078
                        /* Read Asr17 for a Leon3 monoprocessor */
2079
                        r_const = tcg_const_tl((1 << 8)
2080
                                               | (dc->def->nwindows - 1));
2081
                        gen_movl_TN_reg(rd, r_const);
2082
                        tcg_temp_free(r_const);
2083
                        break;
2084
                    }
2085
#endif
2086
                    gen_movl_TN_reg(rd, cpu_y);
2087
                    break;
2088
#ifdef TARGET_SPARC64
2089
                case 0x2: /* V9 rdccr */
2090
                    gen_helper_compute_psr();
2091
                    gen_helper_rdccr(cpu_dst);
2092
                    gen_movl_TN_reg(rd, cpu_dst);
2093
                    break;
2094
                case 0x3: /* V9 rdasi */
2095
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_asi);
2096
                    gen_movl_TN_reg(rd, cpu_dst);
2097
                    break;
2098
                case 0x4: /* V9 rdtick */
2099
                    {
2100
                        TCGv_ptr r_tickptr;
2101

    
2102
                        r_tickptr = tcg_temp_new_ptr();
2103
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2104
                                       offsetof(CPUState, tick));
2105
                        gen_helper_tick_get_count(cpu_dst, r_tickptr);
2106
                        tcg_temp_free_ptr(r_tickptr);
2107
                        gen_movl_TN_reg(rd, cpu_dst);
2108
                    }
2109
                    break;
2110
                case 0x5: /* V9 rdpc */
2111
                    {
2112
                        TCGv r_const;
2113

    
2114
                        r_const = tcg_const_tl(dc->pc);
2115
                        gen_movl_TN_reg(rd, r_const);
2116
                        tcg_temp_free(r_const);
2117
                    }
2118
                    break;
2119
                case 0x6: /* V9 rdfprs */
2120
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
2121
                    gen_movl_TN_reg(rd, cpu_dst);
2122
                    break;
2123
                case 0xf: /* V9 membar */
2124
                    break; /* no effect */
2125
                case 0x13: /* Graphics Status */
2126
                    if (gen_trap_ifnofpu(dc, cpu_cond))
2127
                        goto jmp_insn;
2128
                    gen_movl_TN_reg(rd, cpu_gsr);
2129
                    break;
2130
                case 0x16: /* Softint */
2131
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_softint);
2132
                    gen_movl_TN_reg(rd, cpu_dst);
2133
                    break;
2134
                case 0x17: /* Tick compare */
2135
                    gen_movl_TN_reg(rd, cpu_tick_cmpr);
2136
                    break;
2137
                case 0x18: /* System tick */
2138
                    {
2139
                        TCGv_ptr r_tickptr;
2140

    
2141
                        r_tickptr = tcg_temp_new_ptr();
2142
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2143
                                       offsetof(CPUState, stick));
2144
                        gen_helper_tick_get_count(cpu_dst, r_tickptr);
2145
                        tcg_temp_free_ptr(r_tickptr);
2146
                        gen_movl_TN_reg(rd, cpu_dst);
2147
                    }
2148
                    break;
2149
                case 0x19: /* System tick compare */
2150
                    gen_movl_TN_reg(rd, cpu_stick_cmpr);
2151
                    break;
2152
                case 0x10: /* Performance Control */
2153
                case 0x11: /* Performance Instrumentation Counter */
2154
                case 0x12: /* Dispatch Control */
2155
                case 0x14: /* Softint set, WO */
2156
                case 0x15: /* Softint clear, WO */
2157
#endif
2158
                default:
2159
                    goto illegal_insn;
2160
                }
2161
#if !defined(CONFIG_USER_ONLY)
2162
            } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2163
#ifndef TARGET_SPARC64
2164
                if (!supervisor(dc))
2165
                    goto priv_insn;
2166
                gen_helper_compute_psr();
2167
                dc->cc_op = CC_OP_FLAGS;
2168
                gen_helper_rdpsr(cpu_dst);
2169
#else
2170
                CHECK_IU_FEATURE(dc, HYPV);
2171
                if (!hypervisor(dc))
2172
                    goto priv_insn;
2173
                rs1 = GET_FIELD(insn, 13, 17);
2174
                switch (rs1) {
2175
                case 0: // hpstate
2176
                    // gen_op_rdhpstate();
2177
                    break;
2178
                case 1: // htstate
2179
                    // gen_op_rdhtstate();
2180
                    break;
2181
                case 3: // hintp
2182
                    tcg_gen_mov_tl(cpu_dst, cpu_hintp);
2183
                    break;
2184
                case 5: // htba
2185
                    tcg_gen_mov_tl(cpu_dst, cpu_htba);
2186
                    break;
2187
                case 6: // hver
2188
                    tcg_gen_mov_tl(cpu_dst, cpu_hver);
2189
                    break;
2190
                case 31: // hstick_cmpr
2191
                    tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
2192
                    break;
2193
                default:
2194
                    goto illegal_insn;
2195
                }
2196
#endif
2197
                gen_movl_TN_reg(rd, cpu_dst);
2198
                break;
2199
            } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2200
                if (!supervisor(dc))
2201
                    goto priv_insn;
2202
#ifdef TARGET_SPARC64
2203
                rs1 = GET_FIELD(insn, 13, 17);
2204
                switch (rs1) {
2205
                case 0: // tpc
2206
                    {
2207
                        TCGv_ptr r_tsptr;
2208

    
2209
                        r_tsptr = tcg_temp_new_ptr();
2210
                        gen_load_trap_state_at_tl(r_tsptr, cpu_env);
2211
                        tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2212
                                      offsetof(trap_state, tpc));
2213
                        tcg_temp_free_ptr(r_tsptr);
2214
                    }
2215
                    break;
2216
                case 1: // tnpc
2217
                    {
2218
                        TCGv_ptr r_tsptr;
2219

    
2220
                        r_tsptr = tcg_temp_new_ptr();
2221
                        gen_load_trap_state_at_tl(r_tsptr, cpu_env);
2222
                        tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2223
                                      offsetof(trap_state, tnpc));
2224
                        tcg_temp_free_ptr(r_tsptr);
2225
                    }
2226
                    break;
2227
                case 2: // tstate
2228
                    {
2229
                        TCGv_ptr r_tsptr;
2230

    
2231
                        r_tsptr = tcg_temp_new_ptr();
2232
                        gen_load_trap_state_at_tl(r_tsptr, cpu_env);
2233
                        tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2234
                                      offsetof(trap_state, tstate));
2235
                        tcg_temp_free_ptr(r_tsptr);
2236
                    }
2237
                    break;
2238
                case 3: // tt
2239
                    {
2240
                        TCGv_ptr r_tsptr;
2241

    
2242
                        r_tsptr = tcg_temp_new_ptr();
2243
                        gen_load_trap_state_at_tl(r_tsptr, cpu_env);
2244
                        tcg_gen_ld_i32(cpu_tmp32, r_tsptr,
2245
                                       offsetof(trap_state, tt));
2246
                        tcg_temp_free_ptr(r_tsptr);
2247
                        tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2248
                    }
2249
                    break;
2250
                case 4: // tick
2251
                    {
2252
                        TCGv_ptr r_tickptr;
2253

    
2254
                        r_tickptr = tcg_temp_new_ptr();
2255
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2256
                                       offsetof(CPUState, tick));
2257
                        gen_helper_tick_get_count(cpu_tmp0, r_tickptr);
2258
                        gen_movl_TN_reg(rd, cpu_tmp0);
2259
                        tcg_temp_free_ptr(r_tickptr);
2260
                    }
2261
                    break;
2262
                case 5: // tba
2263
                    tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
2264
                    break;
2265
                case 6: // pstate
2266
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2267
                                   offsetof(CPUSPARCState, pstate));
2268
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2269
                    break;
2270
                case 7: // tl
2271
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2272
                                   offsetof(CPUSPARCState, tl));
2273
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2274
                    break;
2275
                case 8: // pil
2276
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2277
                                   offsetof(CPUSPARCState, psrpil));
2278
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2279
                    break;
2280
                case 9: // cwp
2281
                    gen_helper_rdcwp(cpu_tmp0);
2282
                    break;
2283
                case 10: // cansave
2284
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2285
                                   offsetof(CPUSPARCState, cansave));
2286
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2287
                    break;
2288
                case 11: // canrestore
2289
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2290
                                   offsetof(CPUSPARCState, canrestore));
2291
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2292
                    break;
2293
                case 12: // cleanwin
2294
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2295
                                   offsetof(CPUSPARCState, cleanwin));
2296
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2297
                    break;
2298
                case 13: // otherwin
2299
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2300
                                   offsetof(CPUSPARCState, otherwin));
2301
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2302
                    break;
2303
                case 14: // wstate
2304
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2305
                                   offsetof(CPUSPARCState, wstate));
2306
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2307
                    break;
2308
                case 16: // UA2005 gl
2309
                    CHECK_IU_FEATURE(dc, GL);
2310
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2311
                                   offsetof(CPUSPARCState, gl));
2312
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2313
                    break;
2314
                case 26: // UA2005 strand status
2315
                    CHECK_IU_FEATURE(dc, HYPV);
2316
                    if (!hypervisor(dc))
2317
                        goto priv_insn;
2318
                    tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
2319
                    break;
2320
                case 31: // ver
2321
                    tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
2322
                    break;
2323
                case 15: // fq
2324
                default:
2325
                    goto illegal_insn;
2326
                }
2327
#else
2328
                tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
2329
#endif
2330
                gen_movl_TN_reg(rd, cpu_tmp0);
2331
                break;
2332
            } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2333
#ifdef TARGET_SPARC64
2334
                save_state(dc, cpu_cond);
2335
                gen_helper_flushw();
2336
#else
2337
                if (!supervisor(dc))
2338
                    goto priv_insn;
2339
                gen_movl_TN_reg(rd, cpu_tbr);
2340
#endif
2341
                break;
2342
#endif
2343
            } else if (xop == 0x34) {   /* FPU Operations */
2344
                if (gen_trap_ifnofpu(dc, cpu_cond))
2345
                    goto jmp_insn;
2346
                gen_op_clear_ieee_excp_and_FTT();
2347
                rs1 = GET_FIELD(insn, 13, 17);
2348
                rs2 = GET_FIELD(insn, 27, 31);
2349
                xop = GET_FIELD(insn, 18, 26);
2350
                save_state(dc, cpu_cond);
2351
                switch (xop) {
2352
                case 0x1: /* fmovs */
2353
                    tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
2354
                    break;
2355
                case 0x5: /* fnegs */
2356
                    gen_helper_fnegs(cpu_fpr[rd], cpu_fpr[rs2]);
2357
                    break;
2358
                case 0x9: /* fabss */
2359
                    gen_helper_fabss(cpu_fpr[rd], cpu_fpr[rs2]);
2360
                    break;
2361
                case 0x29: /* fsqrts */
2362
                    CHECK_FPU_FEATURE(dc, FSQRT);
2363
                    gen_clear_float_exceptions();
2364
                    gen_helper_fsqrts(cpu_tmp32, cpu_fpr[rs2]);
2365
                    gen_helper_check_ieee_exceptions();
2366
                    tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2367
                    break;
2368
                case 0x2a: /* fsqrtd */
2369
                    CHECK_FPU_FEATURE(dc, FSQRT);
2370
                    gen_op_load_fpr_DT1(DFPREG(rs2));
2371
                    gen_clear_float_exceptions();
2372
                    gen_helper_fsqrtd();
2373
                    gen_helper_check_ieee_exceptions();
2374
                    gen_op_store_DT0_fpr(DFPREG(rd));
2375
                    break;
2376
                case 0x2b: /* fsqrtq */
2377
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2378
                    gen_op_load_fpr_QT1(QFPREG(rs2));
2379
                    gen_clear_float_exceptions();
2380
                    gen_helper_fsqrtq();
2381
                    gen_helper_check_ieee_exceptions();
2382
                    gen_op_store_QT0_fpr(QFPREG(rd));
2383
                    break;
2384
                case 0x41: /* fadds */
2385
                    gen_clear_float_exceptions();
2386
                    gen_helper_fadds(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
2387
                    gen_helper_check_ieee_exceptions();
2388
                    tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2389
                    break;
2390
                case 0x42: /* faddd */
2391
                    gen_op_load_fpr_DT0(DFPREG(rs1));
2392
                    gen_op_load_fpr_DT1(DFPREG(rs2));
2393
                    gen_clear_float_exceptions();
2394
                    gen_helper_faddd();
2395
                    gen_helper_check_ieee_exceptions();
2396
                    gen_op_store_DT0_fpr(DFPREG(rd));
2397
                    break;
2398
                case 0x43: /* faddq */
2399
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2400
                    gen_op_load_fpr_QT0(QFPREG(rs1));
2401
                    gen_op_load_fpr_QT1(QFPREG(rs2));
2402
                    gen_clear_float_exceptions();
2403
                    gen_helper_faddq();
2404
                    gen_helper_check_ieee_exceptions();
2405
                    gen_op_store_QT0_fpr(QFPREG(rd));
2406
                    break;
2407
                case 0x45: /* fsubs */
2408
                    gen_clear_float_exceptions();
2409
                    gen_helper_fsubs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
2410
                    gen_helper_check_ieee_exceptions();
2411
                    tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2412
                    break;
2413
                case 0x46: /* fsubd */
2414
                    gen_op_load_fpr_DT0(DFPREG(rs1));
2415
                    gen_op_load_fpr_DT1(DFPREG(rs2));
2416
                    gen_clear_float_exceptions();
2417
                    gen_helper_fsubd();
2418
                    gen_helper_check_ieee_exceptions();
2419
                    gen_op_store_DT0_fpr(DFPREG(rd));
2420
                    break;
2421
                case 0x47: /* fsubq */
2422
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2423
                    gen_op_load_fpr_QT0(QFPREG(rs1));
2424
                    gen_op_load_fpr_QT1(QFPREG(rs2));
2425
                    gen_clear_float_exceptions();
2426
                    gen_helper_fsubq();
2427
                    gen_helper_check_ieee_exceptions();
2428
                    gen_op_store_QT0_fpr(QFPREG(rd));
2429
                    break;
2430
                case 0x49: /* fmuls */
2431
                    CHECK_FPU_FEATURE(dc, FMUL);
2432
                    gen_clear_float_exceptions();
2433
                    gen_helper_fmuls(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
2434
                    gen_helper_check_ieee_exceptions();
2435
                    tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2436
                    break;
2437
                case 0x4a: /* fmuld */
2438
                    CHECK_FPU_FEATURE(dc, FMUL);
2439
                    gen_op_load_fpr_DT0(DFPREG(rs1));
2440
                    gen_op_load_fpr_DT1(DFPREG(rs2));
2441
                    gen_clear_float_exceptions();
2442
                    gen_helper_fmuld();
2443
                    gen_helper_check_ieee_exceptions();
2444
                    gen_op_store_DT0_fpr(DFPREG(rd));
2445
                    break;
2446
                case 0x4b: /* fmulq */
2447
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2448
                    CHECK_FPU_FEATURE(dc, FMUL);
2449
                    gen_op_load_fpr_QT0(QFPREG(rs1));
2450
                    gen_op_load_fpr_QT1(QFPREG(rs2));
2451
                    gen_clear_float_exceptions();
2452
                    gen_helper_fmulq();
2453
                    gen_helper_check_ieee_exceptions();
2454
                    gen_op_store_QT0_fpr(QFPREG(rd));
2455
                    break;
2456
                case 0x4d: /* fdivs */
2457
                    gen_clear_float_exceptions();
2458
                    gen_helper_fdivs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
2459
                    gen_helper_check_ieee_exceptions();
2460
                    tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2461
                    break;
2462
                case 0x4e: /* fdivd */
2463
                    gen_op_load_fpr_DT0(DFPREG(rs1));
2464
                    gen_op_load_fpr_DT1(DFPREG(rs2));
2465
                    gen_clear_float_exceptions();
2466
                    gen_helper_fdivd();
2467
                    gen_helper_check_ieee_exceptions();
2468
                    gen_op_store_DT0_fpr(DFPREG(rd));
2469
                    break;
2470
                case 0x4f: /* fdivq */
2471
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2472
                    gen_op_load_fpr_QT0(QFPREG(rs1));
2473
                    gen_op_load_fpr_QT1(QFPREG(rs2));
2474
                    gen_clear_float_exceptions();
2475
                    gen_helper_fdivq();
2476
                    gen_helper_check_ieee_exceptions();
2477
                    gen_op_store_QT0_fpr(QFPREG(rd));
2478
                    break;
2479
                case 0x69: /* fsmuld */
2480
                    CHECK_FPU_FEATURE(dc, FSMULD);
2481
                    gen_clear_float_exceptions();
2482
                    gen_helper_fsmuld(cpu_fpr[rs1], cpu_fpr[rs2]);
2483
                    gen_helper_check_ieee_exceptions();
2484
                    gen_op_store_DT0_fpr(DFPREG(rd));
2485
                    break;
2486
                case 0x6e: /* fdmulq */
2487
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2488
                    gen_op_load_fpr_DT0(DFPREG(rs1));
2489
                    gen_op_load_fpr_DT1(DFPREG(rs2));
2490
                    gen_clear_float_exceptions();
2491
                    gen_helper_fdmulq();
2492
                    gen_helper_check_ieee_exceptions();
2493
                    gen_op_store_QT0_fpr(QFPREG(rd));
2494
                    break;
2495
                case 0xc4: /* fitos */
2496
                    gen_clear_float_exceptions();
2497
                    gen_helper_fitos(cpu_tmp32, cpu_fpr[rs2]);
2498
                    gen_helper_check_ieee_exceptions();
2499
                    tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2500
                    break;
2501
                case 0xc6: /* fdtos */
2502
                    gen_op_load_fpr_DT1(DFPREG(rs2));
2503
                    gen_clear_float_exceptions();
2504
                    gen_helper_fdtos(cpu_tmp32);
2505
                    gen_helper_check_ieee_exceptions();
2506
                    tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2507
                    break;
2508
                case 0xc7: /* fqtos */
2509
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2510
                    gen_op_load_fpr_QT1(QFPREG(rs2));
2511
                    gen_clear_float_exceptions();
2512
                    gen_helper_fqtos(cpu_tmp32);
2513
                    gen_helper_check_ieee_exceptions();
2514
                    tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2515
                    break;
2516
                case 0xc8: /* fitod */
2517
                    gen_helper_fitod(cpu_fpr[rs2]);
2518
                    gen_op_store_DT0_fpr(DFPREG(rd));
2519
                    break;
2520
                case 0xc9: /* fstod */
2521
                    gen_helper_fstod(cpu_fpr[rs2]);
2522
                    gen_op_store_DT0_fpr(DFPREG(rd));
2523
                    break;
2524
                case 0xcb: /* fqtod */
2525
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2526
                    gen_op_load_fpr_QT1(QFPREG(rs2));
2527
                    gen_clear_float_exceptions();
2528
                    gen_helper_fqtod();
2529
                    gen_helper_check_ieee_exceptions();
2530
                    gen_op_store_DT0_fpr(DFPREG(rd));
2531
                    break;
2532
                case 0xcc: /* fitoq */
2533
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2534
                    gen_helper_fitoq(cpu_fpr[rs2]);
2535
                    gen_op_store_QT0_fpr(QFPREG(rd));
2536
                    break;
2537
                case 0xcd: /* fstoq */
2538
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2539
                    gen_helper_fstoq(cpu_fpr[rs2]);
2540
                    gen_op_store_QT0_fpr(QFPREG(rd));
2541
                    break;
2542
                case 0xce: /* fdtoq */
2543
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2544
                    gen_op_load_fpr_DT1(DFPREG(rs2));
2545
                    gen_helper_fdtoq();
2546
                    gen_op_store_QT0_fpr(QFPREG(rd));
2547
                    break;
2548
                case 0xd1: /* fstoi */
2549
                    gen_clear_float_exceptions();
2550
                    gen_helper_fstoi(cpu_tmp32, cpu_fpr[rs2]);
2551
                    gen_helper_check_ieee_exceptions();
2552
                    tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2553
                    break;
2554
                case 0xd2: /* fdtoi */
2555
                    gen_op_load_fpr_DT1(DFPREG(rs2));
2556
                    gen_clear_float_exceptions();
2557
                    gen_helper_fdtoi(cpu_tmp32);
2558
                    gen_helper_check_ieee_exceptions();
2559
                    tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2560
                    break;
2561
                case 0xd3: /* fqtoi */
2562
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2563
                    gen_op_load_fpr_QT1(QFPREG(rs2));
2564
                    gen_clear_float_exceptions();
2565
                    gen_helper_fqtoi(cpu_tmp32);
2566
                    gen_helper_check_ieee_exceptions();
2567
                    tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2568
                    break;
2569
#ifdef TARGET_SPARC64
2570
                case 0x2: /* V9 fmovd */
2571
                    tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]);
2572
                    tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
2573
                                    cpu_fpr[DFPREG(rs2) + 1]);
2574
                    break;
2575
                case 0x3: /* V9 fmovq */
2576
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2577
                    tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]);
2578
                    tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1],
2579
                                    cpu_fpr[QFPREG(rs2) + 1]);
2580
                    tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2],
2581
                                    cpu_fpr[QFPREG(rs2) + 2]);
2582
                    tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3],
2583
                                    cpu_fpr[QFPREG(rs2) + 3]);
2584
                    break;
2585
                case 0x6: /* V9 fnegd */
2586
                    gen_op_load_fpr_DT1(DFPREG(rs2));
2587
                    gen_helper_fnegd();
2588
                    gen_op_store_DT0_fpr(DFPREG(rd));
2589
                    break;
2590
                case 0x7: /* V9 fnegq */
2591
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2592
                    gen_op_load_fpr_QT1(QFPREG(rs2));
2593
                    gen_helper_fnegq();
2594
                    gen_op_store_QT0_fpr(QFPREG(rd));
2595
                    break;
2596
                case 0xa: /* V9 fabsd */
2597
                    gen_op_load_fpr_DT1(DFPREG(rs2));
2598
                    gen_helper_fabsd();
2599
                    gen_op_store_DT0_fpr(DFPREG(rd));
2600
                    break;
2601
                case 0xb: /* V9 fabsq */
2602
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2603
                    gen_op_load_fpr_QT1(QFPREG(rs2));
2604
                    gen_helper_fabsq();
2605
                    gen_op_store_QT0_fpr(QFPREG(rd));
2606
                    break;
2607
                case 0x81: /* V9 fstox */
2608
                    gen_clear_float_exceptions();
2609
                    gen_helper_fstox(cpu_fpr[rs2]);
2610
                    gen_helper_check_ieee_exceptions();
2611
                    gen_op_store_DT0_fpr(DFPREG(rd));
2612
                    break;
2613
                case 0x82: /* V9 fdtox */
2614
                    gen_op_load_fpr_DT1(DFPREG(rs2));
2615
                    gen_clear_float_exceptions();
2616
                    gen_helper_fdtox();
2617
                    gen_helper_check_ieee_exceptions();
2618
                    gen_op_store_DT0_fpr(DFPREG(rd));
2619
                    break;
2620
                case 0x83: /* V9 fqtox */
2621
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2622
                    gen_op_load_fpr_QT1(QFPREG(rs2));
2623
                    gen_clear_float_exceptions();
2624
                    gen_helper_fqtox();
2625
                    gen_helper_check_ieee_exceptions();
2626
                    gen_op_store_DT0_fpr(DFPREG(rd));
2627
                    break;
2628
                case 0x84: /* V9 fxtos */
2629
                    gen_op_load_fpr_DT1(DFPREG(rs2));
2630
                    gen_clear_float_exceptions();
2631
                    gen_helper_fxtos(cpu_tmp32);
2632
                    gen_helper_check_ieee_exceptions();
2633
                    tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2634
                    break;
2635
                case 0x88: /* V9 fxtod */
2636
                    gen_op_load_fpr_DT1(DFPREG(rs2));
2637
                    gen_clear_float_exceptions();
2638
                    gen_helper_fxtod();
2639
                    gen_helper_check_ieee_exceptions();
2640
                    gen_op_store_DT0_fpr(DFPREG(rd));
2641
                    break;
2642
                case 0x8c: /* V9 fxtoq */
2643
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2644
                    gen_op_load_fpr_DT1(DFPREG(rs2));
2645
                    gen_clear_float_exceptions();
2646
                    gen_helper_fxtoq();
2647
                    gen_helper_check_ieee_exceptions();
2648
                    gen_op_store_QT0_fpr(QFPREG(rd));
2649
                    break;
2650
#endif
2651
                default:
2652
                    goto illegal_insn;
2653
                }
2654
            } else if (xop == 0x35) {   /* FPU Operations */
2655
#ifdef TARGET_SPARC64
2656
                int cond;
2657
#endif
2658
                if (gen_trap_ifnofpu(dc, cpu_cond))
2659
                    goto jmp_insn;
2660
                gen_op_clear_ieee_excp_and_FTT();
2661
                rs1 = GET_FIELD(insn, 13, 17);
2662
                rs2 = GET_FIELD(insn, 27, 31);
2663
                xop = GET_FIELD(insn, 18, 26);
2664
                save_state(dc, cpu_cond);
2665
#ifdef TARGET_SPARC64
2666
                if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2667
                    int l1;
2668

    
2669
                    l1 = gen_new_label();
2670
                    cond = GET_FIELD_SP(insn, 14, 17);
2671
                    cpu_src1 = get_src1(insn, cpu_src1);
2672
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2673
                                       0, l1);
2674
                    tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
2675
                    gen_set_label(l1);
2676
                    break;
2677
                } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2678
                    int l1;
2679

    
2680
                    l1 = gen_new_label();
2681
                    cond = GET_FIELD_SP(insn, 14, 17);
2682
                    cpu_src1 = get_src1(insn, cpu_src1);
2683
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2684
                                       0, l1);
2685
                    tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]);
2686
                    tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], cpu_fpr[DFPREG(rs2) + 1]);
2687
                    gen_set_label(l1);
2688
                    break;
2689
                } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2690
                    int l1;
2691

    
2692
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2693
                    l1 = gen_new_label();
2694
                    cond = GET_FIELD_SP(insn, 14, 17);
2695
                    cpu_src1 = get_src1(insn, cpu_src1);
2696
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2697
                                       0, l1);
2698
                    tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]);
2699
                    tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], cpu_fpr[QFPREG(rs2) + 1]);
2700
                    tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], cpu_fpr[QFPREG(rs2) + 2]);
2701
                    tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], cpu_fpr[QFPREG(rs2) + 3]);
2702
                    gen_set_label(l1);
2703
                    break;
2704
                }
2705
#endif
2706
                switch (xop) {
2707
#ifdef TARGET_SPARC64
2708
#define FMOVSCC(fcc)                                                    \
2709
                    {                                                   \
2710
                        TCGv r_cond;                                    \
2711
                        int l1;                                         \
2712
                                                                        \
2713
                        l1 = gen_new_label();                           \
2714
                        r_cond = tcg_temp_new();                        \
2715
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2716
                        gen_fcond(r_cond, fcc, cond);                   \
2717
                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2718
                                           0, l1);                      \
2719
                        tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);     \
2720
                        gen_set_label(l1);                              \
2721
                        tcg_temp_free(r_cond);                          \
2722
                    }
2723
#define FMOVDCC(fcc)                                                    \
2724
                    {                                                   \
2725
                        TCGv r_cond;                                    \
2726
                        int l1;                                         \
2727
                                                                        \
2728
                        l1 = gen_new_label();                           \
2729
                        r_cond = tcg_temp_new();                        \
2730
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2731
                        gen_fcond(r_cond, fcc, cond);                   \
2732
                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2733
                                           0, l1);                      \
2734
                        tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)],            \
2735
                                        cpu_fpr[DFPREG(rs2)]);          \
2736
                        tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],        \
2737
                                        cpu_fpr[DFPREG(rs2) + 1]);      \
2738
                        gen_set_label(l1);                              \
2739
                        tcg_temp_free(r_cond);                          \
2740
                    }
2741
#define FMOVQCC(fcc)                                                    \
2742
                    {                                                   \
2743
                        TCGv r_cond;                                    \
2744
                        int l1;                                         \
2745
                                                                        \
2746
                        l1 = gen_new_label();                           \
2747
                        r_cond = tcg_temp_new();                        \
2748
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2749
                        gen_fcond(r_cond, fcc, cond);                   \
2750
                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2751
                                           0, l1);                      \
2752
                        tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)],            \
2753
                                        cpu_fpr[QFPREG(rs2)]);          \
2754
                        tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1],        \
2755
                                        cpu_fpr[QFPREG(rs2) + 1]);      \
2756
                        tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2],        \
2757
                                        cpu_fpr[QFPREG(rs2) + 2]);      \
2758
                        tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3],        \
2759
                                        cpu_fpr[QFPREG(rs2) + 3]);      \
2760
                        gen_set_label(l1);                              \
2761
                        tcg_temp_free(r_cond);                          \
2762
                    }
2763
                    case 0x001: /* V9 fmovscc %fcc0 */
2764
                        FMOVSCC(0);
2765
                        break;
2766
                    case 0x002: /* V9 fmovdcc %fcc0 */
2767
                        FMOVDCC(0);
2768
                        break;
2769
                    case 0x003: /* V9 fmovqcc %fcc0 */
2770
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2771
                        FMOVQCC(0);
2772
                        break;
2773
                    case 0x041: /* V9 fmovscc %fcc1 */
2774
                        FMOVSCC(1);
2775
                        break;
2776
                    case 0x042: /* V9 fmovdcc %fcc1 */
2777
                        FMOVDCC(1);
2778
                        break;
2779
                    case 0x043: /* V9 fmovqcc %fcc1 */
2780
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2781
                        FMOVQCC(1);
2782
                        break;
2783
                    case 0x081: /* V9 fmovscc %fcc2 */
2784
                        FMOVSCC(2);
2785
                        break;
2786
                    case 0x082: /* V9 fmovdcc %fcc2 */
2787
                        FMOVDCC(2);
2788
                        break;
2789
                    case 0x083: /* V9 fmovqcc %fcc2 */
2790
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2791
                        FMOVQCC(2);
2792
                        break;
2793
                    case 0x0c1: /* V9 fmovscc %fcc3 */
2794
                        FMOVSCC(3);
2795
                        break;
2796
                    case 0x0c2: /* V9 fmovdcc %fcc3 */
2797
                        FMOVDCC(3);
2798
                        break;
2799
                    case 0x0c3: /* V9 fmovqcc %fcc3 */
2800
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2801
                        FMOVQCC(3);
2802
                        break;
2803
#undef FMOVSCC
2804
#undef FMOVDCC
2805
#undef FMOVQCC
2806
#define FMOVSCC(icc)                                                    \
2807
                    {                                                   \
2808
                        TCGv r_cond;                                    \
2809
                        int l1;                                         \
2810
                                                                        \
2811
                        l1 = gen_new_label();                           \
2812
                        r_cond = tcg_temp_new();                        \
2813
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2814
                        gen_cond(r_cond, icc, cond, dc);                \
2815
                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2816
                                           0, l1);                      \
2817
                        tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);     \
2818
                        gen_set_label(l1);                              \
2819
                        tcg_temp_free(r_cond);                          \
2820
                    }
2821
#define FMOVDCC(icc)                                                    \
2822
                    {                                                   \
2823
                        TCGv r_cond;                                    \
2824
                        int l1;                                         \
2825
                                                                        \
2826
                        l1 = gen_new_label();                           \
2827
                        r_cond = tcg_temp_new();                        \
2828
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2829
                        gen_cond(r_cond, icc, cond, dc);                \
2830
                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2831
                                           0, l1);                      \
2832
                        tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)],            \
2833
                                        cpu_fpr[DFPREG(rs2)]);          \
2834
                        tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],        \
2835
                                        cpu_fpr[DFPREG(rs2) + 1]);      \
2836
                        gen_set_label(l1);                              \
2837
                        tcg_temp_free(r_cond);                          \
2838
                    }
2839
#define FMOVQCC(icc)                                                    \
2840
                    {                                                   \
2841
                        TCGv r_cond;                                    \
2842
                        int l1;                                         \
2843
                                                                        \
2844
                        l1 = gen_new_label();                           \
2845
                        r_cond = tcg_temp_new();                        \
2846
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2847
                        gen_cond(r_cond, icc, cond, dc);                \
2848
                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2849
                                           0, l1);                      \
2850
                        tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)],            \
2851
                                        cpu_fpr[QFPREG(rs2)]);          \
2852
                        tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1],        \
2853
                                        cpu_fpr[QFPREG(rs2) + 1]);      \
2854
                        tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2],        \
2855
                                        cpu_fpr[QFPREG(rs2) + 2]);      \
2856
                        tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3],        \
2857
                                        cpu_fpr[QFPREG(rs2) + 3]);      \
2858
                        gen_set_label(l1);                              \
2859
                        tcg_temp_free(r_cond);                          \
2860
                    }
2861

    
2862
                    case 0x101: /* V9 fmovscc %icc */
2863
                        FMOVSCC(0);
2864
                        break;
2865
                    case 0x102: /* V9 fmovdcc %icc */
2866
                        FMOVDCC(0);
2867
                    case 0x103: /* V9 fmovqcc %icc */
2868
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2869
                        FMOVQCC(0);
2870
                        break;
2871
                    case 0x181: /* V9 fmovscc %xcc */
2872
                        FMOVSCC(1);
2873
                        break;
2874
                    case 0x182: /* V9 fmovdcc %xcc */
2875
                        FMOVDCC(1);
2876
                        break;
2877
                    case 0x183: /* V9 fmovqcc %xcc */
2878
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2879
                        FMOVQCC(1);
2880
                        break;
2881
#undef FMOVSCC
2882
#undef FMOVDCC
2883
#undef FMOVQCC
2884
#endif
2885
                    case 0x51: /* fcmps, V9 %fcc */
2886
                        gen_op_fcmps(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
2887
                        break;
2888
                    case 0x52: /* fcmpd, V9 %fcc */
2889
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2890
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2891
                        gen_op_fcmpd(rd & 3);
2892
                        break;
2893
                    case 0x53: /* fcmpq, V9 %fcc */
2894
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2895
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2896
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2897
                        gen_op_fcmpq(rd & 3);
2898
                        break;
2899
                    case 0x55: /* fcmpes, V9 %fcc */
2900
                        gen_op_fcmpes(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
2901
                        break;
2902
                    case 0x56: /* fcmped, V9 %fcc */
2903
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2904
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2905
                        gen_op_fcmped(rd & 3);
2906
                        break;
2907
                    case 0x57: /* fcmpeq, V9 %fcc */
2908
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2909
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2910
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2911
                        gen_op_fcmpeq(rd & 3);
2912
                        break;
2913
                    default:
2914
                        goto illegal_insn;
2915
                }
2916
            } else if (xop == 0x2) {
2917
                // clr/mov shortcut
2918

    
2919
                rs1 = GET_FIELD(insn, 13, 17);
2920
                if (rs1 == 0) {
2921
                    // or %g0, x, y -> mov T0, x; mov y, T0
2922
                    if (IS_IMM) {       /* immediate */
2923
                        TCGv r_const;
2924

    
2925
                        simm = GET_FIELDs(insn, 19, 31);
2926
                        r_const = tcg_const_tl(simm);
2927
                        gen_movl_TN_reg(rd, r_const);
2928
                        tcg_temp_free(r_const);
2929
                    } else {            /* register */
2930
                        rs2 = GET_FIELD(insn, 27, 31);
2931
                        gen_movl_reg_TN(rs2, cpu_dst);
2932
                        gen_movl_TN_reg(rd, cpu_dst);
2933
                    }
2934
                } else {
2935
                    cpu_src1 = get_src1(insn, cpu_src1);
2936
                    if (IS_IMM) {       /* immediate */
2937
                        simm = GET_FIELDs(insn, 19, 31);
2938
                        tcg_gen_ori_tl(cpu_dst, cpu_src1, simm);
2939
                        gen_movl_TN_reg(rd, cpu_dst);
2940
                    } else {            /* register */
2941
                        // or x, %g0, y -> mov T1, x; mov y, T1
2942
                        rs2 = GET_FIELD(insn, 27, 31);
2943
                        if (rs2 != 0) {
2944
                            gen_movl_reg_TN(rs2, cpu_src2);
2945
                            tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2946
                            gen_movl_TN_reg(rd, cpu_dst);
2947
                        } else
2948
                            gen_movl_TN_reg(rd, cpu_src1);
2949
                    }
2950
                }
2951
#ifdef TARGET_SPARC64
2952
            } else if (xop == 0x25) { /* sll, V9 sllx */
2953
                cpu_src1 = get_src1(insn, cpu_src1);
2954
                if (IS_IMM) {   /* immediate */
2955
                    simm = GET_FIELDs(insn, 20, 31);
2956
                    if (insn & (1 << 12)) {
2957
                        tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
2958
                    } else {
2959
                        tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
2960
                    }
2961
                } else {                /* register */
2962
                    rs2 = GET_FIELD(insn, 27, 31);
2963
                    gen_movl_reg_TN(rs2, cpu_src2);
2964
                    if (insn & (1 << 12)) {
2965
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2966
                    } else {
2967
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2968
                    }
2969
                    tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2970
                }
2971
                gen_movl_TN_reg(rd, cpu_dst);
2972
            } else if (xop == 0x26) { /* srl, V9 srlx */
2973
                cpu_src1 = get_src1(insn, cpu_src1);
2974
                if (IS_IMM) {   /* immediate */
2975
                    simm = GET_FIELDs(insn, 20, 31);
2976
                    if (insn & (1 << 12)) {
2977
                        tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
2978
                    } else {
2979
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2980
                        tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
2981
                    }
2982
                } else {                /* register */
2983
                    rs2 = GET_FIELD(insn, 27, 31);
2984
                    gen_movl_reg_TN(rs2, cpu_src2);
2985
                    if (insn & (1 << 12)) {
2986
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2987
                        tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2988
                    } else {
2989
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2990
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2991
                        tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2992
                    }
2993
                }
2994
                gen_movl_TN_reg(rd, cpu_dst);
2995
            } else if (xop == 0x27) { /* sra, V9 srax */
2996
                cpu_src1 = get_src1(insn, cpu_src1);
2997
                if (IS_IMM) {   /* immediate */
2998
                    simm = GET_FIELDs(insn, 20, 31);
2999
                    if (insn & (1 << 12)) {
3000
                        tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
3001
                    } else {
3002
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3003
                        tcg_gen_ext32s_i64(cpu_dst, cpu_dst);
3004
                        tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
3005
                    }
3006
                } else {                /* register */
3007
                    rs2 = GET_FIELD(insn, 27, 31);
3008
                    gen_movl_reg_TN(rs2, cpu_src2);
3009
                    if (insn & (1 << 12)) {
3010
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3011
                        tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
3012
                    } else {
3013
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3014
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3015
                        tcg_gen_ext32s_i64(cpu_dst, cpu_dst);
3016
                        tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
3017
                    }
3018
                }
3019
                gen_movl_TN_reg(rd, cpu_dst);
3020
#endif
3021
            } else if (xop < 0x36) {
3022
                if (xop < 0x20) {
3023
                    cpu_src1 = get_src1(insn, cpu_src1);
3024
                    cpu_src2 = get_src2(insn, cpu_src2);
3025
                    switch (xop & ~0x10) {
3026
                    case 0x0: /* add */
3027
                        if (IS_IMM) {
3028
                            simm = GET_FIELDs(insn, 19, 31);
3029
                            if (xop & 0x10) {
3030
                                gen_op_addi_cc(cpu_dst, cpu_src1, simm);
3031
                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3032
                                dc->cc_op = CC_OP_ADD;
3033
                            } else {
3034
                                tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
3035
                            }
3036
                        } else {
3037
                            if (xop & 0x10) {
3038
                                gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
3039
                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3040
                                dc->cc_op = CC_OP_ADD;
3041
                            } else {
3042
                                tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3043
                            }
3044
                        }
3045
                        break;
3046
                    case 0x1: /* and */
3047
                        if (IS_IMM) {
3048
                            simm = GET_FIELDs(insn, 19, 31);
3049
                            tcg_gen_andi_tl(cpu_dst, cpu_src1, simm);
3050
                        } else {
3051
                            tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
3052
                        }
3053
                        if (xop & 0x10) {
3054
                            tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3055
                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3056
                            dc->cc_op = CC_OP_LOGIC;
3057
                        }
3058
                        break;
3059
                    case 0x2: /* or */
3060
                        if (IS_IMM) {
3061
                            simm = GET_FIELDs(insn, 19, 31);
3062
                            tcg_gen_ori_tl(cpu_dst, cpu_src1, simm);
3063
                        } else {
3064
                            tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3065
                        }
3066
                        if (xop & 0x10) {
3067
                            tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3068
                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3069
                            dc->cc_op = CC_OP_LOGIC;
3070
                        }
3071
                        break;
3072
                    case 0x3: /* xor */
3073
                        if (IS_IMM) {
3074
                            simm = GET_FIELDs(insn, 19, 31);
3075
                            tcg_gen_xori_tl(cpu_dst, cpu_src1, simm);
3076
                        } else {
3077
                            tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3078
                        }
3079
                        if (xop & 0x10) {
3080
                            tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3081
                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3082
                            dc->cc_op = CC_OP_LOGIC;
3083
                        }
3084
                        break;
3085
                    case 0x4: /* sub */
3086
                        if (IS_IMM) {
3087
                            simm = GET_FIELDs(insn, 19, 31);
3088
                            if (xop & 0x10) {
3089
                                gen_op_subi_cc(cpu_dst, cpu_src1, simm, dc);
3090
                            } else {
3091
                                tcg_gen_subi_tl(cpu_dst, cpu_src1, simm);
3092
                            }
3093
                        } else {
3094
                            if (xop & 0x10) {
3095
                                gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3096
                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
3097
                                dc->cc_op = CC_OP_SUB;
3098
                            } else {
3099
                                tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3100
                            }
3101
                        }
3102
                        break;
3103
                    case 0x5: /* andn */
3104
                        if (IS_IMM) {
3105
                            simm = GET_FIELDs(insn, 19, 31);
3106
                            tcg_gen_andi_tl(cpu_dst, cpu_src1, ~simm);
3107
                        } else {
3108
                            tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
3109
                        }
3110
                        if (xop & 0x10) {
3111
                            tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3112
                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3113
                            dc->cc_op = CC_OP_LOGIC;
3114
                        }
3115
                        break;
3116
                    case 0x6: /* orn */
3117
                        if (IS_IMM) {
3118
                            simm = GET_FIELDs(insn, 19, 31);
3119
                            tcg_gen_ori_tl(cpu_dst, cpu_src1, ~simm);
3120
                        } else {
3121
                            tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
3122
                        }
3123
                        if (xop & 0x10) {
3124
                            tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3125
                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3126
                            dc->cc_op = CC_OP_LOGIC;
3127
                        }
3128
                        break;
3129
                    case 0x7: /* xorn */
3130
                        if (IS_IMM) {
3131
                            simm = GET_FIELDs(insn, 19, 31);
3132
                            tcg_gen_xori_tl(cpu_dst, cpu_src1, ~simm);
3133
                        } else {
3134
                            tcg_gen_not_tl(cpu_tmp0, cpu_src2);
3135
                            tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3136
                        }
3137
                        if (xop & 0x10) {
3138
                            tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3139
                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3140
                            dc->cc_op = CC_OP_LOGIC;
3141
                        }
3142
                        break;
3143
                    case 0x8: /* addx, V9 addc */
3144
                        gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3145
                                        (xop & 0x10));
3146
                        break;
3147
#ifdef TARGET_SPARC64
3148
                    case 0x9: /* V9 mulx */
3149
                        if (IS_IMM) {
3150
                            simm = GET_FIELDs(insn, 19, 31);
3151
                            tcg_gen_muli_i64(cpu_dst, cpu_src1, simm);
3152
                        } else {
3153
                            tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3154
                        }
3155
                        break;
3156
#endif
3157
                    case 0xa: /* umul */
3158
                        CHECK_IU_FEATURE(dc, MUL);
3159
                        gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3160
                        if (xop & 0x10) {
3161
                            tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3162
                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3163
                            dc->cc_op = CC_OP_LOGIC;
3164
                        }
3165
                        break;
3166
                    case 0xb: /* smul */
3167
                        CHECK_IU_FEATURE(dc, MUL);
3168
                        gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3169
                        if (xop & 0x10) {
3170
                            tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3171
                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3172
                            dc->cc_op = CC_OP_LOGIC;
3173
                        }
3174
                        break;
3175
                    case 0xc: /* subx, V9 subc */
3176
                        gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3177
                                        (xop & 0x10));
3178
                        break;
3179
#ifdef TARGET_SPARC64
3180
                    case 0xd: /* V9 udivx */
3181
                        {
3182
                            TCGv r_temp1, r_temp2;
3183
                            r_temp1 = tcg_temp_local_new();
3184
                            r_temp2 = tcg_temp_local_new();
3185
                            tcg_gen_mov_tl(r_temp1, cpu_src1);
3186
                            tcg_gen_mov_tl(r_temp2, cpu_src2);
3187
                            gen_trap_ifdivzero_tl(r_temp2);
3188
                            tcg_gen_divu_i64(cpu_dst, r_temp1, r_temp2);
3189
                            tcg_temp_free(r_temp1);
3190
                            tcg_temp_free(r_temp2);
3191
                        }
3192
                        break;
3193
#endif
3194
                    case 0xe: /* udiv */
3195
                        CHECK_IU_FEATURE(dc, DIV);
3196
                        if (xop & 0x10) {
3197
                            gen_helper_udiv_cc(cpu_dst, cpu_src1, cpu_src2);
3198
                            dc->cc_op = CC_OP_DIV;
3199
                        } else {
3200
                            gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2);
3201
                        }
3202
                        break;
3203
                    case 0xf: /* sdiv */
3204
                        CHECK_IU_FEATURE(dc, DIV);
3205
                        if (xop & 0x10) {
3206
                            gen_helper_sdiv_cc(cpu_dst, cpu_src1, cpu_src2);
3207
                            dc->cc_op = CC_OP_DIV;
3208
                        } else {
3209
                            gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2);
3210
                        }
3211
                        break;
3212
                    default:
3213
                        goto illegal_insn;
3214
                    }
3215
                    gen_movl_TN_reg(rd, cpu_dst);
3216
                } else {
3217
                    cpu_src1 = get_src1(insn, cpu_src1);
3218
                    cpu_src2 = get_src2(insn, cpu_src2);
3219
                    switch (xop) {
3220
                    case 0x20: /* taddcc */
3221
                        gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3222
                        gen_movl_TN_reg(rd, cpu_dst);
3223
                        tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
3224
                        dc->cc_op = CC_OP_TADD;
3225
                        break;
3226
                    case 0x21: /* tsubcc */
3227
                        gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3228
                        gen_movl_TN_reg(rd, cpu_dst);
3229
                        tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
3230
                        dc->cc_op = CC_OP_TSUB;
3231
                        break;
3232
                    case 0x22: /* taddcctv */
3233
                        save_state(dc, cpu_cond);
3234
                        gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3235
                        gen_movl_TN_reg(rd, cpu_dst);
3236
                        tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADDTV);
3237
                        dc->cc_op = CC_OP_TADDTV;
3238
                        break;
3239
                    case 0x23: /* tsubcctv */
3240
                        save_state(dc, cpu_cond);
3241
                        gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3242
                        gen_movl_TN_reg(rd, cpu_dst);
3243
                        tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUBTV);
3244
                        dc->cc_op = CC_OP_TSUBTV;
3245
                        break;
3246
                    case 0x24: /* mulscc */
3247
                        gen_helper_compute_psr();
3248
                        gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3249
                        gen_movl_TN_reg(rd, cpu_dst);
3250
                        tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3251
                        dc->cc_op = CC_OP_ADD;
3252
                        break;
3253
#ifndef TARGET_SPARC64
3254
                    case 0x25:  /* sll */
3255
                        if (IS_IMM) { /* immediate */
3256
                            simm = GET_FIELDs(insn, 20, 31);
3257
                            tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
3258
                        } else { /* register */
3259
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3260
                            tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3261
                        }
3262
                        gen_movl_TN_reg(rd, cpu_dst);
3263
                        break;
3264
                    case 0x26:  /* srl */
3265
                        if (IS_IMM) { /* immediate */
3266
                            simm = GET_FIELDs(insn, 20, 31);
3267
                            tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
3268
                        } else { /* register */
3269
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3270
                            tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3271
                        }
3272
                        gen_movl_TN_reg(rd, cpu_dst);
3273
                        break;
3274
                    case 0x27:  /* sra */
3275
                        if (IS_IMM) { /* immediate */
3276
                            simm = GET_FIELDs(insn, 20, 31);
3277
                            tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
3278
                        } else { /* register */
3279
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3280
                            tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3281
                        }
3282
                        gen_movl_TN_reg(rd, cpu_dst);
3283
                        break;
3284
#endif
3285
                    case 0x30:
3286
                        {
3287
                            switch(rd) {
3288
                            case 0: /* wry */
3289
                                tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3290
                                tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
3291
                                break;
3292
#ifndef TARGET_SPARC64
3293
                            case 0x01 ... 0x0f: /* undefined in the
3294
                                                   SPARCv8 manual, nop
3295
                                                   on the microSPARC
3296
                                                   II */
3297
                            case 0x10 ... 0x1f: /* implementation-dependent
3298
                                                   in the SPARCv8
3299
                                                   manual, nop on the
3300
                                                   microSPARC II */
3301
                                break;
3302
#else
3303
                            case 0x2: /* V9 wrccr */
3304
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3305
                                gen_helper_wrccr(cpu_dst);
3306
                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3307
                                dc->cc_op = CC_OP_FLAGS;
3308
                                break;
3309
                            case 0x3: /* V9 wrasi */
3310
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3311
                                tcg_gen_andi_tl(cpu_dst, cpu_dst, 0xff);
3312
                                tcg_gen_trunc_tl_i32(cpu_asi, cpu_dst);
3313
                                break;
3314
                            case 0x6: /* V9 wrfprs */
3315
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3316
                                tcg_gen_trunc_tl_i32(cpu_fprs, cpu_dst);
3317
                                save_state(dc, cpu_cond);
3318
                                gen_op_next_insn();
3319
                                tcg_gen_exit_tb(0);
3320
                                dc->is_br = 1;
3321
                                break;
3322
                            case 0xf: /* V9 sir, nop if user */
3323
#if !defined(CONFIG_USER_ONLY)
3324
                                if (supervisor(dc)) {
3325
                                    ; // XXX
3326
                                }
3327
#endif
3328
                                break;
3329
                            case 0x13: /* Graphics Status */
3330
                                if (gen_trap_ifnofpu(dc, cpu_cond))
3331
                                    goto jmp_insn;
3332
                                tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
3333
                                break;
3334
                            case 0x14: /* Softint set */
3335
                                if (!supervisor(dc))
3336
                                    goto illegal_insn;
3337
                                tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
3338
                                gen_helper_set_softint(cpu_tmp64);
3339
                                break;
3340
                            case 0x15: /* Softint clear */
3341
                                if (!supervisor(dc))
3342
                                    goto illegal_insn;
3343
                                tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
3344
                                gen_helper_clear_softint(cpu_tmp64);
3345
                                break;
3346
                            case 0x16: /* Softint write */
3347
                                if (!supervisor(dc))
3348
                                    goto illegal_insn;
3349
                                tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
3350
                                gen_helper_write_softint(cpu_tmp64);
3351
                                break;
3352
                            case 0x17: /* Tick compare */
3353
#if !defined(CONFIG_USER_ONLY)
3354
                                if (!supervisor(dc))
3355
                                    goto illegal_insn;
3356
#endif
3357
                                {
3358
                                    TCGv_ptr r_tickptr;
3359

    
3360
                                    tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
3361
                                                   cpu_src2);
3362
                                    r_tickptr = tcg_temp_new_ptr();
3363
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3364
                                                   offsetof(CPUState, tick));
3365
                                    gen_helper_tick_set_limit(r_tickptr,
3366
                                                              cpu_tick_cmpr);
3367
                                    tcg_temp_free_ptr(r_tickptr);
3368
                                }
3369
                                break;
3370
                            case 0x18: /* System tick */
3371
#if !defined(CONFIG_USER_ONLY)
3372
                                if (!supervisor(dc))
3373
                                    goto illegal_insn;
3374
#endif
3375
                                {
3376
                                    TCGv_ptr r_tickptr;
3377

    
3378
                                    tcg_gen_xor_tl(cpu_dst, cpu_src1,
3379
                                                   cpu_src2);
3380
                                    r_tickptr = tcg_temp_new_ptr();
3381
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3382
                                                   offsetof(CPUState, stick));
3383
                                    gen_helper_tick_set_count(r_tickptr,
3384
                                                              cpu_dst);
3385
                                    tcg_temp_free_ptr(r_tickptr);
3386
                                }
3387
                                break;
3388
                            case 0x19: /* System tick compare */
3389
#if !defined(CONFIG_USER_ONLY)
3390
                                if (!supervisor(dc))
3391
                                    goto illegal_insn;
3392
#endif
3393
                                {
3394
                                    TCGv_ptr r_tickptr;
3395

    
3396
                                    tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
3397
                                                   cpu_src2);
3398
                                    r_tickptr = tcg_temp_new_ptr();
3399
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3400
                                                   offsetof(CPUState, stick));
3401
                                    gen_helper_tick_set_limit(r_tickptr,
3402
                                                              cpu_stick_cmpr);
3403
                                    tcg_temp_free_ptr(r_tickptr);
3404
                                }
3405
                                break;
3406

    
3407
                            case 0x10: /* Performance Control */
3408
                            case 0x11: /* Performance Instrumentation
3409
                                          Counter */
3410
                            case 0x12: /* Dispatch Control */
3411
#endif
3412
                            default:
3413
                                goto illegal_insn;
3414
                            }
3415
                        }
3416
                        break;
3417
#if !defined(CONFIG_USER_ONLY)
3418
                    case 0x31: /* wrpsr, V9 saved, restored */
3419
                        {
3420
                            if (!supervisor(dc))
3421
                                goto priv_insn;
3422
#ifdef TARGET_SPARC64
3423
                            switch (rd) {
3424
                            case 0:
3425
                                gen_helper_saved();
3426
                                break;
3427
                            case 1:
3428
                                gen_helper_restored();
3429
                                break;
3430
                            case 2: /* UA2005 allclean */
3431
                            case 3: /* UA2005 otherw */
3432
                            case 4: /* UA2005 normalw */
3433
                            case 5: /* UA2005 invalw */
3434
                                // XXX
3435
                            default:
3436
                                goto illegal_insn;
3437
                            }
3438
#else
3439
                            tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3440
                            gen_helper_wrpsr(cpu_dst);
3441
                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3442
                            dc->cc_op = CC_OP_FLAGS;
3443
                            save_state(dc, cpu_cond);
3444
                            gen_op_next_insn();
3445
                            tcg_gen_exit_tb(0);
3446
                            dc->is_br = 1;
3447
#endif
3448
                        }
3449
                        break;
3450
                    case 0x32: /* wrwim, V9 wrpr */
3451
                        {
3452
                            if (!supervisor(dc))
3453
                                goto priv_insn;
3454
                            tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3455
#ifdef TARGET_SPARC64
3456
                            switch (rd) {
3457
                            case 0: // tpc
3458
                                {
3459
                                    TCGv_ptr r_tsptr;
3460

    
3461
                                    r_tsptr = tcg_temp_new_ptr();
3462
                                    gen_load_trap_state_at_tl(r_tsptr, cpu_env);
3463
                                    tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3464
                                                  offsetof(trap_state, tpc));
3465
                                    tcg_temp_free_ptr(r_tsptr);
3466
                                }
3467
                                break;
3468
                            case 1: // tnpc
3469
                                {
3470
                                    TCGv_ptr r_tsptr;
3471

    
3472
                                    r_tsptr = tcg_temp_new_ptr();
3473
                                    gen_load_trap_state_at_tl(r_tsptr, cpu_env);
3474
                                    tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3475
                                                  offsetof(trap_state, tnpc));
3476
                                    tcg_temp_free_ptr(r_tsptr);
3477
                                }
3478
                                break;
3479
                            case 2: // tstate
3480
                                {
3481
                                    TCGv_ptr r_tsptr;
3482

    
3483
                                    r_tsptr = tcg_temp_new_ptr();
3484
                                    gen_load_trap_state_at_tl(r_tsptr, cpu_env);
3485
                                    tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3486
                                                  offsetof(trap_state,
3487
                                                           tstate));
3488
                                    tcg_temp_free_ptr(r_tsptr);
3489
                                }
3490
                                break;
3491
                            case 3: // tt
3492
                                {
3493
                                    TCGv_ptr r_tsptr;
3494

    
3495
                                    r_tsptr = tcg_temp_new_ptr();
3496
                                    gen_load_trap_state_at_tl(r_tsptr, cpu_env);
3497
                                    tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3498
                                    tcg_gen_st_i32(cpu_tmp32, r_tsptr,
3499
                                                   offsetof(trap_state, tt));
3500
                                    tcg_temp_free_ptr(r_tsptr);
3501
                                }
3502
                                break;
3503
                            case 4: // tick
3504
                                {
3505
                                    TCGv_ptr r_tickptr;
3506

    
3507
                                    r_tickptr = tcg_temp_new_ptr();
3508
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3509
                                                   offsetof(CPUState, tick));
3510
                                    gen_helper_tick_set_count(r_tickptr,
3511
                                                              cpu_tmp0);
3512
                                    tcg_temp_free_ptr(r_tickptr);
3513
                                }
3514
                                break;
3515
                            case 5: // tba
3516
                                tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
3517
                                break;
3518
                            case 6: // pstate
3519
                                {
3520
                                    TCGv r_tmp = tcg_temp_local_new();
3521

    
3522
                                    tcg_gen_mov_tl(r_tmp, cpu_tmp0);
3523
                                    save_state(dc, cpu_cond);
3524
                                    gen_helper_wrpstate(r_tmp);
3525
                                    tcg_temp_free(r_tmp);
3526
                                    dc->npc = DYNAMIC_PC;
3527
                                }
3528
                                break;
3529
                            case 7: // tl
3530
                                {
3531
                                    TCGv r_tmp = tcg_temp_local_new();
3532

    
3533
                                    tcg_gen_mov_tl(r_tmp, cpu_tmp0);
3534
                                    save_state(dc, cpu_cond);
3535
                                    tcg_gen_trunc_tl_i32(cpu_tmp32, r_tmp);
3536
                                    tcg_temp_free(r_tmp);
3537
                                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
3538
                                                   offsetof(CPUSPARCState, tl));
3539
                                    dc->npc = DYNAMIC_PC;
3540
                                }
3541
                                break;
3542
                            case 8: // pil
3543
                                gen_helper_wrpil(cpu_tmp0);
3544
                                break;
3545
                            case 9: // cwp
3546
                                gen_helper_wrcwp(cpu_tmp0);
3547
                                break;
3548
                            case 10: // cansave
3549
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3550
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3551
                                               offsetof(CPUSPARCState,
3552
                                                        cansave));
3553
                                break;
3554
                            case 11: // canrestore
3555
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3556
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3557
                                               offsetof(CPUSPARCState,
3558
                                                        canrestore));
3559
                                break;
3560
                            case 12: // cleanwin
3561
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3562
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3563
                                               offsetof(CPUSPARCState,
3564
                                                        cleanwin));
3565
                                break;
3566
                            case 13: // otherwin
3567
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3568
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3569
                                               offsetof(CPUSPARCState,
3570
                                                        otherwin));
3571
                                break;
3572
                            case 14: // wstate
3573
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3574
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3575
                                               offsetof(CPUSPARCState,
3576
                                                        wstate));
3577
                                break;
3578
                            case 16: // UA2005 gl
3579
                                CHECK_IU_FEATURE(dc, GL);
3580
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3581
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3582
                                               offsetof(CPUSPARCState, gl));
3583
                                break;
3584
                            case 26: // UA2005 strand status
3585
                                CHECK_IU_FEATURE(dc, HYPV);
3586
                                if (!hypervisor(dc))
3587
                                    goto priv_insn;
3588
                                tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
3589
                                break;
3590
                            default:
3591
                                goto illegal_insn;
3592
                            }
3593
#else
3594
                            tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3595
                            if (dc->def->nwindows != 32)
3596
                                tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32,
3597
                                                (1 << dc->def->nwindows) - 1);
3598
                            tcg_gen_mov_i32(cpu_wim, cpu_tmp32);
3599
#endif
3600
                        }
3601
                        break;
3602
                    case 0x33: /* wrtbr, UA2005 wrhpr */
3603
                        {
3604
#ifndef TARGET_SPARC64
3605
                            if (!supervisor(dc))
3606
                                goto priv_insn;
3607
                            tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
3608
#else
3609
                            CHECK_IU_FEATURE(dc, HYPV);
3610
                            if (!hypervisor(dc))
3611
                                goto priv_insn;
3612
                            tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3613
                            switch (rd) {
3614
                            case 0: // hpstate
3615
                                // XXX gen_op_wrhpstate();
3616
                                save_state(dc, cpu_cond);
3617
                                gen_op_next_insn();
3618
                                tcg_gen_exit_tb(0);
3619
                                dc->is_br = 1;
3620
                                break;
3621
                            case 1: // htstate
3622
                                // XXX gen_op_wrhtstate();
3623
                                break;
3624
                            case 3: // hintp
3625
                                tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
3626
                                break;
3627
                            case 5: // htba
3628
                                tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
3629
                                break;
3630
                            case 31: // hstick_cmpr
3631
                                {
3632
                                    TCGv_ptr r_tickptr;
3633

    
3634
                                    tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
3635
                                    r_tickptr = tcg_temp_new_ptr();
3636
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3637
                                                   offsetof(CPUState, hstick));
3638
                                    gen_helper_tick_set_limit(r_tickptr,
3639
                                                              cpu_hstick_cmpr);
3640
                                    tcg_temp_free_ptr(r_tickptr);
3641
                                }
3642
                                break;
3643
                            case 6: // hver readonly
3644
                            default:
3645
                                goto illegal_insn;
3646
                            }
3647
#endif
3648
                        }
3649
                        break;
3650
#endif
3651
#ifdef TARGET_SPARC64
3652
                    case 0x2c: /* V9 movcc */
3653
                        {
3654
                            int cc = GET_FIELD_SP(insn, 11, 12);
3655
                            int cond = GET_FIELD_SP(insn, 14, 17);
3656
                            TCGv r_cond;
3657
                            int l1;
3658

    
3659
                            r_cond = tcg_temp_new();
3660
                            if (insn & (1 << 18)) {
3661
                                if (cc == 0)
3662
                                    gen_cond(r_cond, 0, cond, dc);
3663
                                else if (cc == 2)
3664
                                    gen_cond(r_cond, 1, cond, dc);
3665
                                else
3666
                                    goto illegal_insn;
3667
                            } else {
3668
                                gen_fcond(r_cond, cc, cond);
3669
                            }
3670

    
3671
                            l1 = gen_new_label();
3672

    
3673
                            tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3674
                            if (IS_IMM) {       /* immediate */
3675
                                TCGv r_const;
3676

    
3677
                                simm = GET_FIELD_SPs(insn, 0, 10);
3678
                                r_const = tcg_const_tl(simm);
3679
                                gen_movl_TN_reg(rd, r_const);
3680
                                tcg_temp_free(r_const);
3681
                            } else {
3682
                                rs2 = GET_FIELD_SP(insn, 0, 4);
3683
                                gen_movl_reg_TN(rs2, cpu_tmp0);
3684
                                gen_movl_TN_reg(rd, cpu_tmp0);
3685
                            }
3686
                            gen_set_label(l1);
3687
                            tcg_temp_free(r_cond);
3688
                            break;
3689
                        }
3690
                    case 0x2d: /* V9 sdivx */
3691
                        gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3692
                        gen_movl_TN_reg(rd, cpu_dst);
3693
                        break;
3694
                    case 0x2e: /* V9 popc */
3695
                        {
3696
                            cpu_src2 = get_src2(insn, cpu_src2);
3697
                            gen_helper_popc(cpu_dst, cpu_src2);
3698
                            gen_movl_TN_reg(rd, cpu_dst);
3699
                        }
3700
                    case 0x2f: /* V9 movr */
3701
                        {
3702
                            int cond = GET_FIELD_SP(insn, 10, 12);
3703
                            int l1;
3704

    
3705
                            cpu_src1 = get_src1(insn, cpu_src1);
3706

    
3707
                            l1 = gen_new_label();
3708

    
3709
                            tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3710
                                              cpu_src1, 0, l1);
3711
                            if (IS_IMM) {       /* immediate */
3712
                                TCGv r_const;
3713

    
3714
                                simm = GET_FIELD_SPs(insn, 0, 9);
3715
                                r_const = tcg_const_tl(simm);
3716
                                gen_movl_TN_reg(rd, r_const);
3717
                                tcg_temp_free(r_const);
3718
                            } else {
3719
                                rs2 = GET_FIELD_SP(insn, 0, 4);
3720
                                gen_movl_reg_TN(rs2, cpu_tmp0);
3721
                                gen_movl_TN_reg(rd, cpu_tmp0);
3722
                            }
3723
                            gen_set_label(l1);
3724
                            break;
3725
                        }
3726
#endif
3727
                    default:
3728
                        goto illegal_insn;
3729
                    }
3730
                }
3731
            } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3732
#ifdef TARGET_SPARC64
3733
                int opf = GET_FIELD_SP(insn, 5, 13);
3734
                rs1 = GET_FIELD(insn, 13, 17);
3735
                rs2 = GET_FIELD(insn, 27, 31);
3736
                if (gen_trap_ifnofpu(dc, cpu_cond))
3737
                    goto jmp_insn;
3738

    
3739
                switch (opf) {
3740
                case 0x000: /* VIS I edge8cc */
3741
                case 0x001: /* VIS II edge8n */
3742
                case 0x002: /* VIS I edge8lcc */
3743
                case 0x003: /* VIS II edge8ln */
3744
                case 0x004: /* VIS I edge16cc */
3745
                case 0x005: /* VIS II edge16n */
3746
                case 0x006: /* VIS I edge16lcc */
3747
                case 0x007: /* VIS II edge16ln */
3748
                case 0x008: /* VIS I edge32cc */
3749
                case 0x009: /* VIS II edge32n */
3750
                case 0x00a: /* VIS I edge32lcc */
3751
                case 0x00b: /* VIS II edge32ln */
3752
                    // XXX
3753
                    goto illegal_insn;
3754
                case 0x010: /* VIS I array8 */
3755
                    CHECK_FPU_FEATURE(dc, VIS1);
3756
                    cpu_src1 = get_src1(insn, cpu_src1);
3757
                    gen_movl_reg_TN(rs2, cpu_src2);
3758
                    gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
3759
                    gen_movl_TN_reg(rd, cpu_dst);
3760
                    break;
3761
                case 0x012: /* VIS I array16 */
3762
                    CHECK_FPU_FEATURE(dc, VIS1);
3763
                    cpu_src1 = get_src1(insn, cpu_src1);
3764
                    gen_movl_reg_TN(rs2, cpu_src2);
3765
                    gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
3766
                    tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3767
                    gen_movl_TN_reg(rd, cpu_dst);
3768
                    break;
3769
                case 0x014: /* VIS I array32 */
3770
                    CHECK_FPU_FEATURE(dc, VIS1);
3771
                    cpu_src1 = get_src1(insn, cpu_src1);
3772
                    gen_movl_reg_TN(rs2, cpu_src2);
3773
                    gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
3774
                    tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3775
                    gen_movl_TN_reg(rd, cpu_dst);
3776
                    break;
3777
                case 0x018: /* VIS I alignaddr */
3778
                    CHECK_FPU_FEATURE(dc, VIS1);
3779
                    cpu_src1 = get_src1(insn, cpu_src1);
3780
                    gen_movl_reg_TN(rs2, cpu_src2);
3781
                    gen_helper_alignaddr(cpu_dst, cpu_src1, cpu_src2);
3782
                    gen_movl_TN_reg(rd, cpu_dst);
3783
                    break;
3784
                case 0x019: /* VIS II bmask */
3785
                case 0x01a: /* VIS I alignaddrl */
3786
                    // XXX
3787
                    goto illegal_insn;
3788
                case 0x020: /* VIS I fcmple16 */
3789
                    CHECK_FPU_FEATURE(dc, VIS1);
3790
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3791
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3792
                    gen_helper_fcmple16();
3793
                    gen_op_store_DT0_fpr(DFPREG(rd));
3794
                    break;
3795
                case 0x022: /* VIS I fcmpne16 */
3796
                    CHECK_FPU_FEATURE(dc, VIS1);
3797
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3798
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3799
                    gen_helper_fcmpne16();
3800
                    gen_op_store_DT0_fpr(DFPREG(rd));
3801
                    break;
3802
                case 0x024: /* VIS I fcmple32 */
3803
                    CHECK_FPU_FEATURE(dc, VIS1);
3804
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3805
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3806
                    gen_helper_fcmple32();
3807
                    gen_op_store_DT0_fpr(DFPREG(rd));
3808
                    break;
3809
                case 0x026: /* VIS I fcmpne32 */
3810
                    CHECK_FPU_FEATURE(dc, VIS1);
3811
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3812
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3813
                    gen_helper_fcmpne32();
3814
                    gen_op_store_DT0_fpr(DFPREG(rd));
3815
                    break;
3816
                case 0x028: /* VIS I fcmpgt16 */
3817
                    CHECK_FPU_FEATURE(dc, VIS1);
3818
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3819
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3820
                    gen_helper_fcmpgt16();
3821
                    gen_op_store_DT0_fpr(DFPREG(rd));
3822
                    break;
3823
                case 0x02a: /* VIS I fcmpeq16 */
3824
                    CHECK_FPU_FEATURE(dc, VIS1);
3825
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3826
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3827
                    gen_helper_fcmpeq16();
3828
                    gen_op_store_DT0_fpr(DFPREG(rd));
3829
                    break;
3830
                case 0x02c: /* VIS I fcmpgt32 */
3831
                    CHECK_FPU_FEATURE(dc, VIS1);
3832
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3833
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3834
                    gen_helper_fcmpgt32();
3835
                    gen_op_store_DT0_fpr(DFPREG(rd));
3836
                    break;
3837
                case 0x02e: /* VIS I fcmpeq32 */
3838
                    CHECK_FPU_FEATURE(dc, VIS1);
3839
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3840
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3841
                    gen_helper_fcmpeq32();
3842
                    gen_op_store_DT0_fpr(DFPREG(rd));
3843
                    break;
3844
                case 0x031: /* VIS I fmul8x16 */
3845
                    CHECK_FPU_FEATURE(dc, VIS1);
3846
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3847
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3848
                    gen_helper_fmul8x16();
3849
                    gen_op_store_DT0_fpr(DFPREG(rd));
3850
                    break;
3851
                case 0x033: /* VIS I fmul8x16au */
3852
                    CHECK_FPU_FEATURE(dc, VIS1);
3853
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3854
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3855
                    gen_helper_fmul8x16au();
3856
                    gen_op_store_DT0_fpr(DFPREG(rd));
3857
                    break;
3858
                case 0x035: /* VIS I fmul8x16al */
3859
                    CHECK_FPU_FEATURE(dc, VIS1);
3860
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3861
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3862
                    gen_helper_fmul8x16al();
3863
                    gen_op_store_DT0_fpr(DFPREG(rd));
3864
                    break;
3865
                case 0x036: /* VIS I fmul8sux16 */
3866
                    CHECK_FPU_FEATURE(dc, VIS1);
3867
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3868
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3869
                    gen_helper_fmul8sux16();
3870
                    gen_op_store_DT0_fpr(DFPREG(rd));
3871
                    break;
3872
                case 0x037: /* VIS I fmul8ulx16 */
3873
                    CHECK_FPU_FEATURE(dc, VIS1);
3874
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3875
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3876
                    gen_helper_fmul8ulx16();
3877
                    gen_op_store_DT0_fpr(DFPREG(rd));
3878
                    break;
3879
                case 0x038: /* VIS I fmuld8sux16 */
3880
                    CHECK_FPU_FEATURE(dc, VIS1);
3881
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3882
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3883
                    gen_helper_fmuld8sux16();
3884
                    gen_op_store_DT0_fpr(DFPREG(rd));
3885
                    break;
3886
                case 0x039: /* VIS I fmuld8ulx16 */
3887
                    CHECK_FPU_FEATURE(dc, VIS1);
3888
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3889
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3890
                    gen_helper_fmuld8ulx16();
3891
                    gen_op_store_DT0_fpr(DFPREG(rd));
3892
                    break;
3893
                case 0x03a: /* VIS I fpack32 */
3894
                case 0x03b: /* VIS I fpack16 */
3895
                case 0x03d: /* VIS I fpackfix */
3896
                case 0x03e: /* VIS I pdist */
3897
                    // XXX
3898
                    goto illegal_insn;
3899
                case 0x048: /* VIS I faligndata */
3900
                    CHECK_FPU_FEATURE(dc, VIS1);
3901
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3902
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3903
                    gen_helper_faligndata();
3904
                    gen_op_store_DT0_fpr(DFPREG(rd));
3905
                    break;
3906
                case 0x04b: /* VIS I fpmerge */
3907
                    CHECK_FPU_FEATURE(dc, VIS1);
3908
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3909
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3910
                    gen_helper_fpmerge();
3911
                    gen_op_store_DT0_fpr(DFPREG(rd));
3912
                    break;
3913
                case 0x04c: /* VIS II bshuffle */
3914
                    // XXX
3915
                    goto illegal_insn;
3916
                case 0x04d: /* VIS I fexpand */
3917
                    CHECK_FPU_FEATURE(dc, VIS1);
3918
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3919
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3920
                    gen_helper_fexpand();
3921
                    gen_op_store_DT0_fpr(DFPREG(rd));
3922
                    break;
3923
                case 0x050: /* VIS I fpadd16 */
3924
                    CHECK_FPU_FEATURE(dc, VIS1);
3925
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3926
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3927
                    gen_helper_fpadd16();
3928
                    gen_op_store_DT0_fpr(DFPREG(rd));
3929
                    break;
3930
                case 0x051: /* VIS I fpadd16s */
3931
                    CHECK_FPU_FEATURE(dc, VIS1);
3932
                    gen_helper_fpadd16s(cpu_fpr[rd],
3933
                                        cpu_fpr[rs1], cpu_fpr[rs2]);
3934
                    break;
3935
                case 0x052: /* VIS I fpadd32 */
3936
                    CHECK_FPU_FEATURE(dc, VIS1);
3937
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3938
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3939
                    gen_helper_fpadd32();
3940
                    gen_op_store_DT0_fpr(DFPREG(rd));
3941
                    break;
3942
                case 0x053: /* VIS I fpadd32s */
3943
                    CHECK_FPU_FEATURE(dc, VIS1);
3944
                    gen_helper_fpadd32s(cpu_fpr[rd],
3945
                                        cpu_fpr[rs1], cpu_fpr[rs2]);
3946
                    break;
3947
                case 0x054: /* VIS I fpsub16 */
3948
                    CHECK_FPU_FEATURE(dc, VIS1);
3949
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3950
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3951
                    gen_helper_fpsub16();
3952
                    gen_op_store_DT0_fpr(DFPREG(rd));
3953
                    break;
3954
                case 0x055: /* VIS I fpsub16s */
3955
                    CHECK_FPU_FEATURE(dc, VIS1);
3956
                    gen_helper_fpsub16s(cpu_fpr[rd],
3957
                                        cpu_fpr[rs1], cpu_fpr[rs2]);
3958
                    break;
3959
                case 0x056: /* VIS I fpsub32 */
3960
                    CHECK_FPU_FEATURE(dc, VIS1);
3961
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3962
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3963
                    gen_helper_fpsub32();
3964
                    gen_op_store_DT0_fpr(DFPREG(rd));
3965
                    break;
3966
                case 0x057: /* VIS I fpsub32s */
3967
                    CHECK_FPU_FEATURE(dc, VIS1);
3968
                    gen_helper_fpsub32s(cpu_fpr[rd],
3969
                                        cpu_fpr[rs1], cpu_fpr[rs2]);
3970
                    break;
3971
                case 0x060: /* VIS I fzero */
3972
                    CHECK_FPU_FEATURE(dc, VIS1);
3973
                    tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], 0);
3974
                    tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], 0);
3975
                    break;
3976
                case 0x061: /* VIS I fzeros */
3977
                    CHECK_FPU_FEATURE(dc, VIS1);
3978
                    tcg_gen_movi_i32(cpu_fpr[rd], 0);
3979
                    break;
3980
                case 0x062: /* VIS I fnor */
3981
                    CHECK_FPU_FEATURE(dc, VIS1);
3982
                    tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
3983
                                    cpu_fpr[DFPREG(rs2)]);
3984
                    tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
3985
                                    cpu_fpr[DFPREG(rs2) + 1]);
3986
                    break;
3987
                case 0x063: /* VIS I fnors */
3988
                    CHECK_FPU_FEATURE(dc, VIS1);
3989
                    tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
3990
                    break;
3991
                case 0x064: /* VIS I fandnot2 */
3992
                    CHECK_FPU_FEATURE(dc, VIS1);
3993
                    tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
3994
                                     cpu_fpr[DFPREG(rs2)]);
3995
                    tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
3996
                                     cpu_fpr[DFPREG(rs1) + 1],
3997
                                     cpu_fpr[DFPREG(rs2) + 1]);
3998
                    break;
3999
                case 0x065: /* VIS I fandnot2s */
4000
                    CHECK_FPU_FEATURE(dc, VIS1);
4001
                    tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
4002
                    break;
4003
                case 0x066: /* VIS I fnot2 */
4004
                    CHECK_FPU_FEATURE(dc, VIS1);
4005
                    tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]);
4006
                    tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
4007
                                    cpu_fpr[DFPREG(rs2) + 1]);
4008
                    break;
4009
                case 0x067: /* VIS I fnot2s */
4010
                    CHECK_FPU_FEATURE(dc, VIS1);
4011
                    tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs2]);
4012
                    break;
4013
                case 0x068: /* VIS I fandnot1 */
4014
                    CHECK_FPU_FEATURE(dc, VIS1);
4015
                    tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)],
4016
                                     cpu_fpr[DFPREG(rs1)]);
4017
                    tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
4018
                                     cpu_fpr[DFPREG(rs2) + 1],
4019
                                     cpu_fpr[DFPREG(rs1) + 1]);
4020
                    break;
4021
                case 0x069: /* VIS I fandnot1s */
4022
                    CHECK_FPU_FEATURE(dc, VIS1);
4023
                    tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]);
4024
                    break;
4025
                case 0x06a: /* VIS I fnot1 */
4026
                    CHECK_FPU_FEATURE(dc, VIS1);
4027
                    tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]);
4028
                    tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
4029
                                    cpu_fpr[DFPREG(rs1) + 1]);
4030
                    break;
4031
                case 0x06b: /* VIS I fnot1s */
4032
                    CHECK_FPU_FEATURE(dc, VIS1);
4033
                    tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs1]);
4034
                    break;
4035
                case 0x06c: /* VIS I fxor */
4036
                    CHECK_FPU_FEATURE(dc, VIS1);
4037
                    tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
4038
                                    cpu_fpr[DFPREG(rs2)]);
4039
                    tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1],
4040
                                    cpu_fpr[DFPREG(rs1) + 1],
4041
                                    cpu_fpr[DFPREG(rs2) + 1]);
4042
                    break;
4043
                case 0x06d: /* VIS I fxors */
4044
                    CHECK_FPU_FEATURE(dc, VIS1);
4045
                    tcg_gen_xor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
4046
                    break;
4047
                case 0x06e: /* VIS I fnand */
4048
                    CHECK_FPU_FEATURE(dc, VIS1);
4049
                    tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
4050
                                     cpu_fpr[DFPREG(rs2)]);
4051
                    tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
4052
                                     cpu_fpr[DFPREG(rs2) + 1]);
4053
                    break;
4054
                case 0x06f: /* VIS I fnands */
4055
                    CHECK_FPU_FEATURE(dc, VIS1);
4056
                    tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
4057
                    break;
4058
                case 0x070: /* VIS I fand */
4059
                    CHECK_FPU_FEATURE(dc, VIS1);
4060
                    tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
4061
                                    cpu_fpr[DFPREG(rs2)]);
4062
                    tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1],
4063
                                    cpu_fpr[DFPREG(rs1) + 1],
4064
                                    cpu_fpr[DFPREG(rs2) + 1]);
4065
                    break;
4066
                case 0x071: /* VIS I fands */
4067
                    CHECK_FPU_FEATURE(dc, VIS1);
4068
                    tcg_gen_and_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
4069
                    break;
4070
                case 0x072: /* VIS I fxnor */
4071
                    CHECK_FPU_FEATURE(dc, VIS1);
4072
                    tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
4073
                    tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
4074
                                    cpu_fpr[DFPREG(rs1)]);
4075
                    tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1);
4076
                    tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
4077
                                    cpu_fpr[DFPREG(rs1) + 1]);
4078
                    break;
4079
                case 0x073: /* VIS I fxnors */
4080
                    CHECK_FPU_FEATURE(dc, VIS1);
4081
                    tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
4082
                    tcg_gen_xor_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]);
4083
                    break;
4084
                case 0x074: /* VIS I fsrc1 */
4085
                    CHECK_FPU_FEATURE(dc, VIS1);
4086
                    tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]);
4087
                    tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
4088
                                    cpu_fpr[DFPREG(rs1) + 1]);
4089
                    break;
4090
                case 0x075: /* VIS I fsrc1s */
4091
                    CHECK_FPU_FEATURE(dc, VIS1);
4092
                    tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs1]);
4093
                    break;
4094
                case 0x076: /* VIS I fornot2 */
4095
                    CHECK_FPU_FEATURE(dc, VIS1);
4096
                    tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
4097
                                    cpu_fpr[DFPREG(rs2)]);
4098
                    tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
4099
                                    cpu_fpr[DFPREG(rs1) + 1],
4100
                                    cpu_fpr[DFPREG(rs2) + 1]);
4101
                    break;
4102
                case 0x077: /* VIS I fornot2s */
4103
                    CHECK_FPU_FEATURE(dc, VIS1);
4104
                    tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
4105
                    break;
4106
                case 0x078: /* VIS I fsrc2 */
4107
                    CHECK_FPU_FEATURE(dc, VIS1);
4108
                    gen_op_load_fpr_DT0(DFPREG(rs2));
4109
                    gen_op_store_DT0_fpr(DFPREG(rd));
4110
                    break;
4111
                case 0x079: /* VIS I fsrc2s */
4112
                    CHECK_FPU_FEATURE(dc, VIS1);
4113
                    tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
4114
                    break;
4115
                case 0x07a: /* VIS I fornot1 */
4116
                    CHECK_FPU_FEATURE(dc, VIS1);
4117
                    tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)],
4118
                                    cpu_fpr[DFPREG(rs1)]);
4119
                    tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
4120
                                    cpu_fpr[DFPREG(rs2) + 1],
4121
                                    cpu_fpr[DFPREG(rs1) + 1]);
4122
                    break;
4123
                case 0x07b: /* VIS I fornot1s */
4124
                    CHECK_FPU_FEATURE(dc, VIS1);
4125
                    tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]);
4126
                    break;
4127
                case 0x07c: /* VIS I for */
4128
                    CHECK_FPU_FEATURE(dc, VIS1);
4129
                    tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
4130
                                   cpu_fpr[DFPREG(rs2)]);
4131
                    tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1],
4132
                                   cpu_fpr[DFPREG(rs1) + 1],
4133
                                   cpu_fpr[DFPREG(rs2) + 1]);
4134
                    break;
4135
                case 0x07d: /* VIS I fors */
4136
                    CHECK_FPU_FEATURE(dc, VIS1);
4137
                    tcg_gen_or_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
4138
                    break;
4139
                case 0x07e: /* VIS I fone */
4140
                    CHECK_FPU_FEATURE(dc, VIS1);
4141
                    tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], -1);
4142
                    tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], -1);
4143
                    break;
4144
                case 0x07f: /* VIS I fones */
4145
                    CHECK_FPU_FEATURE(dc, VIS1);
4146
                    tcg_gen_movi_i32(cpu_fpr[rd], -1);
4147
                    break;
4148
                case 0x080: /* VIS I shutdown */
4149
                case 0x081: /* VIS II siam */
4150
                    // XXX
4151
                    goto illegal_insn;
4152
                default:
4153
                    goto illegal_insn;
4154
                }
4155
#else
4156
                goto ncp_insn;
4157
#endif
4158
            } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4159
#ifdef TARGET_SPARC64
4160
                goto illegal_insn;
4161
#else
4162
                goto ncp_insn;
4163
#endif
4164
#ifdef TARGET_SPARC64
4165
            } else if (xop == 0x39) { /* V9 return */
4166
                TCGv_i32 r_const;
4167

    
4168
                save_state(dc, cpu_cond);
4169
                cpu_src1 = get_src1(insn, cpu_src1);
4170
                if (IS_IMM) {   /* immediate */
4171
                    simm = GET_FIELDs(insn, 19, 31);
4172
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
4173
                } else {                /* register */
4174
                    rs2 = GET_FIELD(insn, 27, 31);
4175
                    if (rs2) {
4176
                        gen_movl_reg_TN(rs2, cpu_src2);
4177
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4178
                    } else
4179
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
4180
                }
4181
                gen_helper_restore();
4182
                gen_mov_pc_npc(dc, cpu_cond);
4183
                r_const = tcg_const_i32(3);
4184
                gen_helper_check_align(cpu_dst, r_const);
4185
                tcg_temp_free_i32(r_const);
4186
                tcg_gen_mov_tl(cpu_npc, cpu_dst);
4187
                dc->npc = DYNAMIC_PC;
4188
                goto jmp_insn;
4189
#endif
4190
            } else {
4191
                cpu_src1 = get_src1(insn, cpu_src1);
4192
                if (IS_IMM) {   /* immediate */
4193
                    simm = GET_FIELDs(insn, 19, 31);
4194
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
4195
                } else {                /* register */
4196
                    rs2 = GET_FIELD(insn, 27, 31);
4197
                    if (rs2) {
4198
                        gen_movl_reg_TN(rs2, cpu_src2);
4199
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4200
                    } else
4201
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
4202
                }
4203
                switch (xop) {
4204
                case 0x38:      /* jmpl */
4205
                    {
4206
                        TCGv r_pc;
4207
                        TCGv_i32 r_const;
4208

    
4209
                        r_pc = tcg_const_tl(dc->pc);
4210
                        gen_movl_TN_reg(rd, r_pc);
4211
                        tcg_temp_free(r_pc);
4212
                        gen_mov_pc_npc(dc, cpu_cond);
4213
                        r_const = tcg_const_i32(3);
4214
                        gen_helper_check_align(cpu_dst, r_const);
4215
                        tcg_temp_free_i32(r_const);
4216
                        tcg_gen_mov_tl(cpu_npc, cpu_dst);
4217
                        dc->npc = DYNAMIC_PC;
4218
                    }
4219
                    goto jmp_insn;
4220
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4221
                case 0x39:      /* rett, V9 return */
4222
                    {
4223
                        TCGv_i32 r_const;
4224

    
4225
                        if (!supervisor(dc))
4226
                            goto priv_insn;
4227
                        gen_mov_pc_npc(dc, cpu_cond);
4228
                        r_const = tcg_const_i32(3);
4229
                        gen_helper_check_align(cpu_dst, r_const);
4230
                        tcg_temp_free_i32(r_const);
4231
                        tcg_gen_mov_tl(cpu_npc, cpu_dst);
4232
                        dc->npc = DYNAMIC_PC;
4233
                        gen_helper_rett();
4234
                    }
4235
                    goto jmp_insn;
4236
#endif
4237
                case 0x3b: /* flush */
4238
                    if (!((dc)->def->features & CPU_FEATURE_FLUSH))
4239
                        goto unimp_flush;
4240
                    /* nop */
4241
                    break;
4242
                case 0x3c:      /* save */
4243
                    save_state(dc, cpu_cond);
4244
                    gen_helper_save();
4245
                    gen_movl_TN_reg(rd, cpu_dst);
4246
                    break;
4247
                case 0x3d:      /* restore */
4248
                    save_state(dc, cpu_cond);
4249
                    gen_helper_restore();
4250
                    gen_movl_TN_reg(rd, cpu_dst);
4251
                    break;
4252
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4253
                case 0x3e:      /* V9 done/retry */
4254
                    {
4255
                        switch (rd) {
4256
                        case 0:
4257
                            if (!supervisor(dc))
4258
                                goto priv_insn;
4259
                            dc->npc = DYNAMIC_PC;
4260
                            dc->pc = DYNAMIC_PC;
4261
                            gen_helper_done();
4262
                            goto jmp_insn;
4263
                        case 1:
4264
                            if (!supervisor(dc))
4265
                                goto priv_insn;
4266
                            dc->npc = DYNAMIC_PC;
4267
                            dc->pc = DYNAMIC_PC;
4268
                            gen_helper_retry();
4269
                            goto jmp_insn;
4270
                        default:
4271
                            goto illegal_insn;
4272
                        }
4273
                    }
4274
                    break;
4275
#endif
4276
                default:
4277
                    goto illegal_insn;
4278
                }
4279
            }
4280
            break;
4281
        }
4282
        break;
4283
    case 3:                     /* load/store instructions */
4284
        {
4285
            unsigned int xop = GET_FIELD(insn, 7, 12);
4286

    
4287
            /* flush pending conditional evaluations before exposing
4288
               cpu state */
4289
            if (dc->cc_op != CC_OP_FLAGS) {
4290
                dc->cc_op = CC_OP_FLAGS;
4291
                gen_helper_compute_psr();
4292
            }
4293
            cpu_src1 = get_src1(insn, cpu_src1);
4294
            if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
4295
                rs2 = GET_FIELD(insn, 27, 31);
4296
                gen_movl_reg_TN(rs2, cpu_src2);
4297
                tcg_gen_mov_tl(cpu_addr, cpu_src1);
4298
            } else if (IS_IMM) {     /* immediate */
4299
                simm = GET_FIELDs(insn, 19, 31);
4300
                tcg_gen_addi_tl(cpu_addr, cpu_src1, simm);
4301
            } else {            /* register */
4302
                rs2 = GET_FIELD(insn, 27, 31);
4303
                if (rs2 != 0) {
4304
                    gen_movl_reg_TN(rs2, cpu_src2);
4305
                    tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4306
                } else
4307
                    tcg_gen_mov_tl(cpu_addr, cpu_src1);
4308
            }
4309
            if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4310
                (xop > 0x17 && xop <= 0x1d ) ||
4311
                (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4312
                switch (xop) {
4313
                case 0x0:       /* ld, V9 lduw, load unsigned word */
4314
                    gen_address_mask(dc, cpu_addr);
4315
                    tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4316
                    break;
4317
                case 0x1:       /* ldub, load unsigned byte */
4318
                    gen_address_mask(dc, cpu_addr);
4319
                    tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4320
                    break;
4321
                case 0x2:       /* lduh, load unsigned halfword */
4322
                    gen_address_mask(dc, cpu_addr);
4323
                    tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4324
                    break;
4325
                case 0x3:       /* ldd, load double word */
4326
                    if (rd & 1)
4327
                        goto illegal_insn;
4328
                    else {
4329
                        TCGv_i32 r_const;
4330

    
4331
                        save_state(dc, cpu_cond);
4332
                        r_const = tcg_const_i32(7);
4333
                        gen_helper_check_align(cpu_addr, r_const); // XXX remove
4334
                        tcg_temp_free_i32(r_const);
4335
                        gen_address_mask(dc, cpu_addr);
4336
                        tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4337
                        tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4338
                        tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4339
                        gen_movl_TN_reg(rd + 1, cpu_tmp0);
4340
                        tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4341
                        tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4342
                        tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4343
                    }
4344
                    break;
4345
                case 0x9:       /* ldsb, load signed byte */
4346
                    gen_address_mask(dc, cpu_addr);
4347
                    tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4348
                    break;
4349
                case 0xa:       /* ldsh, load signed halfword */
4350
                    gen_address_mask(dc, cpu_addr);
4351
                    tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4352
                    break;
4353
                case 0xd:       /* ldstub -- XXX: should be atomically */
4354
                    {
4355
                        TCGv r_const;
4356

    
4357
                        gen_address_mask(dc, cpu_addr);
4358
                        tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4359
                        r_const = tcg_const_tl(0xff);
4360
                        tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4361
                        tcg_temp_free(r_const);
4362
                    }
4363
                    break;
4364
                case 0x0f:      /* swap, swap register with memory. Also
4365
                                   atomically */
4366
                    CHECK_IU_FEATURE(dc, SWAP);
4367
                    gen_movl_reg_TN(rd, cpu_val);
4368
                    gen_address_mask(dc, cpu_addr);
4369
                    tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
4370
                    tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4371
                    tcg_gen_mov_tl(cpu_val, cpu_tmp0);
4372
                    break;
4373
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4374
                case 0x10:      /* lda, V9 lduwa, load word alternate */
4375
#ifndef TARGET_SPARC64
4376
                    if (IS_IMM)
4377
                        goto illegal_insn;
4378
                    if (!supervisor(dc))
4379
                        goto priv_insn;
4380
#endif
4381
                    save_state(dc, cpu_cond);
4382
                    gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4383
                    break;
4384
                case 0x11:      /* lduba, load unsigned byte alternate */
4385
#ifndef TARGET_SPARC64
4386
                    if (IS_IMM)
4387
                        goto illegal_insn;
4388
                    if (!supervisor(dc))
4389
                        goto priv_insn;
4390
#endif
4391
                    save_state(dc, cpu_cond);
4392
                    gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4393
                    break;
4394
                case 0x12:      /* lduha, load unsigned halfword alternate */
4395
#ifndef TARGET_SPARC64
4396
                    if (IS_IMM)
4397
                        goto illegal_insn;
4398
                    if (!supervisor(dc))
4399
                        goto priv_insn;
4400
#endif
4401
                    save_state(dc, cpu_cond);
4402
                    gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4403
                    break;
4404
                case 0x13:      /* ldda, load double word alternate */
4405
#ifndef TARGET_SPARC64
4406
                    if (IS_IMM)
4407
                        goto illegal_insn;
4408
                    if (!supervisor(dc))
4409
                        goto priv_insn;
4410
#endif
4411
                    if (rd & 1)
4412
                        goto illegal_insn;
4413
                    save_state(dc, cpu_cond);
4414
                    gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
4415
                    goto skip_move;
4416
                case 0x19:      /* ldsba, load signed byte alternate */
4417
#ifndef TARGET_SPARC64
4418
                    if (IS_IMM)
4419
                        goto illegal_insn;
4420
                    if (!supervisor(dc))
4421
                        goto priv_insn;
4422
#endif
4423
                    save_state(dc, cpu_cond);
4424
                    gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4425
                    break;
4426
                case 0x1a:      /* ldsha, load signed halfword alternate */
4427
#ifndef TARGET_SPARC64
4428
                    if (IS_IMM)
4429
                        goto illegal_insn;
4430
                    if (!supervisor(dc))
4431
                        goto priv_insn;
4432
#endif
4433
                    save_state(dc, cpu_cond);
4434
                    gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4435
                    break;
4436
                case 0x1d:      /* ldstuba -- XXX: should be atomically */
4437
#ifndef TARGET_SPARC64
4438
                    if (IS_IMM)
4439
                        goto illegal_insn;
4440
                    if (!supervisor(dc))
4441
                        goto priv_insn;
4442
#endif
4443
                    save_state(dc, cpu_cond);
4444
                    gen_ldstub_asi(cpu_val, cpu_addr, insn);
4445
                    break;
4446
                case 0x1f:      /* swapa, swap reg with alt. memory. Also
4447
                                   atomically */
4448
                    CHECK_IU_FEATURE(dc, SWAP);
4449
#ifndef TARGET_SPARC64
4450
                    if (IS_IMM)
4451
                        goto illegal_insn;
4452
                    if (!supervisor(dc))
4453
                        goto priv_insn;
4454
#endif
4455
                    save_state(dc, cpu_cond);
4456
                    gen_movl_reg_TN(rd, cpu_val);
4457
                    gen_swap_asi(cpu_val, cpu_addr, insn);
4458
                    break;
4459

    
4460
#ifndef TARGET_SPARC64
4461
                case 0x30: /* ldc */
4462
                case 0x31: /* ldcsr */
4463
                case 0x33: /* lddc */
4464
                    goto ncp_insn;
4465
#endif
4466
#endif
4467
#ifdef TARGET_SPARC64
4468
                case 0x08: /* V9 ldsw */
4469
                    gen_address_mask(dc, cpu_addr);
4470
                    tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4471
                    break;
4472
                case 0x0b: /* V9 ldx */
4473
                    gen_address_mask(dc, cpu_addr);
4474
                    tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4475
                    break;
4476
                case 0x18: /* V9 ldswa */
4477
                    save_state(dc, cpu_cond);
4478
                    gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4479
                    break;
4480
                case 0x1b: /* V9 ldxa */
4481
                    save_state(dc, cpu_cond);
4482
                    gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4483
                    break;
4484
                case 0x2d: /* V9 prefetch, no effect */
4485
                    goto skip_move;
4486
                case 0x30: /* V9 ldfa */
4487
                    if (gen_trap_ifnofpu(dc, cpu_cond)) {
4488
                        goto jmp_insn;
4489
                    }
4490
                    save_state(dc, cpu_cond);
4491
                    gen_ldf_asi(cpu_addr, insn, 4, rd);
4492
                    goto skip_move;
4493
                case 0x33: /* V9 lddfa */
4494
                    if (gen_trap_ifnofpu(dc, cpu_cond)) {
4495
                        goto jmp_insn;
4496
                    }
4497
                    save_state(dc, cpu_cond);
4498
                    gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4499
                    goto skip_move;
4500
                case 0x3d: /* V9 prefetcha, no effect */
4501
                    goto skip_move;
4502
                case 0x32: /* V9 ldqfa */
4503
                    CHECK_FPU_FEATURE(dc, FLOAT128);
4504
                    if (gen_trap_ifnofpu(dc, cpu_cond)) {
4505
                        goto jmp_insn;
4506
                    }
4507
                    save_state(dc, cpu_cond);
4508
                    gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4509
                    goto skip_move;
4510
#endif
4511
                default:
4512
                    goto illegal_insn;
4513
                }
4514
                gen_movl_TN_reg(rd, cpu_val);
4515
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4516
            skip_move: ;
4517
#endif
4518
            } else if (xop >= 0x20 && xop < 0x24) {
4519
                if (gen_trap_ifnofpu(dc, cpu_cond))
4520
                    goto jmp_insn;
4521
                save_state(dc, cpu_cond);
4522
                switch (xop) {
4523
                case 0x20:      /* ldf, load fpreg */
4524
                    gen_address_mask(dc, cpu_addr);
4525
                    tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
4526
                    tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0);
4527
                    break;
4528
                case 0x21:      /* ldfsr, V9 ldxfsr */
4529
#ifdef TARGET_SPARC64
4530
                    gen_address_mask(dc, cpu_addr);
4531
                    if (rd == 1) {
4532
                        tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4533
                        gen_helper_ldxfsr(cpu_tmp64);
4534
                    } else {
4535
                        tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
4536
                        tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
4537
                        gen_helper_ldfsr(cpu_tmp32);
4538
                    }
4539
#else
4540
                    {
4541
                        tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4542
                        gen_helper_ldfsr(cpu_tmp32);
4543
                    }
4544
#endif
4545
                    break;
4546
                case 0x22:      /* ldqf, load quad fpreg */
4547
                    {
4548
                        TCGv_i32 r_const;
4549

    
4550
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4551
                        r_const = tcg_const_i32(dc->mem_idx);
4552
                        gen_address_mask(dc, cpu_addr);
4553
                        gen_helper_ldqf(cpu_addr, r_const);
4554
                        tcg_temp_free_i32(r_const);
4555
                        gen_op_store_QT0_fpr(QFPREG(rd));
4556
                    }
4557
                    break;
4558
                case 0x23:      /* lddf, load double fpreg */
4559
                    {
4560
                        TCGv_i32 r_const;
4561

    
4562
                        r_const = tcg_const_i32(dc->mem_idx);
4563
                        gen_address_mask(dc, cpu_addr);
4564
                        gen_helper_lddf(cpu_addr, r_const);
4565
                        tcg_temp_free_i32(r_const);
4566
                        gen_op_store_DT0_fpr(DFPREG(rd));
4567
                    }
4568
                    break;
4569
                default:
4570
                    goto illegal_insn;
4571
                }
4572
            } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
4573
                       xop == 0xe || xop == 0x1e) {
4574
                gen_movl_reg_TN(rd, cpu_val);
4575
                switch (xop) {
4576
                case 0x4: /* st, store word */
4577
                    gen_address_mask(dc, cpu_addr);
4578
                    tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4579
                    break;
4580
                case 0x5: /* stb, store byte */
4581
                    gen_address_mask(dc, cpu_addr);
4582
                    tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4583
                    break;
4584
                case 0x6: /* sth, store halfword */
4585
                    gen_address_mask(dc, cpu_addr);
4586
                    tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4587
                    break;
4588
                case 0x7: /* std, store double word */
4589
                    if (rd & 1)
4590
                        goto illegal_insn;
4591
                    else {
4592
                        TCGv_i32 r_const;
4593

    
4594
                        save_state(dc, cpu_cond);
4595
                        gen_address_mask(dc, cpu_addr);
4596
                        r_const = tcg_const_i32(7);
4597
                        gen_helper_check_align(cpu_addr, r_const); // XXX remove
4598
                        tcg_temp_free_i32(r_const);
4599
                        gen_movl_reg_TN(rd + 1, cpu_tmp0);
4600
                        tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, cpu_val);
4601
                        tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4602
                    }
4603
                    break;
4604
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4605
                case 0x14: /* sta, V9 stwa, store word alternate */
4606
#ifndef TARGET_SPARC64
4607
                    if (IS_IMM)
4608
                        goto illegal_insn;
4609
                    if (!supervisor(dc))
4610
                        goto priv_insn;
4611
#endif
4612
                    save_state(dc, cpu_cond);
4613
                    gen_st_asi(cpu_val, cpu_addr, insn, 4);
4614
                    dc->npc = DYNAMIC_PC;
4615
                    break;
4616
                case 0x15: /* stba, store byte alternate */
4617
#ifndef TARGET_SPARC64
4618
                    if (IS_IMM)
4619
                        goto illegal_insn;
4620
                    if (!supervisor(dc))
4621
                        goto priv_insn;
4622
#endif
4623
                    save_state(dc, cpu_cond);
4624
                    gen_st_asi(cpu_val, cpu_addr, insn, 1);
4625
                    dc->npc = DYNAMIC_PC;
4626
                    break;
4627
                case 0x16: /* stha, store halfword alternate */
4628
#ifndef TARGET_SPARC64
4629
                    if (IS_IMM)
4630
                        goto illegal_insn;
4631
                    if (!supervisor(dc))
4632
                        goto priv_insn;
4633
#endif
4634
                    save_state(dc, cpu_cond);
4635
                    gen_st_asi(cpu_val, cpu_addr, insn, 2);
4636
                    dc->npc = DYNAMIC_PC;
4637
                    break;
4638
                case 0x17: /* stda, store double word alternate */
4639
#ifndef TARGET_SPARC64
4640
                    if (IS_IMM)
4641
                        goto illegal_insn;
4642
                    if (!supervisor(dc))
4643
                        goto priv_insn;
4644
#endif
4645
                    if (rd & 1)
4646
                        goto illegal_insn;
4647
                    else {
4648
                        save_state(dc, cpu_cond);
4649
                        gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4650
                    }
4651
                    break;
4652
#endif
4653
#ifdef TARGET_SPARC64
4654
                case 0x0e: /* V9 stx */
4655
                    gen_address_mask(dc, cpu_addr);
4656
                    tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4657
                    break;
4658
                case 0x1e: /* V9 stxa */
4659
                    save_state(dc, cpu_cond);
4660
                    gen_st_asi(cpu_val, cpu_addr, insn, 8);
4661
                    dc->npc = DYNAMIC_PC;
4662
                    break;
4663
#endif
4664
                default:
4665
                    goto illegal_insn;
4666
                }
4667
            } else if (xop > 0x23 && xop < 0x28) {
4668
                if (gen_trap_ifnofpu(dc, cpu_cond))
4669
                    goto jmp_insn;
4670
                save_state(dc, cpu_cond);
4671
                switch (xop) {
4672
                case 0x24: /* stf, store fpreg */
4673
                    gen_address_mask(dc, cpu_addr);
4674
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]);
4675
                    tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx);
4676
                    break;
4677
                case 0x25: /* stfsr, V9 stxfsr */
4678
#ifdef TARGET_SPARC64
4679
                    gen_address_mask(dc, cpu_addr);
4680
                    tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr));
4681
                    if (rd == 1)
4682
                        tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4683
                    else
4684
                        tcg_gen_qemu_st32(cpu_tmp64, cpu_addr, dc->mem_idx);
4685
#else
4686
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr));
4687
                    tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4688
#endif
4689
                    break;
4690
                case 0x26:
4691
#ifdef TARGET_SPARC64
4692
                    /* V9 stqf, store quad fpreg */
4693
                    {
4694
                        TCGv_i32 r_const;
4695

    
4696
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4697
                        gen_op_load_fpr_QT0(QFPREG(rd));
4698
                        r_const = tcg_const_i32(dc->mem_idx);
4699
                        gen_address_mask(dc, cpu_addr);
4700
                        gen_helper_stqf(cpu_addr, r_const);
4701
                        tcg_temp_free_i32(r_const);
4702
                    }
4703
                    break;
4704
#else /* !TARGET_SPARC64 */
4705
                    /* stdfq, store floating point queue */
4706
#if defined(CONFIG_USER_ONLY)
4707
                    goto illegal_insn;
4708
#else
4709
                    if (!supervisor(dc))
4710
                        goto priv_insn;
4711
                    if (gen_trap_ifnofpu(dc, cpu_cond))
4712
                        goto jmp_insn;
4713
                    goto nfq_insn;
4714
#endif
4715
#endif
4716
                case 0x27: /* stdf, store double fpreg */
4717
                    {
4718
                        TCGv_i32 r_const;
4719

    
4720
                        gen_op_load_fpr_DT0(DFPREG(rd));
4721
                        r_const = tcg_const_i32(dc->mem_idx);
4722
                        gen_address_mask(dc, cpu_addr);
4723
                        gen_helper_stdf(cpu_addr, r_const);
4724
                        tcg_temp_free_i32(r_const);
4725
                    }
4726
                    break;
4727
                default:
4728
                    goto illegal_insn;
4729
                }
4730
            } else if (xop > 0x33 && xop < 0x3f) {
4731
                save_state(dc, cpu_cond);
4732
                switch (xop) {
4733
#ifdef TARGET_SPARC64
4734
                case 0x34: /* V9 stfa */
4735
                    if (gen_trap_ifnofpu(dc, cpu_cond)) {
4736
                        goto jmp_insn;
4737
                    }
4738
                    gen_stf_asi(cpu_addr, insn, 4, rd);
4739
                    break;
4740
                case 0x36: /* V9 stqfa */
4741
                    {
4742
                        TCGv_i32 r_const;
4743

    
4744
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4745
                        if (gen_trap_ifnofpu(dc, cpu_cond)) {
4746
                            goto jmp_insn;
4747
                        }
4748
                        r_const = tcg_const_i32(7);
4749
                        gen_helper_check_align(cpu_addr, r_const);
4750
                        tcg_temp_free_i32(r_const);
4751
                        gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4752
                    }
4753
                    break;
4754
                case 0x37: /* V9 stdfa */
4755
                    if (gen_trap_ifnofpu(dc, cpu_cond)) {
4756
                        goto jmp_insn;
4757
                    }
4758
                    gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4759
                    break;
4760
                case 0x3c: /* V9 casa */
4761
                    gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4762
                    gen_movl_TN_reg(rd, cpu_val);
4763
                    break;
4764
                case 0x3e: /* V9 casxa */
4765
                    gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4766
                    gen_movl_TN_reg(rd, cpu_val);
4767
                    break;
4768
#else
4769
                case 0x34: /* stc */
4770
                case 0x35: /* stcsr */
4771
                case 0x36: /* stdcq */
4772
                case 0x37: /* stdc */
4773
                    goto ncp_insn;
4774
#endif
4775
                default:
4776
                    goto illegal_insn;
4777
                }
4778
            } else
4779
                goto illegal_insn;
4780
        }
4781
        break;
4782
    }
4783
    /* default case for non jump instructions */
4784
    if (dc->npc == DYNAMIC_PC) {
4785
        dc->pc = DYNAMIC_PC;
4786
        gen_op_next_insn();
4787
    } else if (dc->npc == JUMP_PC) {
4788
        /* we can do a static jump */
4789
        gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4790
        dc->is_br = 1;
4791
    } else {
4792
        dc->pc = dc->npc;
4793
        dc->npc = dc->npc + 4;
4794
    }
4795
 jmp_insn:
4796
    goto egress;
4797
 illegal_insn:
4798
    {
4799
        TCGv_i32 r_const;
4800

    
4801
        save_state(dc, cpu_cond);
4802
        r_const = tcg_const_i32(TT_ILL_INSN);
4803
        gen_helper_raise_exception(r_const);
4804
        tcg_temp_free_i32(r_const);
4805
        dc->is_br = 1;
4806
    }
4807
    goto egress;
4808
 unimp_flush:
4809
    {
4810
        TCGv_i32 r_const;
4811

    
4812
        save_state(dc, cpu_cond);
4813
        r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4814
        gen_helper_raise_exception(r_const);
4815
        tcg_temp_free_i32(r_const);
4816
        dc->is_br = 1;
4817
    }
4818
    goto egress;
4819
#if !defined(CONFIG_USER_ONLY)
4820
 priv_insn:
4821
    {
4822
        TCGv_i32 r_const;
4823

    
4824
        save_state(dc, cpu_cond);
4825
        r_const = tcg_const_i32(TT_PRIV_INSN);
4826
        gen_helper_raise_exception(r_const);
4827
        tcg_temp_free_i32(r_const);
4828
        dc->is_br = 1;
4829
    }
4830
    goto egress;
4831
#endif
4832
 nfpu_insn:
4833
    save_state(dc, cpu_cond);
4834
    gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4835
    dc->is_br = 1;
4836
    goto egress;
4837
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4838
 nfq_insn:
4839
    save_state(dc, cpu_cond);
4840
    gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4841
    dc->is_br = 1;
4842
    goto egress;
4843
#endif
4844
#ifndef TARGET_SPARC64
4845
 ncp_insn:
4846
    {
4847
        TCGv r_const;
4848

    
4849
        save_state(dc, cpu_cond);
4850
        r_const = tcg_const_i32(TT_NCP_INSN);
4851
        gen_helper_raise_exception(r_const);
4852
        tcg_temp_free(r_const);
4853
        dc->is_br = 1;
4854
    }
4855
    goto egress;
4856
#endif
4857
 egress:
4858
    tcg_temp_free(cpu_tmp1);
4859
    tcg_temp_free(cpu_tmp2);
4860
}
4861

    
4862
static inline void gen_intermediate_code_internal(TranslationBlock * tb,
4863
                                                  int spc, CPUSPARCState *env)
4864
{
4865
    target_ulong pc_start, last_pc;
4866
    uint16_t *gen_opc_end;
4867
    DisasContext dc1, *dc = &dc1;
4868
    CPUBreakpoint *bp;
4869
    int j, lj = -1;
4870
    int num_insns;
4871
    int max_insns;
4872

    
4873
    memset(dc, 0, sizeof(DisasContext));
4874
    dc->tb = tb;
4875
    pc_start = tb->pc;
4876
    dc->pc = pc_start;
4877
    last_pc = dc->pc;
4878
    dc->npc = (target_ulong) tb->cs_base;
4879
    dc->cc_op = CC_OP_DYNAMIC;
4880
    dc->mem_idx = cpu_mmu_index(env);
4881
    dc->def = env->def;