root / tcg / sparc / tcg-target.c @ f843e528
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
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"%g0",
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"%g1",
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"%g2",
|
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"%g3",
|
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"%g4",
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"%g5",
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"%g6",
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"%g7",
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"%o0",
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"%o1",
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"%o2",
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"%o3",
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"%o4",
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"%o5",
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"%o6",
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"%o7",
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"%l0",
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"%l1",
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"%l2",
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"%l3",
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"%l4",
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"%l5",
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"%l6",
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"%l7",
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"%i0",
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"%i1",
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"%i2",
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"%i3",
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"%i4",
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"%i5",
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"%i6",
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"%i7",
|
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}; |
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#endif
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|
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static const int tcg_target_reg_alloc_order[] = { |
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TCG_REG_L0, |
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TCG_REG_L1, |
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TCG_REG_L2, |
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TCG_REG_L3, |
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TCG_REG_L4, |
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TCG_REG_L5, |
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TCG_REG_L6, |
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TCG_REG_L7, |
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TCG_REG_I0, |
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TCG_REG_I1, |
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TCG_REG_I2, |
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TCG_REG_I3, |
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TCG_REG_I4, |
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}; |
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|
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static const int tcg_target_call_iarg_regs[6] = { |
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TCG_REG_O0, |
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TCG_REG_O1, |
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TCG_REG_O2, |
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TCG_REG_O3, |
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TCG_REG_O4, |
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TCG_REG_O5, |
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}; |
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|
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static const int tcg_target_call_oarg_regs[2] = { |
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TCG_REG_O0, |
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TCG_REG_O1, |
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}; |
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|
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static inline int check_fit_tl(tcg_target_long val, unsigned int bits) |
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{
|
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return (val << ((sizeof(tcg_target_long) * 8 - bits)) |
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>> (sizeof(tcg_target_long) * 8 - bits)) == val; |
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} |
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|
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static inline int check_fit_i32(uint32_t val, unsigned int bits) |
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{
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return ((val << (32 - bits)) >> (32 - bits)) == val; |
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} |
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|
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static void patch_reloc(uint8_t *code_ptr, int type, |
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tcg_target_long value, tcg_target_long addend) |
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{
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value += addend; |
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switch (type) {
|
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case R_SPARC_32:
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if (value != (uint32_t)value)
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tcg_abort(); |
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*(uint32_t *)code_ptr = value; |
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break;
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case R_SPARC_WDISP22:
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value -= (long)code_ptr;
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value >>= 2;
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if (!check_fit_tl(value, 22)) |
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tcg_abort(); |
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*(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
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break;
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default:
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tcg_abort(); |
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} |
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} |
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|
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/* maximum number of register used for input function arguments */
|
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static inline int tcg_target_get_call_iarg_regs_count(int flags) |
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{
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return 6; |
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} |
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|
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/* parse target specific constraints */
|
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static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
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{
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const char *ct_str; |
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|
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ct_str = *pct_str; |
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switch (ct_str[0]) { |
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case 'r': |
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case 'L': /* qemu_ld/st constraint */ |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
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// Helper args
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2); |
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break;
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case 'I': |
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ct->ct |= TCG_CT_CONST_S11; |
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break;
|
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case 'J': |
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ct->ct |= TCG_CT_CONST_S13; |
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break;
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default:
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return -1; |
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} |
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ct_str++; |
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*pct_str = ct_str; |
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return 0; |
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} |
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|
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/* test if a constant matches the constraint */
|
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static inline int tcg_target_const_match(tcg_target_long val, |
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const TCGArgConstraint *arg_ct)
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{
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int ct;
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|
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ct = arg_ct->ct; |
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if (ct & TCG_CT_CONST)
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return 1; |
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else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) |
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return 1; |
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else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) |
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return 1; |
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else
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return 0; |
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} |
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|
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#define INSN_OP(x) ((x) << 30) |
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#define INSN_OP2(x) ((x) << 22) |
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#define INSN_OP3(x) ((x) << 19) |
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#define INSN_OPF(x) ((x) << 5) |
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#define INSN_RD(x) ((x) << 25) |
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#define INSN_RS1(x) ((x) << 14) |
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#define INSN_RS2(x) (x)
|
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#define INSN_ASI(x) ((x) << 5) |
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|
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#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) |
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#define INSN_OFF22(x) (((x) >> 2) & 0x3fffff) |
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|
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#define INSN_COND(x, a) (((x) << 25) | ((a) << 29)) |
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#define COND_N 0x0 |
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#define COND_E 0x1 |
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#define COND_LE 0x2 |
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#define COND_L 0x3 |
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#define COND_LEU 0x4 |
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#define COND_CS 0x5 |
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#define COND_NEG 0x6 |
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#define COND_VS 0x7 |
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#define COND_A 0x8 |
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#define COND_NE 0x9 |
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#define COND_G 0xa |
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#define COND_GE 0xb |
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#define COND_GU 0xc |
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#define COND_CC 0xd |
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#define COND_POS 0xe |
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#define COND_VC 0xf |
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#define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2)) |
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|
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#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) |
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#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) |
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#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) |
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#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) |
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#define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) |
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#define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) |
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#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) |
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#define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10)) |
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#define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c)) |
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#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) |
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#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) |
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#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) |
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#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) |
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#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) |
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#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) |
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|
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#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) |
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#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) |
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#define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) |
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|
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#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) |
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#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) |
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#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) |
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|
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#define WRY (INSN_OP(2) | INSN_OP3(0x30)) |
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#define JMPL (INSN_OP(2) | INSN_OP3(0x38)) |
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#define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) |
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#define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) |
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#define SETHI (INSN_OP(0) | INSN_OP2(0x4)) |
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#define CALL INSN_OP(1) |
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#define LDUB (INSN_OP(3) | INSN_OP3(0x01)) |
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#define LDSB (INSN_OP(3) | INSN_OP3(0x09)) |
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#define LDUH (INSN_OP(3) | INSN_OP3(0x02)) |
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#define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) |
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#define LDUW (INSN_OP(3) | INSN_OP3(0x00)) |
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#define LDSW (INSN_OP(3) | INSN_OP3(0x08)) |
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#define LDX (INSN_OP(3) | INSN_OP3(0x0b)) |
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#define STB (INSN_OP(3) | INSN_OP3(0x05)) |
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#define STH (INSN_OP(3) | INSN_OP3(0x06)) |
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#define STW (INSN_OP(3) | INSN_OP3(0x04)) |
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#define STX (INSN_OP(3) | INSN_OP3(0x0e)) |
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#define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) |
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#define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) |
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#define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) |
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#define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) |
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#define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) |
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#define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) |
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#define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) |
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#define STBA (INSN_OP(3) | INSN_OP3(0x15)) |
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#define STHA (INSN_OP(3) | INSN_OP3(0x16)) |
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#define STWA (INSN_OP(3) | INSN_OP3(0x14)) |
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#define STXA (INSN_OP(3) | INSN_OP3(0x1e)) |
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|
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#ifndef ASI_PRIMARY_LITTLE
|
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#define ASI_PRIMARY_LITTLE 0x88 |
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#endif
|
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|
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static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2, |
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int op)
|
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{
|
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tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
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INSN_RS2(rs2)); |
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} |
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|
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static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1, |
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uint32_t offset, int op)
|
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{
|
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tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
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INSN_IMM13(offset)); |
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} |
| 279 |
|
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static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
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{
|
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tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); |
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} |
| 284 |
|
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static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg) |
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{
|
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tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); |
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} |
| 289 |
|
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static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg) |
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{
|
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tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); |
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} |
| 294 |
|
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static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg) |
| 296 |
{
|
| 297 |
if (check_fit_tl(arg, 12)) |
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tcg_out_movi_imm13(s, ret, arg); |
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else {
|
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tcg_out_sethi(s, ret, arg); |
| 301 |
if (arg & 0x3ff) |
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tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
|
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} |
| 304 |
} |
| 305 |
|
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static inline void tcg_out_movi(TCGContext *s, TCGType type, |
| 307 |
int ret, tcg_target_long arg)
|
| 308 |
{
|
| 309 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
| 310 |
if (!check_fit_tl(arg, 32) && (arg & ~0xffffffffULL) != 0) { |
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tcg_out_movi_imm32(s, TCG_REG_I4, arg >> 32);
|
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tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
|
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tcg_out_movi_imm32(s, ret, arg); |
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tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR); |
| 315 |
} else if (check_fit_tl(arg, 12)) |
| 316 |
tcg_out_movi_imm13(s, ret, arg); |
| 317 |
else {
|
| 318 |
tcg_out_sethi(s, ret, arg); |
| 319 |
if (arg & 0x3ff) |
| 320 |
tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
|
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} |
| 322 |
#else
|
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tcg_out_movi_imm32(s, ret, arg); |
| 324 |
#endif
|
| 325 |
} |
| 326 |
|
| 327 |
static inline void tcg_out_ld_raw(TCGContext *s, int ret, |
| 328 |
tcg_target_long arg) |
| 329 |
{
|
| 330 |
tcg_out_sethi(s, ret, arg); |
| 331 |
tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | |
| 332 |
INSN_IMM13(arg & 0x3ff));
|
| 333 |
} |
| 334 |
|
| 335 |
static inline void tcg_out_ld_ptr(TCGContext *s, int ret, |
| 336 |
tcg_target_long arg) |
| 337 |
{
|
| 338 |
if (!check_fit_tl(arg, 10)) |
| 339 |
tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
|
| 340 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
| 341 |
tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) | |
| 342 |
INSN_IMM13(arg & 0x3ff));
|
| 343 |
#else
|
| 344 |
tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | |
| 345 |
INSN_IMM13(arg & 0x3ff));
|
| 346 |
#endif
|
| 347 |
} |
| 348 |
|
| 349 |
static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op) |
| 350 |
{
|
| 351 |
if (check_fit_tl(offset, 13)) |
| 352 |
tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | |
| 353 |
INSN_IMM13(offset)); |
| 354 |
else {
|
| 355 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset); |
| 356 |
tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) | |
| 357 |
INSN_RS2(addr)); |
| 358 |
} |
| 359 |
} |
| 360 |
|
| 361 |
static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr, |
| 362 |
int offset, int op, int asi) |
| 363 |
{
|
| 364 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset); |
| 365 |
tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) | |
| 366 |
INSN_ASI(asi) | INSN_RS2(addr)); |
| 367 |
} |
| 368 |
|
| 369 |
static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, |
| 370 |
int arg1, tcg_target_long arg2)
|
| 371 |
{
|
| 372 |
if (type == TCG_TYPE_I32)
|
| 373 |
tcg_out_ldst(s, ret, arg1, arg2, LDUW); |
| 374 |
else
|
| 375 |
tcg_out_ldst(s, ret, arg1, arg2, LDX); |
| 376 |
} |
| 377 |
|
| 378 |
static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, |
| 379 |
int arg1, tcg_target_long arg2)
|
| 380 |
{
|
| 381 |
if (type == TCG_TYPE_I32)
|
| 382 |
tcg_out_ldst(s, arg, arg1, arg2, STW); |
| 383 |
else
|
| 384 |
tcg_out_ldst(s, arg, arg1, arg2, STX); |
| 385 |
} |
| 386 |
|
| 387 |
static inline void tcg_out_sety(TCGContext *s, tcg_target_long val) |
| 388 |
{
|
| 389 |
if (val == 0 || val == -1) |
| 390 |
tcg_out32(s, WRY | INSN_IMM13(val)); |
| 391 |
else
|
| 392 |
fprintf(stderr, "unimplemented sety %ld\n", (long)val); |
| 393 |
} |
| 394 |
|
| 395 |
static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
| 396 |
{
|
| 397 |
if (val != 0) { |
| 398 |
if (check_fit_tl(val, 13)) |
| 399 |
tcg_out_arithi(s, reg, reg, val, ARITH_ADD); |
| 400 |
else {
|
| 401 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val); |
| 402 |
tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD); |
| 403 |
} |
| 404 |
} |
| 405 |
} |
| 406 |
|
| 407 |
static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val) |
| 408 |
{
|
| 409 |
if (val != 0) { |
| 410 |
if (check_fit_tl(val, 13)) |
| 411 |
tcg_out_arithi(s, reg, reg, val, ARITH_AND); |
| 412 |
else {
|
| 413 |
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val); |
| 414 |
tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_AND); |
| 415 |
} |
| 416 |
} |
| 417 |
} |
| 418 |
|
| 419 |
static inline void tcg_out_nop(TCGContext *s) |
| 420 |
{
|
| 421 |
tcg_out_sethi(s, TCG_REG_G0, 0);
|
| 422 |
} |
| 423 |
|
| 424 |
static void tcg_out_branch(TCGContext *s, int opc, int label_index) |
| 425 |
{
|
| 426 |
int32_t val; |
| 427 |
TCGLabel *l = &s->labels[label_index]; |
| 428 |
|
| 429 |
if (l->has_value) {
|
| 430 |
val = l->u.value - (tcg_target_long)s->code_ptr; |
| 431 |
tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) |
| 432 |
| INSN_OFF22(l->u.value - (unsigned long)s->code_ptr))); |
| 433 |
} else {
|
| 434 |
tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
|
| 435 |
tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0)); |
| 436 |
} |
| 437 |
} |
| 438 |
|
| 439 |
static const uint8_t tcg_cond_to_bcond[10] = { |
| 440 |
[TCG_COND_EQ] = COND_E, |
| 441 |
[TCG_COND_NE] = COND_NE, |
| 442 |
[TCG_COND_LT] = COND_L, |
| 443 |
[TCG_COND_GE] = COND_GE, |
| 444 |
[TCG_COND_LE] = COND_LE, |
| 445 |
[TCG_COND_GT] = COND_G, |
| 446 |
[TCG_COND_LTU] = COND_CS, |
| 447 |
[TCG_COND_GEU] = COND_CC, |
| 448 |
[TCG_COND_LEU] = COND_LEU, |
| 449 |
[TCG_COND_GTU] = COND_GU, |
| 450 |
}; |
| 451 |
|
| 452 |
static void tcg_out_brcond(TCGContext *s, int cond, |
| 453 |
TCGArg arg1, TCGArg arg2, int const_arg2,
|
| 454 |
int label_index)
|
| 455 |
{
|
| 456 |
if (const_arg2 && arg2 == 0) |
| 457 |
/* orcc %g0, r, %g0 */
|
| 458 |
tcg_out_arith(s, TCG_REG_G0, TCG_REG_G0, arg1, ARITH_ORCC); |
| 459 |
else
|
| 460 |
/* subcc r1, r2, %g0 */
|
| 461 |
tcg_out_arith(s, TCG_REG_G0, arg1, arg2, ARITH_SUBCC); |
| 462 |
tcg_out_branch(s, tcg_cond_to_bcond[cond], label_index); |
| 463 |
tcg_out_nop(s); |
| 464 |
} |
| 465 |
|
| 466 |
/* Generate global QEMU prologue and epilogue code */
|
| 467 |
void tcg_target_qemu_prologue(TCGContext *s)
|
| 468 |
{
|
| 469 |
tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | |
| 470 |
INSN_IMM13(-TCG_TARGET_STACK_MINFRAME)); |
| 471 |
tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) | |
| 472 |
INSN_RS2(TCG_REG_G0)); |
| 473 |
tcg_out_nop(s); |
| 474 |
} |
| 475 |
|
| 476 |
#if defined(CONFIG_SOFTMMU)
|
| 477 |
|
| 478 |
#include "../../softmmu_defs.h" |
| 479 |
|
| 480 |
static const void * const qemu_ld_helpers[4] = { |
| 481 |
__ldb_mmu, |
| 482 |
__ldw_mmu, |
| 483 |
__ldl_mmu, |
| 484 |
__ldq_mmu, |
| 485 |
}; |
| 486 |
|
| 487 |
static const void * const qemu_st_helpers[4] = { |
| 488 |
__stb_mmu, |
| 489 |
__stw_mmu, |
| 490 |
__stl_mmu, |
| 491 |
__stq_mmu, |
| 492 |
}; |
| 493 |
#endif
|
| 494 |
|
| 495 |
#if TARGET_LONG_BITS == 32 |
| 496 |
#define TARGET_LD_OP LDUW
|
| 497 |
#else
|
| 498 |
#define TARGET_LD_OP LDX
|
| 499 |
#endif
|
| 500 |
|
| 501 |
#if TARGET_PHYS_ADDR_BITS == 32 |
| 502 |
#define TARGET_ADDEND_LD_OP LDUW
|
| 503 |
#else
|
| 504 |
#define TARGET_ADDEND_LD_OP LDX
|
| 505 |
#endif
|
| 506 |
|
| 507 |
#ifdef __arch64__
|
| 508 |
#define HOST_LD_OP LDX
|
| 509 |
#define HOST_ST_OP STX
|
| 510 |
#define HOST_SLL_OP SHIFT_SLLX
|
| 511 |
#define HOST_SRA_OP SHIFT_SRAX
|
| 512 |
#else
|
| 513 |
#define HOST_LD_OP LDUW
|
| 514 |
#define HOST_ST_OP STW
|
| 515 |
#define HOST_SLL_OP SHIFT_SLL
|
| 516 |
#define HOST_SRA_OP SHIFT_SRA
|
| 517 |
#endif
|
| 518 |
|
| 519 |
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
| 520 |
int opc)
|
| 521 |
{
|
| 522 |
int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
|
| 523 |
#if defined(CONFIG_SOFTMMU)
|
| 524 |
uint32_t *label1_ptr, *label2_ptr; |
| 525 |
#endif
|
| 526 |
|
| 527 |
data_reg = *args++; |
| 528 |
addr_reg = *args++; |
| 529 |
mem_index = *args; |
| 530 |
s_bits = opc & 3;
|
| 531 |
|
| 532 |
arg0 = TCG_REG_O0; |
| 533 |
arg1 = TCG_REG_O1; |
| 534 |
arg2 = TCG_REG_O2; |
| 535 |
|
| 536 |
#if defined(CONFIG_SOFTMMU)
|
| 537 |
/* srl addr_reg, x, arg1 */
|
| 538 |
tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, |
| 539 |
SHIFT_SRL); |
| 540 |
/* and addr_reg, x, arg0 */
|
| 541 |
tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1), |
| 542 |
ARITH_AND); |
| 543 |
|
| 544 |
/* and arg1, x, arg1 */
|
| 545 |
tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
| 546 |
|
| 547 |
/* add arg1, x, arg1 */
|
| 548 |
tcg_out_addi(s, arg1, offsetof(CPUState, |
| 549 |
tlb_table[mem_index][0].addr_read));
|
| 550 |
|
| 551 |
/* add env, arg1, arg1 */
|
| 552 |
tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD); |
| 553 |
|
| 554 |
/* ld [arg1], arg2 */
|
| 555 |
tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) | |
| 556 |
INSN_RS2(TCG_REG_G0)); |
| 557 |
|
| 558 |
/* subcc arg0, arg2, %g0 */
|
| 559 |
tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC); |
| 560 |
|
| 561 |
/* will become:
|
| 562 |
be label1 */
|
| 563 |
label1_ptr = (uint32_t *)s->code_ptr; |
| 564 |
tcg_out32(s, 0);
|
| 565 |
|
| 566 |
/* mov (delay slot) */
|
| 567 |
tcg_out_mov(s, arg0, addr_reg); |
| 568 |
|
| 569 |
/* mov */
|
| 570 |
tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index); |
| 571 |
|
| 572 |
/* XXX: move that code at the end of the TB */
|
| 573 |
/* qemu_ld_helper[s_bits](arg0, arg1) */
|
| 574 |
tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits] |
| 575 |
- (tcg_target_ulong)s->code_ptr) >> 2)
|
| 576 |
& 0x3fffffff));
|
| 577 |
/* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
| 578 |
global registers */
|
| 579 |
// delay slot
|
| 580 |
tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
| 581 |
TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
| 582 |
sizeof(long), HOST_ST_OP); |
| 583 |
tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
| 584 |
TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
| 585 |
sizeof(long), HOST_LD_OP); |
| 586 |
|
| 587 |
/* data_reg = sign_extend(arg0) */
|
| 588 |
switch(opc) {
|
| 589 |
case 0 | 4: |
| 590 |
/* sll arg0, 24/56, data_reg */
|
| 591 |
tcg_out_arithi(s, data_reg, arg0, (int)sizeof(tcg_target_long) * 8 - 8, |
| 592 |
HOST_SLL_OP); |
| 593 |
/* sra data_reg, 24/56, data_reg */
|
| 594 |
tcg_out_arithi(s, data_reg, data_reg, |
| 595 |
(int)sizeof(tcg_target_long) * 8 - 8, HOST_SRA_OP); |
| 596 |
break;
|
| 597 |
case 1 | 4: |
| 598 |
/* sll arg0, 16/48, data_reg */
|
| 599 |
tcg_out_arithi(s, data_reg, arg0, |
| 600 |
(int)sizeof(tcg_target_long) * 8 - 16, HOST_SLL_OP); |
| 601 |
/* sra data_reg, 16/48, data_reg */
|
| 602 |
tcg_out_arithi(s, data_reg, data_reg, |
| 603 |
(int)sizeof(tcg_target_long) * 8 - 16, HOST_SRA_OP); |
| 604 |
break;
|
| 605 |
case 2 | 4: |
| 606 |
/* sll arg0, 32, data_reg */
|
| 607 |
tcg_out_arithi(s, data_reg, arg0, 32, HOST_SLL_OP);
|
| 608 |
/* sra data_reg, 32, data_reg */
|
| 609 |
tcg_out_arithi(s, data_reg, data_reg, 32, HOST_SRA_OP);
|
| 610 |
break;
|
| 611 |
case 0: |
| 612 |
case 1: |
| 613 |
case 2: |
| 614 |
case 3: |
| 615 |
default:
|
| 616 |
/* mov */
|
| 617 |
tcg_out_mov(s, data_reg, arg0); |
| 618 |
break;
|
| 619 |
} |
| 620 |
|
| 621 |
/* will become:
|
| 622 |
ba label2 */
|
| 623 |
label2_ptr = (uint32_t *)s->code_ptr; |
| 624 |
tcg_out32(s, 0);
|
| 625 |
|
| 626 |
/* nop (delay slot */
|
| 627 |
tcg_out_nop(s); |
| 628 |
|
| 629 |
/* label1: */
|
| 630 |
*label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) | |
| 631 |
INSN_OFF22((unsigned long)s->code_ptr - |
| 632 |
(unsigned long)label1_ptr)); |
| 633 |
|
| 634 |
/* ld [arg1 + x], arg1 */
|
| 635 |
tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) - |
| 636 |
offsetof(CPUTLBEntry, addr_read), TARGET_ADDEND_LD_OP); |
| 637 |
|
| 638 |
#if TARGET_LONG_BITS == 32 |
| 639 |
/* and addr_reg, x, arg0 */
|
| 640 |
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
|
| 641 |
tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND); |
| 642 |
/* add arg0, arg1, arg0 */
|
| 643 |
tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD); |
| 644 |
#else
|
| 645 |
/* add addr_reg, arg1, arg0 */
|
| 646 |
tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD); |
| 647 |
#endif
|
| 648 |
|
| 649 |
#else
|
| 650 |
arg0 = addr_reg; |
| 651 |
#endif
|
| 652 |
|
| 653 |
switch(opc) {
|
| 654 |
case 0: |
| 655 |
/* ldub [arg0], data_reg */
|
| 656 |
tcg_out_ldst(s, data_reg, arg0, 0, LDUB);
|
| 657 |
break;
|
| 658 |
case 0 | 4: |
| 659 |
/* ldsb [arg0], data_reg */
|
| 660 |
tcg_out_ldst(s, data_reg, arg0, 0, LDSB);
|
| 661 |
break;
|
| 662 |
case 1: |
| 663 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 664 |
/* lduh [arg0], data_reg */
|
| 665 |
tcg_out_ldst(s, data_reg, arg0, 0, LDUH);
|
| 666 |
#else
|
| 667 |
/* lduha [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
| 668 |
tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUHA, ASI_PRIMARY_LITTLE);
|
| 669 |
#endif
|
| 670 |
break;
|
| 671 |
case 1 | 4: |
| 672 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 673 |
/* ldsh [arg0], data_reg */
|
| 674 |
tcg_out_ldst(s, data_reg, arg0, 0, LDSH);
|
| 675 |
#else
|
| 676 |
/* ldsha [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
| 677 |
tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSHA, ASI_PRIMARY_LITTLE);
|
| 678 |
#endif
|
| 679 |
break;
|
| 680 |
case 2: |
| 681 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 682 |
/* lduw [arg0], data_reg */
|
| 683 |
tcg_out_ldst(s, data_reg, arg0, 0, LDUW);
|
| 684 |
#else
|
| 685 |
/* lduwa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
| 686 |
tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUWA, ASI_PRIMARY_LITTLE);
|
| 687 |
#endif
|
| 688 |
break;
|
| 689 |
case 2 | 4: |
| 690 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 691 |
/* ldsw [arg0], data_reg */
|
| 692 |
tcg_out_ldst(s, data_reg, arg0, 0, LDSW);
|
| 693 |
#else
|
| 694 |
/* ldswa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
| 695 |
tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSWA, ASI_PRIMARY_LITTLE);
|
| 696 |
#endif
|
| 697 |
break;
|
| 698 |
case 3: |
| 699 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 700 |
/* ldx [arg0], data_reg */
|
| 701 |
tcg_out_ldst(s, data_reg, arg0, 0, LDX);
|
| 702 |
#else
|
| 703 |
/* ldxa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
| 704 |
tcg_out_ldst_asi(s, data_reg, arg0, 0, LDXA, ASI_PRIMARY_LITTLE);
|
| 705 |
#endif
|
| 706 |
break;
|
| 707 |
default:
|
| 708 |
tcg_abort(); |
| 709 |
} |
| 710 |
|
| 711 |
#if defined(CONFIG_SOFTMMU)
|
| 712 |
/* label2: */
|
| 713 |
*label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) | |
| 714 |
INSN_OFF22((unsigned long)s->code_ptr - |
| 715 |
(unsigned long)label2_ptr)); |
| 716 |
#endif
|
| 717 |
} |
| 718 |
|
| 719 |
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
| 720 |
int opc)
|
| 721 |
{
|
| 722 |
int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
|
| 723 |
#if defined(CONFIG_SOFTMMU)
|
| 724 |
uint32_t *label1_ptr, *label2_ptr; |
| 725 |
#endif
|
| 726 |
|
| 727 |
data_reg = *args++; |
| 728 |
addr_reg = *args++; |
| 729 |
mem_index = *args; |
| 730 |
|
| 731 |
s_bits = opc; |
| 732 |
|
| 733 |
arg0 = TCG_REG_O0; |
| 734 |
arg1 = TCG_REG_O1; |
| 735 |
arg2 = TCG_REG_O2; |
| 736 |
|
| 737 |
#if defined(CONFIG_SOFTMMU)
|
| 738 |
/* srl addr_reg, x, arg1 */
|
| 739 |
tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, |
| 740 |
SHIFT_SRL); |
| 741 |
|
| 742 |
/* and addr_reg, x, arg0 */
|
| 743 |
tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1), |
| 744 |
ARITH_AND); |
| 745 |
|
| 746 |
/* and arg1, x, arg1 */
|
| 747 |
tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
| 748 |
|
| 749 |
/* add arg1, x, arg1 */
|
| 750 |
tcg_out_addi(s, arg1, offsetof(CPUState, |
| 751 |
tlb_table[mem_index][0].addr_write));
|
| 752 |
|
| 753 |
/* add env, arg1, arg1 */
|
| 754 |
tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD); |
| 755 |
|
| 756 |
/* ld [arg1], arg2 */
|
| 757 |
tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) | |
| 758 |
INSN_RS2(TCG_REG_G0)); |
| 759 |
|
| 760 |
/* subcc arg0, arg2, %g0 */
|
| 761 |
tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC); |
| 762 |
|
| 763 |
/* will become:
|
| 764 |
be label1 */
|
| 765 |
label1_ptr = (uint32_t *)s->code_ptr; |
| 766 |
tcg_out32(s, 0);
|
| 767 |
|
| 768 |
/* mov (delay slot) */
|
| 769 |
tcg_out_mov(s, arg0, addr_reg); |
| 770 |
|
| 771 |
/* mov */
|
| 772 |
tcg_out_mov(s, arg1, data_reg); |
| 773 |
|
| 774 |
/* mov */
|
| 775 |
tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index); |
| 776 |
|
| 777 |
/* XXX: move that code at the end of the TB */
|
| 778 |
/* qemu_st_helper[s_bits](arg0, arg1, arg2) */
|
| 779 |
tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits] |
| 780 |
- (tcg_target_ulong)s->code_ptr) >> 2)
|
| 781 |
& 0x3fffffff));
|
| 782 |
/* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
| 783 |
global registers */
|
| 784 |
// delay slot
|
| 785 |
tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
| 786 |
TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
| 787 |
sizeof(long), HOST_ST_OP); |
| 788 |
tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
| 789 |
TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
| 790 |
sizeof(long), HOST_LD_OP); |
| 791 |
|
| 792 |
/* will become:
|
| 793 |
ba label2 */
|
| 794 |
label2_ptr = (uint32_t *)s->code_ptr; |
| 795 |
tcg_out32(s, 0);
|
| 796 |
|
| 797 |
/* nop (delay slot) */
|
| 798 |
tcg_out_nop(s); |
| 799 |
|
| 800 |
/* label1: */
|
| 801 |
*label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) | |
| 802 |
INSN_OFF22((unsigned long)s->code_ptr - |
| 803 |
(unsigned long)label1_ptr)); |
| 804 |
|
| 805 |
/* ld [arg1 + x], arg1 */
|
| 806 |
tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) - |
| 807 |
offsetof(CPUTLBEntry, addr_write), TARGET_ADDEND_LD_OP); |
| 808 |
|
| 809 |
#if TARGET_LONG_BITS == 32 |
| 810 |
/* and addr_reg, x, arg0 */
|
| 811 |
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
|
| 812 |
tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND); |
| 813 |
/* add arg0, arg1, arg0 */
|
| 814 |
tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD); |
| 815 |
#else
|
| 816 |
/* add addr_reg, arg1, arg0 */
|
| 817 |
tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD); |
| 818 |
#endif
|
| 819 |
|
| 820 |
#else
|
| 821 |
arg0 = addr_reg; |
| 822 |
#endif
|
| 823 |
|
| 824 |
switch(opc) {
|
| 825 |
case 0: |
| 826 |
/* stb data_reg, [arg0] */
|
| 827 |
tcg_out_ldst(s, data_reg, arg0, 0, STB);
|
| 828 |
break;
|
| 829 |
case 1: |
| 830 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 831 |
/* sth data_reg, [arg0] */
|
| 832 |
tcg_out_ldst(s, data_reg, arg0, 0, STH);
|
| 833 |
#else
|
| 834 |
/* stha data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
| 835 |
tcg_out_ldst_asi(s, data_reg, arg0, 0, STHA, ASI_PRIMARY_LITTLE);
|
| 836 |
#endif
|
| 837 |
break;
|
| 838 |
case 2: |
| 839 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 840 |
/* stw data_reg, [arg0] */
|
| 841 |
tcg_out_ldst(s, data_reg, arg0, 0, STW);
|
| 842 |
#else
|
| 843 |
/* stwa data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
| 844 |
tcg_out_ldst_asi(s, data_reg, arg0, 0, STWA, ASI_PRIMARY_LITTLE);
|
| 845 |
#endif
|
| 846 |
break;
|
| 847 |
case 3: |
| 848 |
#ifdef TARGET_WORDS_BIGENDIAN
|
| 849 |
/* stx data_reg, [arg0] */
|
| 850 |
tcg_out_ldst(s, data_reg, arg0, 0, STX);
|
| 851 |
#else
|
| 852 |
/* stxa data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
| 853 |
tcg_out_ldst_asi(s, data_reg, arg0, 0, STXA, ASI_PRIMARY_LITTLE);
|
| 854 |
#endif
|
| 855 |
break;
|
| 856 |
default:
|
| 857 |
tcg_abort(); |
| 858 |
} |
| 859 |
|
| 860 |
#if defined(CONFIG_SOFTMMU)
|
| 861 |
/* label2: */
|
| 862 |
*label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) | |
| 863 |
INSN_OFF22((unsigned long)s->code_ptr - |
| 864 |
(unsigned long)label2_ptr)); |
| 865 |
#endif
|
| 866 |
} |
| 867 |
|
| 868 |
static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, |
| 869 |
const int *const_args) |
| 870 |
{
|
| 871 |
int c;
|
| 872 |
|
| 873 |
switch (opc) {
|
| 874 |
case INDEX_op_exit_tb:
|
| 875 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
|
| 876 |
tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) | |
| 877 |
INSN_IMM13(8));
|
| 878 |
tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) | |
| 879 |
INSN_RS2(TCG_REG_G0)); |
| 880 |
break;
|
| 881 |
case INDEX_op_goto_tb:
|
| 882 |
if (s->tb_jmp_offset) {
|
| 883 |
/* direct jump method */
|
| 884 |
tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000); |
| 885 |
tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) | |
| 886 |
INSN_IMM13((args[0] & 0x1fff))); |
| 887 |
s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
| 888 |
} else {
|
| 889 |
/* indirect jump method */
|
| 890 |
tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
|
| 891 |
tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) | |
| 892 |
INSN_RS2(TCG_REG_G0)); |
| 893 |
} |
| 894 |
tcg_out_nop(s); |
| 895 |
s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
| 896 |
break;
|
| 897 |
case INDEX_op_call:
|
| 898 |
if (const_args[0]) |
| 899 |
tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
|
| 900 |
- (tcg_target_ulong)s->code_ptr) >> 2)
|
| 901 |
& 0x3fffffff));
|
| 902 |
else {
|
| 903 |
tcg_out_ld_ptr(s, TCG_REG_I5, |
| 904 |
(tcg_target_long)(s->tb_next + args[0]));
|
| 905 |
tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) | |
| 906 |
INSN_RS2(TCG_REG_G0)); |
| 907 |
} |
| 908 |
/* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
| 909 |
global registers */
|
| 910 |
// delay slot
|
| 911 |
tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
| 912 |
TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
| 913 |
sizeof(long), HOST_ST_OP); |
| 914 |
tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
| 915 |
TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
| 916 |
sizeof(long), HOST_LD_OP); |
| 917 |
break;
|
| 918 |
case INDEX_op_jmp:
|
| 919 |
case INDEX_op_br:
|
| 920 |
tcg_out_branch(s, COND_A, args[0]);
|
| 921 |
tcg_out_nop(s); |
| 922 |
break;
|
| 923 |
case INDEX_op_movi_i32:
|
| 924 |
tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); |
| 925 |
break;
|
| 926 |
|
| 927 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
| 928 |
#define OP_32_64(x) \
|
| 929 |
glue(glue(case INDEX_op_, x), _i32:) \
|
| 930 |
glue(glue(case INDEX_op_, x), _i64:)
|
| 931 |
#else
|
| 932 |
#define OP_32_64(x) \
|
| 933 |
glue(glue(case INDEX_op_, x), _i32:)
|
| 934 |
#endif
|
| 935 |
OP_32_64(ld8u); |
| 936 |
tcg_out_ldst(s, args[0], args[1], args[2], LDUB); |
| 937 |
break;
|
| 938 |
OP_32_64(ld8s); |
| 939 |
tcg_out_ldst(s, args[0], args[1], args[2], LDSB); |
| 940 |
break;
|
| 941 |
OP_32_64(ld16u); |
| 942 |
tcg_out_ldst(s, args[0], args[1], args[2], LDUH); |
| 943 |
break;
|
| 944 |
OP_32_64(ld16s); |
| 945 |
tcg_out_ldst(s, args[0], args[1], args[2], LDSH); |
| 946 |
break;
|
| 947 |
case INDEX_op_ld_i32:
|
| 948 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
| 949 |
case INDEX_op_ld32u_i64:
|
| 950 |
#endif
|
| 951 |
tcg_out_ldst(s, args[0], args[1], args[2], LDUW); |
| 952 |
break;
|
| 953 |
OP_32_64(st8); |
| 954 |
tcg_out_ldst(s, args[0], args[1], args[2], STB); |
| 955 |
break;
|
| 956 |
OP_32_64(st16); |
| 957 |
tcg_out_ldst(s, args[0], args[1], args[2], STH); |
| 958 |
break;
|
| 959 |
case INDEX_op_st_i32:
|
| 960 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
| 961 |
case INDEX_op_st32_i64:
|
| 962 |
#endif
|
| 963 |
tcg_out_ldst(s, args[0], args[1], args[2], STW); |
| 964 |
break;
|
| 965 |
OP_32_64(add); |
| 966 |
c = ARITH_ADD; |
| 967 |
goto gen_arith32;
|
| 968 |
OP_32_64(sub); |
| 969 |
c = ARITH_SUB; |
| 970 |
goto gen_arith32;
|
| 971 |
OP_32_64(and); |
| 972 |
c = ARITH_AND; |
| 973 |
goto gen_arith32;
|
| 974 |
OP_32_64(or); |
| 975 |
c = ARITH_OR; |
| 976 |
goto gen_arith32;
|
| 977 |
OP_32_64(xor); |
| 978 |
c = ARITH_XOR; |
| 979 |
goto gen_arith32;
|
| 980 |
case INDEX_op_shl_i32:
|
| 981 |
c = SHIFT_SLL; |
| 982 |
goto gen_arith32;
|
| 983 |
case INDEX_op_shr_i32:
|
| 984 |
c = SHIFT_SRL; |
| 985 |
goto gen_arith32;
|
| 986 |
case INDEX_op_sar_i32:
|
| 987 |
c = SHIFT_SRA; |
| 988 |
goto gen_arith32;
|
| 989 |
case INDEX_op_mul_i32:
|
| 990 |
c = ARITH_UMUL; |
| 991 |
goto gen_arith32;
|
| 992 |
case INDEX_op_div2_i32:
|
| 993 |
#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
|
| 994 |
c = ARITH_SDIVX; |
| 995 |
goto gen_arith32;
|
| 996 |
#else
|
| 997 |
tcg_out_sety(s, 0);
|
| 998 |
c = ARITH_SDIV; |
| 999 |
goto gen_arith32;
|
| 1000 |
#endif
|
| 1001 |
case INDEX_op_divu2_i32:
|
| 1002 |
#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
|
| 1003 |
c = ARITH_UDIVX; |
| 1004 |
goto gen_arith32;
|
| 1005 |
#else
|
| 1006 |
tcg_out_sety(s, 0);
|
| 1007 |
c = ARITH_UDIV; |
| 1008 |
goto gen_arith32;
|
| 1009 |
#endif
|
| 1010 |
|
| 1011 |
case INDEX_op_brcond_i32:
|
| 1012 |
tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
| 1013 |
args[3]);
|
| 1014 |
break;
|
| 1015 |
|
| 1016 |
case INDEX_op_qemu_ld8u:
|
| 1017 |
tcg_out_qemu_ld(s, args, 0);
|
| 1018 |
break;
|
| 1019 |
case INDEX_op_qemu_ld8s:
|
| 1020 |
tcg_out_qemu_ld(s, args, 0 | 4); |
| 1021 |
break;
|
| 1022 |
case INDEX_op_qemu_ld16u:
|
| 1023 |
tcg_out_qemu_ld(s, args, 1);
|
| 1024 |
break;
|
| 1025 |
case INDEX_op_qemu_ld16s:
|
| 1026 |
tcg_out_qemu_ld(s, args, 1 | 4); |
| 1027 |
break;
|
| 1028 |
case INDEX_op_qemu_ld32u:
|
| 1029 |
tcg_out_qemu_ld(s, args, 2);
|
| 1030 |
break;
|
| 1031 |
case INDEX_op_qemu_ld32s:
|
| 1032 |
tcg_out_qemu_ld(s, args, 2 | 4); |
| 1033 |
break;
|
| 1034 |
case INDEX_op_qemu_st8:
|
| 1035 |
tcg_out_qemu_st(s, args, 0);
|
| 1036 |
break;
|
| 1037 |
case INDEX_op_qemu_st16:
|
| 1038 |
tcg_out_qemu_st(s, args, 1);
|
| 1039 |
break;
|
| 1040 |
case INDEX_op_qemu_st32:
|
| 1041 |
tcg_out_qemu_st(s, args, 2);
|
| 1042 |
break;
|
| 1043 |
|
| 1044 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
| 1045 |
case INDEX_op_movi_i64:
|
| 1046 |
tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
| 1047 |
break;
|
| 1048 |
case INDEX_op_ld32s_i64:
|
| 1049 |
tcg_out_ldst(s, args[0], args[1], args[2], LDSW); |
| 1050 |
break;
|
| 1051 |
case INDEX_op_ld_i64:
|
| 1052 |
tcg_out_ldst(s, args[0], args[1], args[2], LDX); |
| 1053 |
break;
|
| 1054 |
case INDEX_op_st_i64:
|
| 1055 |
tcg_out_ldst(s, args[0], args[1], args[2], STX); |
| 1056 |
break;
|
| 1057 |
case INDEX_op_shl_i64:
|
| 1058 |
c = SHIFT_SLLX; |
| 1059 |
goto gen_arith32;
|
| 1060 |
case INDEX_op_shr_i64:
|
| 1061 |
c = SHIFT_SRLX; |
| 1062 |
goto gen_arith32;
|
| 1063 |
case INDEX_op_sar_i64:
|
| 1064 |
c = SHIFT_SRAX; |
| 1065 |
goto gen_arith32;
|
| 1066 |
case INDEX_op_mul_i64:
|
| 1067 |
c = ARITH_MULX; |
| 1068 |
goto gen_arith32;
|
| 1069 |
case INDEX_op_div2_i64:
|
| 1070 |
c = ARITH_SDIVX; |
| 1071 |
goto gen_arith32;
|
| 1072 |
case INDEX_op_divu2_i64:
|
| 1073 |
c = ARITH_UDIVX; |
| 1074 |
goto gen_arith32;
|
| 1075 |
|
| 1076 |
case INDEX_op_brcond_i64:
|
| 1077 |
tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
| 1078 |
args[3]);
|
| 1079 |
break;
|
| 1080 |
case INDEX_op_qemu_ld64:
|
| 1081 |
tcg_out_qemu_ld(s, args, 3);
|
| 1082 |
break;
|
| 1083 |
case INDEX_op_qemu_st64:
|
| 1084 |
tcg_out_qemu_st(s, args, 3);
|
| 1085 |
break;
|
| 1086 |
|
| 1087 |
#endif
|
| 1088 |
gen_arith32:
|
| 1089 |
if (const_args[2]) { |
| 1090 |
tcg_out_arithi(s, args[0], args[1], args[2], c); |
| 1091 |
} else {
|
| 1092 |
tcg_out_arith(s, args[0], args[1], args[2], c); |
| 1093 |
} |
| 1094 |
break;
|
| 1095 |
|
| 1096 |
default:
|
| 1097 |
fprintf(stderr, "unknown opcode 0x%x\n", opc);
|
| 1098 |
tcg_abort(); |
| 1099 |
} |
| 1100 |
} |
| 1101 |
|
| 1102 |
static const TCGTargetOpDef sparc_op_defs[] = { |
| 1103 |
{ INDEX_op_exit_tb, { } },
|
| 1104 |
{ INDEX_op_goto_tb, { } },
|
| 1105 |
{ INDEX_op_call, { "ri" } },
|
| 1106 |
{ INDEX_op_jmp, { "ri" } },
|
| 1107 |
{ INDEX_op_br, { } },
|
| 1108 |
|
| 1109 |
{ INDEX_op_mov_i32, { "r", "r" } },
|
| 1110 |
{ INDEX_op_movi_i32, { "r" } },
|
| 1111 |
{ INDEX_op_ld8u_i32, { "r", "r" } },
|
| 1112 |
{ INDEX_op_ld8s_i32, { "r", "r" } },
|
| 1113 |
{ INDEX_op_ld16u_i32, { "r", "r" } },
|
| 1114 |
{ INDEX_op_ld16s_i32, { "r", "r" } },
|
| 1115 |
{ INDEX_op_ld_i32, { "r", "r" } },
|
| 1116 |
{ INDEX_op_st8_i32, { "r", "r" } },
|
| 1117 |
{ INDEX_op_st16_i32, { "r", "r" } },
|
| 1118 |
{ INDEX_op_st_i32, { "r", "r" } },
|
| 1119 |
|
| 1120 |
{ INDEX_op_add_i32, { "r", "r", "rJ" } },
|
| 1121 |
{ INDEX_op_mul_i32, { "r", "r", "rJ" } },
|
| 1122 |
{ INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } },
|
| 1123 |
{ INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } },
|
| 1124 |
{ INDEX_op_sub_i32, { "r", "r", "rJ" } },
|
| 1125 |
{ INDEX_op_and_i32, { "r", "r", "rJ" } },
|
| 1126 |
{ INDEX_op_or_i32, { "r", "r", "rJ" } },
|
| 1127 |
{ INDEX_op_xor_i32, { "r", "r", "rJ" } },
|
| 1128 |
|
| 1129 |
{ INDEX_op_shl_i32, { "r", "r", "rJ" } },
|
| 1130 |
{ INDEX_op_shr_i32, { "r", "r", "rJ" } },
|
| 1131 |
{ INDEX_op_sar_i32, { "r", "r", "rJ" } },
|
| 1132 |
|
| 1133 |
{ INDEX_op_brcond_i32, { "r", "ri" } },
|
| 1134 |
|
| 1135 |
{ INDEX_op_qemu_ld8u, { "r", "L" } },
|
| 1136 |
{ INDEX_op_qemu_ld8s, { "r", "L" } },
|
| 1137 |
{ INDEX_op_qemu_ld16u, { "r", "L" } },
|
| 1138 |
{ INDEX_op_qemu_ld16s, { "r", "L" } },
|
| 1139 |
{ INDEX_op_qemu_ld32u, { "r", "L" } },
|
| 1140 |
{ INDEX_op_qemu_ld32s, { "r", "L" } },
|
| 1141 |
|
| 1142 |
{ INDEX_op_qemu_st8, { "L", "L" } },
|
| 1143 |
{ INDEX_op_qemu_st16, { "L", "L" } },
|
| 1144 |
{ INDEX_op_qemu_st32, { "L", "L" } },
|
| 1145 |
|
| 1146 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
| 1147 |
{ INDEX_op_mov_i64, { "r", "r" } },
|
| 1148 |
{ INDEX_op_movi_i64, { "r" } },
|
| 1149 |
{ INDEX_op_ld8u_i64, { "r", "r" } },
|
| 1150 |
{ INDEX_op_ld8s_i64, { "r", "r" } },
|
| 1151 |
{ INDEX_op_ld16u_i64, { "r", "r" } },
|
| 1152 |
{ INDEX_op_ld16s_i64, { "r", "r" } },
|
| 1153 |
{ INDEX_op_ld32u_i64, { "r", "r" } },
|
| 1154 |
{ INDEX_op_ld32s_i64, { "r", "r" } },
|
| 1155 |
{ INDEX_op_ld_i64, { "r", "r" } },
|
| 1156 |
{ INDEX_op_st8_i64, { "r", "r" } },
|
| 1157 |
{ INDEX_op_st16_i64, { "r", "r" } },
|
| 1158 |
{ INDEX_op_st32_i64, { "r", "r" } },
|
| 1159 |
{ INDEX_op_st_i64, { "r", "r" } },
|
| 1160 |
{ INDEX_op_qemu_ld64, { "L", "L" } },
|
| 1161 |
{ INDEX_op_qemu_st64, { "L", "L" } },
|
| 1162 |
|
| 1163 |
{ INDEX_op_add_i64, { "r", "r", "rJ" } },
|
| 1164 |
{ INDEX_op_mul_i64, { "r", "r", "rJ" } },
|
| 1165 |
{ INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } },
|
| 1166 |
{ INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } },
|
| 1167 |
{ INDEX_op_sub_i64, { "r", "r", "rJ" } },
|
| 1168 |
{ INDEX_op_and_i64, { "r", "r", "rJ" } },
|
| 1169 |
{ INDEX_op_or_i64, { "r", "r", "rJ" } },
|
| 1170 |
{ INDEX_op_xor_i64, { "r", "r", "rJ" } },
|
| 1171 |
|
| 1172 |
{ INDEX_op_shl_i64, { "r", "r", "rJ" } },
|
| 1173 |
{ INDEX_op_shr_i64, { "r", "r", "rJ" } },
|
| 1174 |
{ INDEX_op_sar_i64, { "r", "r", "rJ" } },
|
| 1175 |
|
| 1176 |
{ INDEX_op_brcond_i64, { "r", "ri" } },
|
| 1177 |
#endif
|
| 1178 |
{ -1 },
|
| 1179 |
}; |
| 1180 |
|
| 1181 |
void tcg_target_init(TCGContext *s)
|
| 1182 |
{
|
| 1183 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
| 1184 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
| 1185 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); |
| 1186 |
#endif
|
| 1187 |
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
| 1188 |
(1 << TCG_REG_G1) |
|
| 1189 |
(1 << TCG_REG_G2) |
|
| 1190 |
(1 << TCG_REG_G3) |
|
| 1191 |
(1 << TCG_REG_G4) |
|
| 1192 |
(1 << TCG_REG_G5) |
|
| 1193 |
(1 << TCG_REG_G6) |
|
| 1194 |
(1 << TCG_REG_G7) |
|
| 1195 |
(1 << TCG_REG_O0) |
|
| 1196 |
(1 << TCG_REG_O1) |
|
| 1197 |
(1 << TCG_REG_O2) |
|
| 1198 |
(1 << TCG_REG_O3) |
|
| 1199 |
(1 << TCG_REG_O4) |
|
| 1200 |
(1 << TCG_REG_O5) |
|
| 1201 |
(1 << TCG_REG_O7));
|
| 1202 |
|
| 1203 |
tcg_regset_clear(s->reserved_regs); |
| 1204 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); |
| 1205 |
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
| 1206 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
|
| 1207 |
#endif
|
| 1208 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
|
| 1209 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); |
| 1210 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); |
| 1211 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); |
| 1212 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7); |
| 1213 |
tcg_add_target_add_op_defs(sparc_op_defs); |
| 1214 |
} |