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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * ARM virtual CPU header
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3 | 5fafdf24 | ths | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 2c0262af | bellard | */
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19 | 2c0262af | bellard | #ifndef CPU_ARM_H
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20 | 2c0262af | bellard | #define CPU_ARM_H
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21 | 2c0262af | bellard | |
22 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
23 | 3cf1e035 | bellard | |
24 | 9042c0e2 | ths | #define ELF_MACHINE EM_ARM
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25 | 9042c0e2 | ths | |
26 | c2764719 | pbrook | #define CPUState struct CPUARMState |
27 | c2764719 | pbrook | |
28 | 9a78eead | Stefan Weil | #include "config.h" |
29 | 9a78eead | Stefan Weil | #include "qemu-common.h" |
30 | 2c0262af | bellard | #include "cpu-defs.h" |
31 | 2c0262af | bellard | |
32 | 53cd6637 | bellard | #include "softfloat.h" |
33 | 53cd6637 | bellard | |
34 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
35 | 1fddef4b | bellard | |
36 | b8a9e8f1 | bellard | #define EXCP_UDEF 1 /* undefined instruction */ |
37 | b8a9e8f1 | bellard | #define EXCP_SWI 2 /* software interrupt */ |
38 | b8a9e8f1 | bellard | #define EXCP_PREFETCH_ABORT 3 |
39 | b8a9e8f1 | bellard | #define EXCP_DATA_ABORT 4 |
40 | b5ff1b31 | bellard | #define EXCP_IRQ 5 |
41 | b5ff1b31 | bellard | #define EXCP_FIQ 6 |
42 | 06c949e6 | pbrook | #define EXCP_BKPT 7 |
43 | 9ee6e8bb | pbrook | #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ |
44 | fbb4a2e3 | pbrook | #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ |
45 | 426f5abc | Paul Brook | #define EXCP_STREX 10 |
46 | 9ee6e8bb | pbrook | |
47 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_RESET 1 |
48 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_NMI 2 |
49 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_HARD 3 |
50 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_MEM 4 |
51 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_BUS 5 |
52 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_USAGE 6 |
53 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_SVC 11 |
54 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_DEBUG 12 |
55 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_PENDSV 14 |
56 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_SYSTICK 15 |
57 | 2c0262af | bellard | |
58 | c1713132 | balrog | typedef void ARMWriteCPFunc(void *opaque, int cp_info, |
59 | c1713132 | balrog | int srcreg, int operand, uint32_t value); |
60 | c1713132 | balrog | typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, |
61 | c1713132 | balrog | int dstreg, int operand); |
62 | c1713132 | balrog | |
63 | f93eb9ff | balrog | struct arm_boot_info;
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64 | f93eb9ff | balrog | |
65 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 2 |
66 | 6ebbf390 | j_mayer | |
67 | b7bcbe95 | bellard | /* We currently assume float and double are IEEE single and double
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68 | b7bcbe95 | bellard | precision respectively.
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69 | b7bcbe95 | bellard | Doing runtime conversions is tricky because VFP registers may contain
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70 | b7bcbe95 | bellard | integer values (eg. as the result of a FTOSI instruction).
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71 | 8e96005d | bellard | s<2n> maps to the least significant half of d<n>
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72 | 8e96005d | bellard | s<2n+1> maps to the most significant half of d<n>
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73 | 8e96005d | bellard | */
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74 | b7bcbe95 | bellard | |
75 | 2c0262af | bellard | typedef struct CPUARMState { |
76 | b5ff1b31 | bellard | /* Regs for current mode. */
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77 | 2c0262af | bellard | uint32_t regs[16];
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78 | b5ff1b31 | bellard | /* Frequently accessed CPSR bits are stored separately for efficiently.
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79 | d37aca66 | pbrook | This contains all the other bits. Use cpsr_{read,write} to access
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80 | b5ff1b31 | bellard | the whole CPSR. */
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81 | b5ff1b31 | bellard | uint32_t uncached_cpsr; |
82 | b5ff1b31 | bellard | uint32_t spsr; |
83 | b5ff1b31 | bellard | |
84 | b5ff1b31 | bellard | /* Banked registers. */
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85 | b5ff1b31 | bellard | uint32_t banked_spsr[6];
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86 | b5ff1b31 | bellard | uint32_t banked_r13[6];
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87 | b5ff1b31 | bellard | uint32_t banked_r14[6];
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88 | 3b46e624 | ths | |
89 | b5ff1b31 | bellard | /* These hold r8-r12. */
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90 | b5ff1b31 | bellard | uint32_t usr_regs[5];
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91 | b5ff1b31 | bellard | uint32_t fiq_regs[5];
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92 | 3b46e624 | ths | |
93 | 2c0262af | bellard | /* cpsr flag cache for faster execution */
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94 | 2c0262af | bellard | uint32_t CF; /* 0 or 1 */
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95 | 2c0262af | bellard | uint32_t VF; /* V is the bit 31. All other bits are undefined */
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96 | 6fbe23d5 | pbrook | uint32_t NF; /* N is bit 31. All other bits are undefined. */
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97 | 6fbe23d5 | pbrook | uint32_t ZF; /* Z set if zero. */
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98 | 99c475ab | bellard | uint32_t QF; /* 0 or 1 */
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99 | 9ee6e8bb | pbrook | uint32_t GE; /* cpsr[19:16] */
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100 | b26eefb6 | pbrook | uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
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101 | 9ee6e8bb | pbrook | uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
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102 | 2c0262af | bellard | |
103 | b5ff1b31 | bellard | /* System control coprocessor (cp15) */
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104 | b5ff1b31 | bellard | struct {
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105 | 40f137e1 | pbrook | uint32_t c0_cpuid; |
106 | c1713132 | balrog | uint32_t c0_cachetype; |
107 | a49ea279 | pbrook | uint32_t c0_ccsid[16]; /* Cache size. */ |
108 | a49ea279 | pbrook | uint32_t c0_clid; /* Cache level. */
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109 | a49ea279 | pbrook | uint32_t c0_cssel; /* Cache size selection. */
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110 | 9ee6e8bb | pbrook | uint32_t c0_c1[8]; /* Feature registers. */ |
111 | 9ee6e8bb | pbrook | uint32_t c0_c2[8]; /* Instruction set registers. */ |
112 | b5ff1b31 | bellard | uint32_t c1_sys; /* System control register. */
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113 | b5ff1b31 | bellard | uint32_t c1_coproc; /* Coprocessor access register. */
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114 | 610c3c8a | balrog | uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
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115 | 9ee6e8bb | pbrook | uint32_t c2_base0; /* MMU translation table base 0. */
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116 | 9ee6e8bb | pbrook | uint32_t c2_base1; /* MMU translation table base 1. */
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117 | b2fa1797 | pbrook | uint32_t c2_control; /* MMU translation table base control. */
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118 | b2fa1797 | pbrook | uint32_t c2_mask; /* MMU translation table base selection mask. */
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119 | b2fa1797 | pbrook | uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
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120 | ce819861 | pbrook | uint32_t c2_data; /* MPU data cachable bits. */
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121 | ce819861 | pbrook | uint32_t c2_insn; /* MPU instruction cachable bits. */
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122 | ce819861 | pbrook | uint32_t c3; /* MMU domain access control register
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123 | ce819861 | pbrook | MPU write buffer control. */
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124 | b5ff1b31 | bellard | uint32_t c5_insn; /* Fault status registers. */
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125 | b5ff1b31 | bellard | uint32_t c5_data; |
126 | ce819861 | pbrook | uint32_t c6_region[8]; /* MPU base/size registers. */ |
127 | b5ff1b31 | bellard | uint32_t c6_insn; /* Fault address registers. */
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128 | b5ff1b31 | bellard | uint32_t c6_data; |
129 | f8bf8606 | Adam Lackorzynski | uint32_t c7_par; /* Translation result. */
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130 | b5ff1b31 | bellard | uint32_t c9_insn; /* Cache lockdown registers. */
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131 | b5ff1b31 | bellard | uint32_t c9_data; |
132 | b5ff1b31 | bellard | uint32_t c13_fcse; /* FCSE PID. */
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133 | b5ff1b31 | bellard | uint32_t c13_context; /* Context ID. */
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134 | 9ee6e8bb | pbrook | uint32_t c13_tls1; /* User RW Thread register. */
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135 | 9ee6e8bb | pbrook | uint32_t c13_tls2; /* User RO Thread register. */
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136 | 9ee6e8bb | pbrook | uint32_t c13_tls3; /* Privileged Thread register. */
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137 | c1713132 | balrog | uint32_t c15_cpar; /* XScale Coprocessor Access Register */
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138 | c3d2689d | balrog | uint32_t c15_ticonfig; /* TI925T configuration byte. */
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139 | c3d2689d | balrog | uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
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140 | c3d2689d | balrog | uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
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141 | c3d2689d | balrog | uint32_t c15_threadid; /* TI debugger thread-ID. */
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142 | b5ff1b31 | bellard | } cp15; |
143 | 40f137e1 | pbrook | |
144 | 9ee6e8bb | pbrook | struct {
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145 | 9ee6e8bb | pbrook | uint32_t other_sp; |
146 | 9ee6e8bb | pbrook | uint32_t vecbase; |
147 | 9ee6e8bb | pbrook | uint32_t basepri; |
148 | 9ee6e8bb | pbrook | uint32_t control; |
149 | 9ee6e8bb | pbrook | int current_sp;
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150 | 9ee6e8bb | pbrook | int exception;
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151 | 9ee6e8bb | pbrook | int pending_exception;
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152 | 9ee6e8bb | pbrook | } v7m; |
153 | 9ee6e8bb | pbrook | |
154 | fe1479c3 | pbrook | /* Thumb-2 EE state. */
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155 | fe1479c3 | pbrook | uint32_t teecr; |
156 | fe1479c3 | pbrook | uint32_t teehbr; |
157 | fe1479c3 | pbrook | |
158 | 40f137e1 | pbrook | /* Internal CPU feature flags. */
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159 | 40f137e1 | pbrook | uint32_t features; |
160 | 40f137e1 | pbrook | |
161 | b7bcbe95 | bellard | /* VFP coprocessor state. */
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162 | b7bcbe95 | bellard | struct {
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163 | 9ee6e8bb | pbrook | float64 regs[32];
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164 | b7bcbe95 | bellard | |
165 | 40f137e1 | pbrook | uint32_t xregs[16];
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166 | b7bcbe95 | bellard | /* We store these fpcsr fields separately for convenience. */
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167 | b7bcbe95 | bellard | int vec_len;
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168 | b7bcbe95 | bellard | int vec_stride;
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169 | b7bcbe95 | bellard | |
170 | 9ee6e8bb | pbrook | /* scratch space when Tn are not sufficient. */
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171 | 9ee6e8bb | pbrook | uint32_t scratch[8];
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172 | 3b46e624 | ths | |
173 | 3a492f3a | Peter Maydell | /* fp_status is the "normal" fp status. standard_fp_status retains
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174 | 3a492f3a | Peter Maydell | * values corresponding to the ARM "Standard FPSCR Value", ie
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175 | 3a492f3a | Peter Maydell | * default-NaN, flush-to-zero, round-to-nearest and is used by
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176 | 3a492f3a | Peter Maydell | * any operations (generally Neon) which the architecture defines
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177 | 3a492f3a | Peter Maydell | * as controlled by the standard FPSCR value rather than the FPSCR.
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178 | 3a492f3a | Peter Maydell | *
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179 | 3a492f3a | Peter Maydell | * To avoid having to transfer exception bits around, we simply
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180 | 3a492f3a | Peter Maydell | * say that the FPSCR cumulative exception flags are the logical
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181 | 3a492f3a | Peter Maydell | * OR of the flags in the two fp statuses. This relies on the
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182 | 3a492f3a | Peter Maydell | * only thing which needs to read the exception flags being
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183 | 3a492f3a | Peter Maydell | * an explicit FPSCR read.
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184 | 3a492f3a | Peter Maydell | */
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185 | 53cd6637 | bellard | float_status fp_status; |
186 | 3a492f3a | Peter Maydell | float_status standard_fp_status; |
187 | b7bcbe95 | bellard | } vfp; |
188 | 426f5abc | Paul Brook | uint32_t exclusive_addr; |
189 | 426f5abc | Paul Brook | uint32_t exclusive_val; |
190 | 426f5abc | Paul Brook | uint32_t exclusive_high; |
191 | 9ee6e8bb | pbrook | #if defined(CONFIG_USER_ONLY)
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192 | 426f5abc | Paul Brook | uint32_t exclusive_test; |
193 | 426f5abc | Paul Brook | uint32_t exclusive_info; |
194 | 9ee6e8bb | pbrook | #endif
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195 | b7bcbe95 | bellard | |
196 | 18c9b560 | balrog | /* iwMMXt coprocessor state. */
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197 | 18c9b560 | balrog | struct {
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198 | 18c9b560 | balrog | uint64_t regs[16];
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199 | 18c9b560 | balrog | uint64_t val; |
200 | 18c9b560 | balrog | |
201 | 18c9b560 | balrog | uint32_t cregs[16];
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202 | 18c9b560 | balrog | } iwmmxt; |
203 | 18c9b560 | balrog | |
204 | ce4defa0 | pbrook | #if defined(CONFIG_USER_ONLY)
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205 | ce4defa0 | pbrook | /* For usermode syscall translation. */
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206 | ce4defa0 | pbrook | int eabi;
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207 | ce4defa0 | pbrook | #endif
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208 | ce4defa0 | pbrook | |
209 | a316d335 | bellard | CPU_COMMON |
210 | a316d335 | bellard | |
211 | 9d551997 | balrog | /* These fields after the common ones so they are preserved on reset. */
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212 | 9ba8c3f4 | Lars Munch | |
213 | 9ba8c3f4 | Lars Munch | /* Coprocessor IO used by peripherals */
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214 | 9ba8c3f4 | Lars Munch | struct {
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215 | 9ba8c3f4 | Lars Munch | ARMReadCPFunc *cp_read; |
216 | 9ba8c3f4 | Lars Munch | ARMWriteCPFunc *cp_write; |
217 | 9ba8c3f4 | Lars Munch | void *opaque;
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218 | 9ba8c3f4 | Lars Munch | } cp[15];
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219 | 983fe826 | Paul Brook | void *nvic;
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220 | f93eb9ff | balrog | struct arm_boot_info *boot_info;
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221 | 2c0262af | bellard | } CPUARMState; |
222 | 2c0262af | bellard | |
223 | aaed909a | bellard | CPUARMState *cpu_arm_init(const char *cpu_model); |
224 | b26eefb6 | pbrook | void arm_translate_init(void); |
225 | 2c0262af | bellard | int cpu_arm_exec(CPUARMState *s);
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226 | 2c0262af | bellard | void cpu_arm_close(CPUARMState *s);
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227 | b5ff1b31 | bellard | void do_interrupt(CPUARMState *);
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228 | b5ff1b31 | bellard | void switch_mode(CPUARMState *, int); |
229 | 9ee6e8bb | pbrook | uint32_t do_arm_semihosting(CPUARMState *env); |
230 | b5ff1b31 | bellard | |
231 | 2c0262af | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
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232 | 2c0262af | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
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233 | 2c0262af | bellard | is returned if the signal was handled by the virtual CPU. */
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234 | 5fafdf24 | ths | int cpu_arm_signal_handler(int host_signum, void *pinfo, |
235 | 2c0262af | bellard | void *puc);
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236 | 84a031c6 | aurel32 | int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, |
237 | 84a031c6 | aurel32 | int mmu_idx, int is_softmuu); |
238 | 0b5c1ce8 | Nathan Froyd | #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
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239 | 2c0262af | bellard | |
240 | fbb4a2e3 | pbrook | static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) |
241 | fbb4a2e3 | pbrook | { |
242 | fbb4a2e3 | pbrook | env->cp15.c13_tls2 = newtls; |
243 | fbb4a2e3 | pbrook | } |
244 | 9ee6e8bb | pbrook | |
245 | b5ff1b31 | bellard | #define CPSR_M (0x1f) |
246 | b5ff1b31 | bellard | #define CPSR_T (1 << 5) |
247 | b5ff1b31 | bellard | #define CPSR_F (1 << 6) |
248 | b5ff1b31 | bellard | #define CPSR_I (1 << 7) |
249 | b5ff1b31 | bellard | #define CPSR_A (1 << 8) |
250 | b5ff1b31 | bellard | #define CPSR_E (1 << 9) |
251 | b5ff1b31 | bellard | #define CPSR_IT_2_7 (0xfc00) |
252 | 9ee6e8bb | pbrook | #define CPSR_GE (0xf << 16) |
253 | 9ee6e8bb | pbrook | #define CPSR_RESERVED (0xf << 20) |
254 | b5ff1b31 | bellard | #define CPSR_J (1 << 24) |
255 | b5ff1b31 | bellard | #define CPSR_IT_0_1 (3 << 25) |
256 | b5ff1b31 | bellard | #define CPSR_Q (1 << 27) |
257 | 9ee6e8bb | pbrook | #define CPSR_V (1 << 28) |
258 | 9ee6e8bb | pbrook | #define CPSR_C (1 << 29) |
259 | 9ee6e8bb | pbrook | #define CPSR_Z (1 << 30) |
260 | 9ee6e8bb | pbrook | #define CPSR_N (1 << 31) |
261 | 9ee6e8bb | pbrook | #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
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262 | 9ee6e8bb | pbrook | |
263 | 9ee6e8bb | pbrook | #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
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264 | 9ee6e8bb | pbrook | #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
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265 | 9ee6e8bb | pbrook | /* Bits writable in user mode. */
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266 | 9ee6e8bb | pbrook | #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
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267 | 9ee6e8bb | pbrook | /* Execution state bits. MRS read as zero, MSR writes ignored. */
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268 | 9ee6e8bb | pbrook | #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
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269 | b5ff1b31 | bellard | |
270 | b5ff1b31 | bellard | /* Return the current CPSR value. */
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271 | 2f4a40e5 | balrog | uint32_t cpsr_read(CPUARMState *env); |
272 | 2f4a40e5 | balrog | /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
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273 | 2f4a40e5 | balrog | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
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274 | 9ee6e8bb | pbrook | |
275 | 9ee6e8bb | pbrook | /* Return the current xPSR value. */
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276 | 9ee6e8bb | pbrook | static inline uint32_t xpsr_read(CPUARMState *env) |
277 | 9ee6e8bb | pbrook | { |
278 | 9ee6e8bb | pbrook | int ZF;
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279 | 6fbe23d5 | pbrook | ZF = (env->ZF == 0);
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280 | 6fbe23d5 | pbrook | return (env->NF & 0x80000000) | (ZF << 30) |
281 | 9ee6e8bb | pbrook | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
282 | 9ee6e8bb | pbrook | | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) |
283 | 9ee6e8bb | pbrook | | ((env->condexec_bits & 0xfc) << 8) |
284 | 9ee6e8bb | pbrook | | env->v7m.exception; |
285 | b5ff1b31 | bellard | } |
286 | b5ff1b31 | bellard | |
287 | 9ee6e8bb | pbrook | /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
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288 | 9ee6e8bb | pbrook | static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) |
289 | 9ee6e8bb | pbrook | { |
290 | 9ee6e8bb | pbrook | if (mask & CPSR_NZCV) {
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291 | 6fbe23d5 | pbrook | env->ZF = (~val) & CPSR_Z; |
292 | 6fbe23d5 | pbrook | env->NF = val; |
293 | 9ee6e8bb | pbrook | env->CF = (val >> 29) & 1; |
294 | 9ee6e8bb | pbrook | env->VF = (val << 3) & 0x80000000; |
295 | 9ee6e8bb | pbrook | } |
296 | 9ee6e8bb | pbrook | if (mask & CPSR_Q)
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297 | 9ee6e8bb | pbrook | env->QF = ((val & CPSR_Q) != 0);
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298 | 9ee6e8bb | pbrook | if (mask & (1 << 24)) |
299 | 9ee6e8bb | pbrook | env->thumb = ((val & (1 << 24)) != 0); |
300 | 9ee6e8bb | pbrook | if (mask & CPSR_IT_0_1) {
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301 | 9ee6e8bb | pbrook | env->condexec_bits &= ~3;
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302 | 9ee6e8bb | pbrook | env->condexec_bits |= (val >> 25) & 3; |
303 | 9ee6e8bb | pbrook | } |
304 | 9ee6e8bb | pbrook | if (mask & CPSR_IT_2_7) {
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305 | 9ee6e8bb | pbrook | env->condexec_bits &= 3;
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306 | 9ee6e8bb | pbrook | env->condexec_bits |= (val >> 8) & 0xfc; |
307 | 9ee6e8bb | pbrook | } |
308 | 9ee6e8bb | pbrook | if (mask & 0x1ff) { |
309 | 9ee6e8bb | pbrook | env->v7m.exception = val & 0x1ff;
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310 | 9ee6e8bb | pbrook | } |
311 | 9ee6e8bb | pbrook | } |
312 | 9ee6e8bb | pbrook | |
313 | 01653295 | Peter Maydell | /* Return the current FPSCR value. */
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314 | 01653295 | Peter Maydell | uint32_t vfp_get_fpscr(CPUARMState *env); |
315 | 01653295 | Peter Maydell | void vfp_set_fpscr(CPUARMState *env, uint32_t val);
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316 | 01653295 | Peter Maydell | |
317 | b5ff1b31 | bellard | enum arm_cpu_mode {
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318 | b5ff1b31 | bellard | ARM_CPU_MODE_USR = 0x10,
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319 | b5ff1b31 | bellard | ARM_CPU_MODE_FIQ = 0x11,
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320 | b5ff1b31 | bellard | ARM_CPU_MODE_IRQ = 0x12,
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321 | b5ff1b31 | bellard | ARM_CPU_MODE_SVC = 0x13,
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322 | b5ff1b31 | bellard | ARM_CPU_MODE_ABT = 0x17,
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323 | b5ff1b31 | bellard | ARM_CPU_MODE_UND = 0x1b,
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324 | b5ff1b31 | bellard | ARM_CPU_MODE_SYS = 0x1f
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325 | b5ff1b31 | bellard | }; |
326 | b5ff1b31 | bellard | |
327 | 40f137e1 | pbrook | /* VFP system registers. */
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328 | 40f137e1 | pbrook | #define ARM_VFP_FPSID 0 |
329 | 40f137e1 | pbrook | #define ARM_VFP_FPSCR 1 |
330 | 9ee6e8bb | pbrook | #define ARM_VFP_MVFR1 6 |
331 | 9ee6e8bb | pbrook | #define ARM_VFP_MVFR0 7 |
332 | 40f137e1 | pbrook | #define ARM_VFP_FPEXC 8 |
333 | 40f137e1 | pbrook | #define ARM_VFP_FPINST 9 |
334 | 40f137e1 | pbrook | #define ARM_VFP_FPINST2 10 |
335 | 40f137e1 | pbrook | |
336 | 18c9b560 | balrog | /* iwMMXt coprocessor control registers. */
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337 | 18c9b560 | balrog | #define ARM_IWMMXT_wCID 0 |
338 | 18c9b560 | balrog | #define ARM_IWMMXT_wCon 1 |
339 | 18c9b560 | balrog | #define ARM_IWMMXT_wCSSF 2 |
340 | 18c9b560 | balrog | #define ARM_IWMMXT_wCASF 3 |
341 | 18c9b560 | balrog | #define ARM_IWMMXT_wCGR0 8 |
342 | 18c9b560 | balrog | #define ARM_IWMMXT_wCGR1 9 |
343 | 18c9b560 | balrog | #define ARM_IWMMXT_wCGR2 10 |
344 | 18c9b560 | balrog | #define ARM_IWMMXT_wCGR3 11 |
345 | 18c9b560 | balrog | |
346 | 40f137e1 | pbrook | enum arm_features {
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347 | 40f137e1 | pbrook | ARM_FEATURE_VFP, |
348 | c1713132 | balrog | ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
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349 | c1713132 | balrog | ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
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350 | ce819861 | pbrook | ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
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351 | 9ee6e8bb | pbrook | ARM_FEATURE_V6, |
352 | 9ee6e8bb | pbrook | ARM_FEATURE_V6K, |
353 | 9ee6e8bb | pbrook | ARM_FEATURE_V7, |
354 | 9ee6e8bb | pbrook | ARM_FEATURE_THUMB2, |
355 | c3d2689d | balrog | ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
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356 | 9ee6e8bb | pbrook | ARM_FEATURE_VFP3, |
357 | 60011498 | Paul Brook | ARM_FEATURE_VFP_FP16, |
358 | 9ee6e8bb | pbrook | ARM_FEATURE_NEON, |
359 | 9ee6e8bb | pbrook | ARM_FEATURE_DIV, |
360 | 9ee6e8bb | pbrook | ARM_FEATURE_M, /* Microcontroller profile. */
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361 | fe1479c3 | pbrook | ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
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362 | e1bbf446 | Peter Maydell | ARM_FEATURE_THUMB2EE, |
363 | e1bbf446 | Peter Maydell | ARM_FEATURE_V7MP /* v7 Multiprocessing Extensions */
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364 | 40f137e1 | pbrook | }; |
365 | 40f137e1 | pbrook | |
366 | 40f137e1 | pbrook | static inline int arm_feature(CPUARMState *env, int feature) |
367 | 40f137e1 | pbrook | { |
368 | 40f137e1 | pbrook | return (env->features & (1u << feature)) != 0; |
369 | 40f137e1 | pbrook | } |
370 | 40f137e1 | pbrook | |
371 | 9a78eead | Stefan Weil | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
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372 | 40f137e1 | pbrook | |
373 | 9ee6e8bb | pbrook | /* Interface between CPU and Interrupt controller. */
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374 | 9ee6e8bb | pbrook | void armv7m_nvic_set_pending(void *opaque, int irq); |
375 | 9ee6e8bb | pbrook | int armv7m_nvic_acknowledge_irq(void *opaque); |
376 | 9ee6e8bb | pbrook | void armv7m_nvic_complete_irq(void *opaque, int irq); |
377 | 9ee6e8bb | pbrook | |
378 | c1713132 | balrog | void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, |
379 | c1713132 | balrog | ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, |
380 | c1713132 | balrog | void *opaque);
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381 | c1713132 | balrog | |
382 | 9ee6e8bb | pbrook | /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
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383 | 9ee6e8bb | pbrook | Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
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384 | 9ee6e8bb | pbrook | conventional cores (ie. Application or Realtime profile). */
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385 | 9ee6e8bb | pbrook | |
386 | 9ee6e8bb | pbrook | #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
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387 | 9ee6e8bb | pbrook | #define ARM_CPUID(env) (env->cp15.c0_cpuid)
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388 | 9ee6e8bb | pbrook | |
389 | 9ee6e8bb | pbrook | #define ARM_CPUID_ARM1026 0x4106a262 |
390 | 9ee6e8bb | pbrook | #define ARM_CPUID_ARM926 0x41069265 |
391 | 9ee6e8bb | pbrook | #define ARM_CPUID_ARM946 0x41059461 |
392 | 9ee6e8bb | pbrook | #define ARM_CPUID_TI915T 0x54029152 |
393 | 9ee6e8bb | pbrook | #define ARM_CPUID_TI925T 0x54029252 |
394 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA250 0x69052100 |
395 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA255 0x69052d00 |
396 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA260 0x69052903 |
397 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA261 0x69052d05 |
398 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA262 0x69052d06 |
399 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA270 0x69054110 |
400 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA270_A0 0x69054110 |
401 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA270_A1 0x69054111 |
402 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA270_B0 0x69054112 |
403 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA270_B1 0x69054113 |
404 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA270_C0 0x69054114 |
405 | 9ee6e8bb | pbrook | #define ARM_CPUID_PXA270_C5 0x69054117 |
406 | 9ee6e8bb | pbrook | #define ARM_CPUID_ARM1136 0x4117b363 |
407 | 827df9f3 | balrog | #define ARM_CPUID_ARM1136_R2 0x4107b362 |
408 | 9ee6e8bb | pbrook | #define ARM_CPUID_ARM11MPCORE 0x410fb022 |
409 | 9ee6e8bb | pbrook | #define ARM_CPUID_CORTEXA8 0x410fc080 |
410 | 10055562 | Paul Brook | #define ARM_CPUID_CORTEXA9 0x410fc090 |
411 | 9ee6e8bb | pbrook | #define ARM_CPUID_CORTEXM3 0x410fc231 |
412 | 9ee6e8bb | pbrook | #define ARM_CPUID_ANY 0xffffffff |
413 | 40f137e1 | pbrook | |
414 | b5ff1b31 | bellard | #if defined(CONFIG_USER_ONLY)
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415 | 2c0262af | bellard | #define TARGET_PAGE_BITS 12 |
416 | b5ff1b31 | bellard | #else
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417 | b5ff1b31 | bellard | /* The ARM MMU allows 1k pages. */
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418 | b5ff1b31 | bellard | /* ??? Linux doesn't actually use these, and they're deprecated in recent
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419 | 82d17978 | balrog | architecture revisions. Maybe a configure option to disable them. */
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420 | b5ff1b31 | bellard | #define TARGET_PAGE_BITS 10 |
421 | b5ff1b31 | bellard | #endif
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422 | 9467d44c | ths | |
423 | 52705890 | Richard Henderson | #define TARGET_PHYS_ADDR_SPACE_BITS 32 |
424 | 52705890 | Richard Henderson | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
425 | 52705890 | Richard Henderson | |
426 | 9467d44c | ths | #define cpu_init cpu_arm_init
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427 | 9467d44c | ths | #define cpu_exec cpu_arm_exec
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428 | 9467d44c | ths | #define cpu_gen_code cpu_arm_gen_code
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429 | 9467d44c | ths | #define cpu_signal_handler cpu_arm_signal_handler
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430 | c732abe2 | j_mayer | #define cpu_list arm_cpu_list
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431 | 9467d44c | ths | |
432 | f8bf8606 | Adam Lackorzynski | #define CPU_SAVE_VERSION 3 |
433 | 9ee6e8bb | pbrook | |
434 | 6ebbf390 | j_mayer | /* MMU modes definitions */
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435 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _kernel
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436 | 6ebbf390 | j_mayer | #define MMU_MODE1_SUFFIX _user
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437 | 6ebbf390 | j_mayer | #define MMU_USER_IDX 1 |
438 | 6ebbf390 | j_mayer | static inline int cpu_mmu_index (CPUState *env) |
439 | 6ebbf390 | j_mayer | { |
440 | 6ebbf390 | j_mayer | return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; |
441 | 6ebbf390 | j_mayer | } |
442 | 6ebbf390 | j_mayer | |
443 | 6e68e076 | pbrook | #if defined(CONFIG_USER_ONLY)
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444 | 6e68e076 | pbrook | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
445 | 6e68e076 | pbrook | { |
446 | f8ed7070 | pbrook | if (newsp)
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447 | 6e68e076 | pbrook | env->regs[13] = newsp;
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448 | 6e68e076 | pbrook | env->regs[0] = 0; |
449 | 6e68e076 | pbrook | } |
450 | 6e68e076 | pbrook | #endif
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451 | 6e68e076 | pbrook | |
452 | 2c0262af | bellard | #include "cpu-all.h" |
453 | 622ed360 | aliguori | |
454 | a1705768 | Peter Maydell | /* Bit usage in the TB flags field: */
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455 | a1705768 | Peter Maydell | #define ARM_TBFLAG_THUMB_SHIFT 0 |
456 | a1705768 | Peter Maydell | #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) |
457 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VECLEN_SHIFT 1 |
458 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) |
459 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 |
460 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) |
461 | a1705768 | Peter Maydell | #define ARM_TBFLAG_PRIV_SHIFT 6 |
462 | a1705768 | Peter Maydell | #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT) |
463 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VFPEN_SHIFT 7 |
464 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) |
465 | a1705768 | Peter Maydell | #define ARM_TBFLAG_CONDEXEC_SHIFT 8 |
466 | a1705768 | Peter Maydell | #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) |
467 | a1705768 | Peter Maydell | /* Bits 31..16 are currently unused. */
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468 | a1705768 | Peter Maydell | |
469 | a1705768 | Peter Maydell | /* some convenience accessor macros */
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470 | a1705768 | Peter Maydell | #define ARM_TBFLAG_THUMB(F) \
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471 | a1705768 | Peter Maydell | (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) |
472 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VECLEN(F) \
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473 | a1705768 | Peter Maydell | (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) |
474 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VECSTRIDE(F) \
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475 | a1705768 | Peter Maydell | (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) |
476 | a1705768 | Peter Maydell | #define ARM_TBFLAG_PRIV(F) \
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477 | a1705768 | Peter Maydell | (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT) |
478 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VFPEN(F) \
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479 | a1705768 | Peter Maydell | (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) |
480 | a1705768 | Peter Maydell | #define ARM_TBFLAG_CONDEXEC(F) \
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481 | a1705768 | Peter Maydell | (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) |
482 | a1705768 | Peter Maydell | |
483 | 6b917547 | aliguori | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
484 | 6b917547 | aliguori | target_ulong *cs_base, int *flags)
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485 | 6b917547 | aliguori | { |
486 | 05ed9a99 | Peter Maydell | int privmode;
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487 | 6b917547 | aliguori | *pc = env->regs[15];
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488 | 6b917547 | aliguori | *cs_base = 0;
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489 | a1705768 | Peter Maydell | *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) |
490 | a1705768 | Peter Maydell | | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) |
491 | a1705768 | Peter Maydell | | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) |
492 | a1705768 | Peter Maydell | | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT); |
493 | 05ed9a99 | Peter Maydell | if (arm_feature(env, ARM_FEATURE_M)) {
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494 | 05ed9a99 | Peter Maydell | privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1)); |
495 | 05ed9a99 | Peter Maydell | } else {
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496 | 05ed9a99 | Peter Maydell | privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; |
497 | 05ed9a99 | Peter Maydell | } |
498 | 05ed9a99 | Peter Maydell | if (privmode) {
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499 | a1705768 | Peter Maydell | *flags |= ARM_TBFLAG_PRIV_MASK; |
500 | a1705768 | Peter Maydell | } |
501 | a1705768 | Peter Maydell | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { |
502 | a1705768 | Peter Maydell | *flags |= ARM_TBFLAG_VFPEN_MASK; |
503 | a1705768 | Peter Maydell | } |
504 | 6b917547 | aliguori | } |
505 | 6b917547 | aliguori | |
506 | 2c0262af | bellard | #endif |