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# Date Author Comment
29501f1b 03/07/2011 12:30 am Peter Maydell

target-arm: Set carry flag correctly for Thumb2 ORNS

The code for Thumb2 ORNS (or negated and set flags) was trashing
a TCG input register which was needed later for use in calculating
flags, with the effect that the carry flag was always set with
the wrong sense. Fix this by using the TCG orc op instead of...

8387da81 03/06/2011 09:28 pm Peter Maydell

target-arm: Handle VMOV between two core and VFP single regs

Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry and
VMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and a
pair of VFP single precision registers):

  • An incorrect condition meant these instruction patterns were being...
cc688901 03/06/2011 09:20 pm Peter Maydell

target-arm: Don't decode old cp15 WFI instructions on v7 cores

In v7 of the ARM architecture, WFI (wait for interrupt) is a first-class
instruction, but in previous versions this functionality was provided
via a cp15 coprocessor register. Add correct feature checks to the...

92cdfaeb 02/21/2011 04:39 pm Peter Maydell

target-arm: Fix shift by immediate and narrow where src, dest overlap

For Neon shifts by immediate and narrow, correctly handle the case
where the source registers and the destination registers overlap
(the second pass should use the original register contents, not the...

c33171c7 02/21/2011 04:39 pm Peter Maydell

target-arm: Refactor to pull narrowing decode into separate function

Pull the code which decodes narrowing operations as being either
signed/unsigned saturate or plain out into its own function.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

b408a9b0 02/20/2011 06:43 pm Christophe Lyon

target-arm: fix Neon VQSHRN and VSHRN.

Call the normal shift helpers instead of the rounding ones.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

0b36f4cd 02/20/2011 06:43 pm Christophe Lyon

target-arm: fix decoding of Neon 64 bit shifts.

Fix decoding of 64 bits variants of VSHRN, VRSHRN, VQSHRN, VQSHRUN,
VQRSHRN, VQRSHRUN, taking into account whether inputs are unsigned
or not.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>...

d68a6f3a 02/20/2011 06:31 pm Peter Maydell

target-arm: Move Neon VZIP to helper functions

Move the implementation of the Neon VUZP unzip instruction from inline
code to helper functions. (At 50+ TCG ops it was well over the
recommended limit for coding inline.) The helper implementations also
give the correct answers where the inline implementation did not....

02acedf9 02/20/2011 06:31 pm Peter Maydell

target-arm: Move Neon VUZP to helper functions

Move the implementation of the Neon VUZP unzip instruction from inline
code to helper functions. (At 50+ TCG ops it was well over the
recommended limit for coding inline.) The helper implementations also
fix the handling of the quadword version of the instruction....

f06053e3 02/20/2011 06:30 pm Juha Riihimäki

target-arm: Correct conversion of Thumb Neon dp encodings into ARM

We handle Thumb Neon data processing instructions by converting them
into the equivalent ARM encoding, as the two are very close. However
the ARM encoding should have bit 28 set, not clear. This wasn't causing...

4dc064e6 02/20/2011 06:28 pm Peter Maydell

target-arm: Fix Neon VQDMLSL instruction

For VQDMLSL, negation has to occur after saturation, not before.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

ebcd88ce 02/20/2011 06:28 pm Peter Maydell

target-arm: Refactor handling of VQDMULL

Refactor the handling of VQDMULL so that it is dealt with in
its own if() case rather than together with the accumulating
instructions.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

e5ca24cb 02/20/2011 06:26 pm Peter Maydell

target-arm: Implement VMULL.P8

Implement VMULL.P8 (the 32x32->64 version of the polynomial multiply
instruction).

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

2d981da7 02/10/2011 07:28 pm Peter Maydell

target-arm: Use standard FPSCR for Neon half-precision operations

The Neon half-precision conversion operations (VCVT.F16.F32 and
VCVT.F32.F16) use ARM standard floating-point arithmetic, unlike
the VFP versions (VCVTB and VCVTT).

Signed-off-by: Peter Maydell <>...

923e6509 02/09/2011 08:48 pm Christophe Lyon

target-arm: implement vsli.64, vsri.64

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

acdf01ef 02/09/2011 08:47 pm Christophe Lyon

target-arm: fix VSHLL Neon instruction.

Fix bit mask used when widening the result of shift on narrow input.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

af1bbf30 02/09/2011 08:37 pm Juha Riihimäki

target-arm: Fix VQMOVUN Neon instruction.

VQMOVUN does a signed-to-unsigned saturating conversion. This is
different from both the signed-to-signed and unsigned-to-unsigned
conversions already implemented, so we need a new set of helper
functions (neon_unarrow_sat*)....

3d185e5d 02/04/2011 10:30 pm Peter Maydell

target-arm: Fix decoding of preload and memory hint space

Correct the decoding of the ARM preload and memory hint space,
by adding decoding of PLI, PLDW and the v7MP unallocated hint
space. This commit also corrects a slightly overexuberant
decoding of PLD which was not checking that bit 4...

a2fdc890 02/04/2011 10:30 pm Peter Maydell

target-arm: Fix decoding of Thumb preload and hint space

Refine the decoding of the Thumb preload and hint space, so we
UNDEF on the patterns that are supposed to UNDEF rather than NOP.
We also move the tests for this space earlier, so we don't emit
harmless but unnecessary address generation code for preload...

72902672 02/04/2011 09:57 pm Christophe Lyon

Set the right overflow bit for neon 32 and 64 bit saturating add/sub.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

5371cb81 02/04/2011 09:48 pm Christophe Lyon

target-arm: Fix Neon vsra instructions.

This patch fixes the errors reported by my tests in VSRA.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

40d3c433 01/26/2011 03:30 pm Christophe Lyon

Support saturation with shift=0.

This patch fixes corner-case saturations, when the target range is
zero. It merely removes the guard against (sh == 0), and makes:
_ssat(0x87654321, 1) return 0xffffffff and set the saturation flag
_usat(0x87654321, 0) return 0 and set the saturation flag...

c6067f04 01/26/2011 03:30 pm Christophe Lyon

target-arm: Fix garbage collection of temporaries in Neon emulation.

Fix garbage collection of temporaries in Neon emulation.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

0fad6efc 01/26/2011 03:30 pm Peter Maydell

target-arm: Fix loading of scalar value for Neon multiply-by-scalar

Fix the register and part of register we get the scalar from in
the various "multiply vector by scalar" ops (VMUL by scalar
and friends).

Signed-off-by: Peter Maydell <>...

5642463a 01/18/2011 04:23 pm Peter Maydell

target-arm: Log instruction start in TCG code

Add support for logging the start of instructions in TCG
code debug dumps for ARM targets.

Signed-off-by: Peter Maydell <>
Signed-off-by: Edgar E. Iglesias <>

5df8bac1 01/14/2011 09:39 pm Peter Maydell

target-arm: Translate with VFP-enabled from TB flags, not CPUState

When translating code, whether the VFP unit is enabled for this TB
is stored in a bit in the TB flags. Use this rather than incorrectly
reading the FPEXC from the CPUState passed to translation....

69d1fc22 01/14/2011 09:39 pm Peter Maydell

target-arm: Translate with VFP len/stride from TB flags, not CPUState

When translating, the VFP vector length and stride for this TB are encoded
in the TB flags; the CPUState copies may be different and must not be used.

Signed-off-by: Peter Maydell <>...

7204ab88 01/14/2011 09:39 pm Peter Maydell

target-arm: Translate with Thumb state from TB flags, not CPUState

The Thumb/ARM state for the TB being translated should come from
the TB flags, not the CPUState.

Signed-off-by: Peter Maydell <>
Reviewed-by: Aurelien Jarno <>...

98eac7ca 01/14/2011 09:39 pm Peter Maydell

target-arm: Translate with condexec bits from TB flags, not CPUState

When translating, the condexec bits for the TB are in the TB flags;
the CPUState condexec bits may be different.

This patch fixes https://bugs.launchpad.net/bugs/604872 where we might
segfault if we took an exception in the middle of a TB with an IT...

61f74d6a 01/14/2011 09:39 pm Peter Maydell

target-arm: Translate with user-state from TB flags, not CPUState

When translating, get the user/priv state from the TB flags, not
the CPUState.

Signed-off-by: Peter Maydell <>
Reviewed-by: Aurelien Jarno <>
Signed-off-by: Aurelien Jarno <>

5de3a9d3 01/14/2011 09:39 pm Peter Maydell

target-arm: Remove redundant setting of IT bits before Thumb SWI

Remove a redundant call to gen_set_condexec() in the translation of Thumb
mode SWI. (SWI and WFI generate "exceptions" which happen after the
execution of the instruction, ie when PC and IT bits have updated....

bc4a0de0 01/14/2011 09:39 pm Peter Maydell

target-arm: Refactor translation of exception generating instructions

Create a new function which does the common sequence of gen_set_condexec,
gen_set_pc_im, gen_exception, set is_jmp to DISAS_JUMP.

Signed-off-by: Peter Maydell <>...

e12ce78d 01/14/2011 09:39 pm Peter Maydell

target-arm: Restore IT bits when resuming after an exception

We were not correctly restoring the IT bits when resuming execution
after taking an unexpected exception in the middle of an IT block.
Fix this by tracking them along with PC changes and restoring in...

39ea3d4e 01/14/2011 09:39 pm Peter Maydell

target-arm: Don't generate code specific to current CPU mode for SRS

When translating the SRS instruction, handle the "store registers
to stack of current mode" case in the helper function rather than
inline. This means the generated code does not make assumptions...

0322b26e 01/12/2011 01:06 am Peter Maydell

ARM: Fix decoding of VQSHL/VQSHLU immediate forms

Fix errors in the decoding of ARM VQSHL/VQSHLU immediate forms,
including using the new VQSHLU helper functions where appropriate.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Peter Maydell <>...

838fa72d 01/06/2011 11:16 pm Aurelien Jarno

target-arm: fix SMMLA/SMMLS instructions

SMMLA and SMMLS are broken on both in normal and thumb mode, that is
both (different) implementations are wrong. They try to avoid a 64-bit
add for the rounding, which is not trivial if you want to support both
SMMLA and SMMLS with the same code....

8aac08b1 12/31/2010 11:22 pm Aurelien Jarno

target-arm: fix UMAAL instruction

UMAAL should use unsigned multiply instead of signed.

This patch fixes this issue by handling UMAAL separately from
UMULL/UMLAL/SMULL/SMLAL as these instructions are different
enough. It also explicitly list instructions in case and catch...

def126ce 12/27/2010 10:06 pm Juha Riihimäki

target-arm: Fix arguments passed to VQSHL helpers

Correct the arguments passed when generating neon qshl_{u,s}64()
helpers so that we use the correct registers.

Signed-off-by: Juha Riihimäki <>
Reviewed-by: Peter Maydell <>...

1a855029 12/27/2010 08:56 pm Aurelien Jarno

target-arm: fix bug in translation of REVSH

The translation of REVSH shifted the low byte 8 steps left before performing
an 8-bit sign extend, causing this part of the expression to alwas be 0.

Reported-by: Johan Bengtsson <>
Signed-off-by: Aurelien Jarno <>

2c9adbda 12/07/2010 05:37 pm Peter Maydell

ARM: fix ldrexd/strexd

Correct ldrexd and strexd code to always read and write the
high word of the 64-bit value from addr+4.
Also make ldrexd and strexd agree that for a 64 bit value the
address in env->exclusive_addr is that of the low word.

This fixes the issues reported in...

04595bf6 12/07/2010 05:37 pm Peter Maydell

ARM: Fix decoding of VFP forms of VCVT between float and int/fixed

Correct the decoding of source and destination registers
for the VFP forms of the VCVT instructions which convert
between floating point and integer or fixed-point.

Signed-off-by: Peter Maydell <>...

f73534a5 12/07/2010 05:37 pm Peter Maydell

ARM: Fix decoding of Neon forms of VCVT between float and fixed point

Fix errors in the decoding of the Neon forms of fixed-point VCVT: * fixed-point VCVT is op 14 and 15, not 15 and 16 * the fbits immediate field was being misinterpreted * the sense of the to_fixed bit was inverted...

d3587ef8 12/07/2010 05:37 pm Peter Maydell

ARM: Fix sense of to_integer bit in Neon VCVT float/int conversion

Signed-off-by: Peter Maydell <>
Reviewed-by: Nathan Froyd <>

2af9ab77 12/07/2010 02:01 pm Johan Bengtsson

target-arm: Add support for PKHxx in thumb2

The PKHxx instructions were not recognized by the thumb2 decoder. The
solution provided in this changeset is identical to the arm-mode
implementation.

Signed-off-by: Johan Bengtsson <>
Signed-off-by: Peter Maydell <>...

4809c612 12/07/2010 02:01 pm Johan Bengtsson

target-arm: Fix mixup in decoding of saturating add and sub

The thumb2 decoder contained a mixup between the bit controlling
doubling and the bit controlling if the operation was an add or a sub.

Signed-off-by: Johan Bengtsson <>
Signed-off-by: Peter Maydell <>...

49e14940 12/07/2010 02:01 pm Adam Lackorzynski

target-arm: Handle 'smc' as an undefined instruction

Refine check on bkpt so that smc and undefined instruction encodings are
handled as an undefined instruction and trap.

Signed-off-by: Adam Lackorzynski <>
Signed-off-by: Peter Maydell <>...

9a78eead 10/30/2010 11:01 am Stefan Weil

target-xxx: Use fprintf_function (format checking)

fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
  • target-i386/helper.c
  • target-mips/translate.c
  • target-ppc/translate.c

Cc: Blue Swirl <>
Signed-off-by: Stefan Weil <>...

ed89a2f1 07/02/2010 12:45 am Chih-Min Chao

target-arm : fix thumb2 parallel add/sub opcode decoding

Signed-off-by: Chih-Min Chao <>
Signed-off-by: Aurelien Jarno <>

41ba8341 06/11/2010 10:37 pm Paul Brook

NEON vldN optimization

When combining multiple values as part of a NEON array load, do explcit
shift/or rather than using gen_bfi. This voids redundant mask
operations.

Signed-off-by: Paul Brook <>

22ed1d34 04/25/2010 10:31 pm Blue Swirl

arm: remove dead assignments, spotted by clang analyzer

Value stored is never read.

Signed-off-by: Blue Swirl <>

8e31209e 04/08/2010 10:12 pm Juha Riihimäki

target-arm: fix neon vmon/vmvn with modified immediate

Signed-Off-By: Riku Voipio <>
Signed-off-by: Juha Riihimäki <>
Signed-off-by: Aurelien Jarno <>

d9968827 04/08/2010 12:11 pm Lars Munch

target-arm: resource leak fixes for iwmmxt disassemble

This patch fixes few resource leaks in the iwmmxt disassemble.

Signed-off-by: Lars Munch <>
Signed-off-by: Aurelien Jarno <>

bedd2912 03/23/2010 11:10 pm Johan Bengtsson

target-arm: Fix handling of AL condition in IT instruction

Do not try to insert a conditional jump over next instruction when the
condition code is AL as this will trigger an internal error.

Signed-off-by: Johan Bengtsson <>
Signed-off-by: Aurelien Jarno <>

ea825eee 03/13/2010 01:01 pm Adam Lackorzynski

target-arm: make RFE usable with any register

The rfe instruction can be used with any register, not just sp. Adjust the
condition check accordingly.

Signed-off-by: Adam Lackorzynski <>
Signed-off-by: Aurelien Jarno <>

a990f58f 03/07/2010 12:22 am Adam Lackorzynski

target-arm: Fix missing 'return' in SRS handling.

There's a return missing in the srs handling which leads to srs always being
treated an an invalid op.

Signed-off-by: Adam Lackorzynski <>
Signed-off-by: Aurelien Jarno <>

30d11a2a 02/28/2010 08:30 pm Juha Riihimäki

target-arm: neon vshll instruction fix

implementation only widened the 32bit source vector elements into a
64bit destination vector but forgot to perform the actual shifting
operation.

Signed-off-by: Juha Riihimäki <>
Signed-off-by: Riku Voipio <>...

79b0e534 02/28/2010 08:30 pm Riku Voipio

target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHN

The rounding/truncating options were inverted. truncating
was done when rounding was meant and vice verse.

Signed-off-by: Riku Voipio <>
Acked-by: Laurent Desnogues <>...

c5883be2 02/23/2010 04:45 pm Paul Brook

ARM CP15 tls fix

Fix temporary handling in cp15 tls register load/store.

Signed-off-by: Paul Brook <>

b8b45b68 02/19/2010 03:38 pm Rabin Vincent

target-arm: implement Thumb-2 exception return

Support the "subs pc, lr" Thumb-2 exception return instruction.

Signed-off-by: Rabin Vincent <>
Signed-off-by: Paul Brook <>

fa26df03 02/19/2010 03:38 pm Rabin Vincent

target-arm: fix thumb CPS

The Thumb CPS currently does not work correctly: CPSID touches more bits
than the instruction wants to, and CPSIE does nothing. Fix it by
passing the correct mask (the "affect" bits) and value.

Signed-off-by: Rabin Vincent <>

3f26c122 02/06/2010 06:19 pm Riku Voipio

target-arm: refactor cp15.c13 register access

Access the cp15.c13 TLS registers directly with TCG ops instead of with
a slow helper. If the the cp15 read/write was not TLS register access,
fall back to the cp15 helper.

This makes accessing __thread variables in linux-user when apps are compiled...

502e64fe 12/24/2009 01:18 am Aurelien Jarno

target-arm: fix strexd

Signed-off-by: Aurelien Jarno <>

426f5abc 11/22/2009 11:35 pm Paul Brook

ARM atomic ops rewrite

Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC.

Signed-off-by: Paul Brook <>

60011498 11/19/2009 06:45 pm Paul Brook

ARM FP16 support

Implement the ARM VFP half precision floating point extensions.

Signed-off-by: Paul Brook <>

f669df27 10/27/2009 10:46 am Aurelien Jarno

target-arm: use native tcg-ops for ror/bic/vorn

Acked-by: Laurent Desnogues <>
Signed-off-by: Aurelien Jarno <>

2301db49 10/27/2009 10:46 am Juha Riihimäki

target-arm: fix neon vshrn/vrshrn ops

In the existing code shift value is clobbered during the pass loop.
This patch changes the code so that it stores the intermediate
result in the target neon register directly and eliminates the need
to use a temporary to hold the intermediate value thus leaving the...

84496233 10/27/2009 10:46 am Juha Riihimäki

target-arm: add support for neon vld1.64/vst1.64 instructions

Add support for NEON vld1.64 and vst1.64 instructions. This patch is
revised to follow more closely the specification and raises
undefined exception if 64bit element size is used for vld2/vst2 or...

71b3c3de 10/27/2009 10:46 am Juha Riihimäki

target-arm: allow modifying vfp fpexc en bit only

All other bits except for the EN in the VFP FPEXC register are defined
as subarchitecture specific and real functionality for any of the
other bits has not been implemented in QEMU. However, current code
allows modifying all bits in the VFP FPEXC register leading to...

ca9a32e4 10/27/2009 10:46 am Juha Riihimäki

target-arm: fix neon vsri, vshl and vsli ops

Shift by immediate value is incorrectly overwritten by a temporary
variable in the processing of NEON vsri, vshl and vsli instructions.
This patch has been revised to also include a fix for the special
case where the code would previously try to shift an integer value...

25aeb69b 10/26/2009 09:36 pm Juha Riihimäki

target-arm: fix incorrect temporary variable freeing

tmp4 and tmp5 temporary variables are allocated using tcg_const_i32
but incorrectly released using dead_tmp which will cause resource
leak tracking to report false leaks.

Signed-off-by: Juha Riihimäki <>...

7b2919a0 10/23/2009 06:22 pm Juha.Riihimaki@nokia.com

target-arm: optimize thumb 32-bit multiply

Current implementation of thumb mul instruction is implemented as a
32x32->64 multiply which then uses only 32 least significant bits of
the result. Replace that with a simple 32x32->32 multiply.

Signed-off-by: Juha Riihimäki <>...

b75263d6 10/23/2009 06:11 pm Juha Riihimäki

target-arm: cleanup internal resource leaks

Revised patch for getting rid of tcg temporary variable leaks in
target-arm/translate.c. This version also includes the leak patch for
gen_set_cpsr macro, now converted as a static inline function, which I
sent earlier as a separate patch on top of this patch....

dcc65026 10/18/2009 05:00 pm Aurelien Jarno

target-arm: fix bugs introduced by 1b2b1e547bd912b7d3c4863d0a0f75f6f38330ed

Use load_reg_var() instead of accessing cpu_R[rn] directly to generate
correct code when rn = 15.

Signed-off-by: Aurelien Jarno <>

98a46317 10/18/2009 04:53 pm Aurelien Jarno

target-arm: fix bugs introduced by 3174f8e91fecf8756e861d1febb049f3c619a2c7

Use load_reg_var() instead of accessing cpu_R[rn] directly to generate
correct code when rn = 15.

Signed-off-by: Aurelien Jarno <>

747a651e 10/18/2009 12:52 am Filip Navara

target-arm: remove cpu_T for ARM once and for all

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

a6445c52 10/18/2009 12:52 am Filip Navara

target-arm: convert gen_lookup_tb not to use cpu_T

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

19457615 10/18/2009 12:52 am Filip Navara

target-arm: convert NEON VZIP/VUZP/VTRN helper functions to pure TCG

The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16
helpers used fixed registers to return values. This patch replaces that with
TCG code, so T0/T1 is no longer directly used by the helper functions....

15bb4eac 10/18/2009 12:52 am Filip Navara

target-arm: fix TANDC and TORC instructions

Uninitialized register was used instead of proper TCG variable.

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

396e467c 10/18/2009 12:52 am Filip Navara

target-arm: replace thumb usage of cpu_T registers by proper register allocations

The goal is eventually to get rid of all cpu_T register usage and to use
just short-lived tmp/tmp2 registers. This patch converts all the places where
cpu_T was used in the Thumb code and replaces it with explicit TCG register...

3174f8e9 10/18/2009 12:52 am Filip Navara

target-arm: convert rest of disas_arm_insn / disas_thumb2_insn not to use cpu_T

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

dd8fbd78 10/18/2009 12:52 am Filip Navara

target-arm: convert disas_neon_data_insn and helpers not to use cpu_T

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

1b2b1e54 10/18/2009 12:52 am Filip Navara

target-arm: convert disas_neon_ls_insn not to use cpu_T

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

3a554c0f 10/18/2009 12:52 am Filip Navara

target-arm: convert disas_dsp_insn not use cpu_T

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

da6b5335 10/18/2009 12:52 am Filip Navara

target-arm: convert disas_iwmmxt_insn not to use cpu_T

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

312eea9f 10/18/2009 12:52 am Filip Navara

target-arm: convert VFP not to use cpu_T

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

155c3eac 10/18/2009 12:52 am Filip Navara

target-arm: use tcg_global_mem_new_i32 to allocate registers

Currently each read/write of ARM register involves a LD/ST TCG operation. This
patch uses TCG memory-backed registers to represent the ARM register set. With
memory-backed registers the LD/ST operations are transparently generated by TCG...

12edd4f2 10/18/2009 12:52 am Filip Navara

target-arm: get rid of temporary variable cache

The temporary variable cache in no longer need since tcg_temp_free was introduced.

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

288eebe5 10/18/2009 12:52 am Filip Navara

target-arm: remove useless line that sets register that is never used again

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

217aff9c 10/18/2009 12:52 am Filip Navara

target-arm: remove unused gen_movl_T2_reg function

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

c67b6b71 10/18/2009 12:52 am Filip Navara

target-arm: fix SRS/RFE instructions

The encoding of 'IA' and 'DB' conditions was swapped.
SRS instruction must store banked SPSR instead of CPSR at the specific address.
Missing 'return' statement at the end of RFE handling.
Fixed write-back code to reference correct registers....

2fbac54b 10/18/2009 12:52 am Filip Navara

target-arm: get rid of gen_set_psr_T0 and replace it by gen_set_psr/gen_set_psr_im

Signed-off-by: Filip Navara <>
Signed-off-by: Aurelien Jarno <>

72cf2d4f 09/12/2009 10:36 am Blue Swirl

Fix sys-queue.h conflict for good

Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...

8167ee88 07/16/2009 11:47 pm Blue Swirl

Update to a hopefully more future proof FSF address

Signed-off-by: Blue Swirl <>

024589f1 06/24/2009 05:09 pm Filip Navara

Remove unused gen_bx_T0 function.

Signed-off-by: Filip Navara <>
Signed-off-by: Anthony Liguori <>

21aeb343 05/15/2009 05:18 am Juha Riihimäki

fix ARMv7 data processing instructions

ARMv7 defines a new behavior for ARM data processing instructions
compared to earlier architecture revisions; when the destination
register is R15, a Branch and Exchange operation is executed rather
than a simple Branch to the target address. This patch corrects the...

e9bb4aa9 05/15/2009 04:48 am Juha Riihimäki

fix ARMv7 data processing instructions

Modernize parts of target-arm/translate.c in preparation for the
modifications in the subsequent patch in this patch set. This is done
in order to avoid writing new code to target-arm/translate.c that
would use deprecated methods and/or variables....

1b530a6d 04/05/2009 11:08 pm aurel32

Add new command line option -singlestep for tcg single stepping.

This replaces a compile time option for some targets and adds
this feature to targets which did not have a compile time option.

Add monitor command to enable or disable single step mode.

Modify monitor command "info status" to display single step mode....

cbbccffc 03/17/2009 02:19 pm pbrook

Fix ARM quadword VDUP (core register).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6857 c046a42c-6fe2-441c-8c8c-71466251a162

66896cb8 03/13/2009 11:34 am aurel32

tcg: rename bswap_i32/i64 functions

Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162

8fec2b8c 01/16/2009 12:36 am aliguori

global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)

These are references to 'loglevel' that aren't on a simple 'if (loglevel &
X) qemu_log()' statement.

Signed-off-by: Eduardo Habkost <>
Signed-off-by: Anthony Liguori <>...