Revision f8bf8606
| b/target-arm/cpu.h | ||
|---|---|---|
| 126 | 126 |
uint32_t c6_region[8]; /* MPU base/size registers. */ |
| 127 | 127 |
uint32_t c6_insn; /* Fault address registers. */ |
| 128 | 128 |
uint32_t c6_data; |
| 129 |
uint32_t c7_par; /* Translation result. */ |
|
| 129 | 130 |
uint32_t c9_insn; /* Cache lockdown registers. */ |
| 130 | 131 |
uint32_t c9_data; |
| 131 | 132 |
uint32_t c13_fcse; /* FCSE PID. */ |
| ... | ... | |
| 428 | 429 |
#define cpu_signal_handler cpu_arm_signal_handler |
| 429 | 430 |
#define cpu_list arm_cpu_list |
| 430 | 431 |
|
| 431 |
#define CPU_SAVE_VERSION 2
|
|
| 432 |
#define CPU_SAVE_VERSION 3
|
|
| 432 | 433 |
|
| 433 | 434 |
/* MMU modes definitions */ |
| 434 | 435 |
#define MMU_MODE0_SUFFIX _kernel |
| b/target-arm/helper.c | ||
|---|---|---|
| 1456 | 1456 |
case 7: /* Cache control. */ |
| 1457 | 1457 |
env->cp15.c15_i_max = 0x000; |
| 1458 | 1458 |
env->cp15.c15_i_min = 0xff0; |
| 1459 |
/* No cache, so nothing to do. */ |
|
| 1460 |
/* ??? MPCore has VA to PA translation functions. */ |
|
| 1459 |
if (op1 != 0) {
|
|
| 1460 |
goto bad_reg; |
|
| 1461 |
} |
|
| 1462 |
/* No cache, so nothing to do except VA->PA translations. */ |
|
| 1463 |
if (arm_feature(env, ARM_FEATURE_V6K)) {
|
|
| 1464 |
switch (crm) {
|
|
| 1465 |
case 4: |
|
| 1466 |
if (arm_feature(env, ARM_FEATURE_V7)) {
|
|
| 1467 |
env->cp15.c7_par = val & 0xfffff6ff; |
|
| 1468 |
} else {
|
|
| 1469 |
env->cp15.c7_par = val & 0xfffff1ff; |
|
| 1470 |
} |
|
| 1471 |
break; |
|
| 1472 |
case 8: {
|
|
| 1473 |
uint32_t phys_addr; |
|
| 1474 |
target_ulong page_size; |
|
| 1475 |
int prot; |
|
| 1476 |
int ret, is_user = op2 & 2; |
|
| 1477 |
int access_type = op2 & 1; |
|
| 1478 |
|
|
| 1479 |
if (op2 & 4) {
|
|
| 1480 |
/* Other states are only available with TrustZone */ |
|
| 1481 |
goto bad_reg; |
|
| 1482 |
} |
|
| 1483 |
ret = get_phys_addr(env, val, access_type, is_user, |
|
| 1484 |
&phys_addr, &prot, &page_size); |
|
| 1485 |
if (ret == 0) {
|
|
| 1486 |
/* We do not set any attribute bits in the PAR */ |
|
| 1487 |
if (page_size == (1 << 24) |
|
| 1488 |
&& arm_feature(env, ARM_FEATURE_V7)) {
|
|
| 1489 |
env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1; |
|
| 1490 |
} else {
|
|
| 1491 |
env->cp15.c7_par = phys_addr & 0xfffff000; |
|
| 1492 |
} |
|
| 1493 |
} else {
|
|
| 1494 |
env->cp15.c7_par = ((ret & (10 << 1)) >> 5) | |
|
| 1495 |
((ret & (12 << 1)) >> 6) | |
|
| 1496 |
((ret & 0xf) << 1) | 1; |
|
| 1497 |
} |
|
| 1498 |
break; |
|
| 1499 |
} |
|
| 1500 |
} |
|
| 1501 |
} |
|
| 1461 | 1502 |
break; |
| 1462 | 1503 |
case 8: /* MMU TLB control. */ |
| 1463 | 1504 |
switch (op2) {
|
| ... | ... | |
| 1789 | 1830 |
} |
| 1790 | 1831 |
} |
| 1791 | 1832 |
case 7: /* Cache control. */ |
| 1833 |
if (crm == 4 && op1 == 0 && op2 == 0) {
|
|
| 1834 |
return env->cp15.c7_par; |
|
| 1835 |
} |
|
| 1792 | 1836 |
/* FIXME: Should only clear Z flag if destination is r15. */ |
| 1793 | 1837 |
env->ZF = 0; |
| 1794 | 1838 |
return 0; |
| b/target-arm/machine.c | ||
|---|---|---|
| 41 | 41 |
} |
| 42 | 42 |
qemu_put_be32(f, env->cp15.c6_insn); |
| 43 | 43 |
qemu_put_be32(f, env->cp15.c6_data); |
| 44 |
qemu_put_be32(f, env->cp15.c7_par); |
|
| 44 | 45 |
qemu_put_be32(f, env->cp15.c9_insn); |
| 45 | 46 |
qemu_put_be32(f, env->cp15.c9_data); |
| 46 | 47 |
qemu_put_be32(f, env->cp15.c13_fcse); |
| ... | ... | |
| 148 | 149 |
} |
| 149 | 150 |
env->cp15.c6_insn = qemu_get_be32(f); |
| 150 | 151 |
env->cp15.c6_data = qemu_get_be32(f); |
| 152 |
env->cp15.c7_par = qemu_get_be32(f); |
|
| 151 | 153 |
env->cp15.c9_insn = qemu_get_be32(f); |
| 152 | 154 |
env->cp15.c9_data = qemu_get_be32(f); |
| 153 | 155 |
env->cp15.c13_fcse = qemu_get_be32(f); |
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