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/*
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 * ARM virtual CPU header
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#ifndef CPU_ARM_H
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#define CPU_ARM_H
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#define TARGET_LONG_BITS 32
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#define ELF_MACHINE        EM_ARM
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#define CPUState struct CPUARMState
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#include "config.h"
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#include "qemu-common.h"
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#include "cpu-defs.h"
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#include "softfloat.h"
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#define TARGET_HAS_ICE 1
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#define EXCP_UDEF            1   /* undefined instruction */
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#define EXCP_SWI             2   /* software interrupt */
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#define EXCP_PREFETCH_ABORT  3
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#define EXCP_DATA_ABORT      4
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#define EXCP_IRQ             5
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#define EXCP_FIQ             6
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#define EXCP_BKPT            7
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#define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
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#define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
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#define EXCP_STREX          10
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#define ARMV7M_EXCP_RESET   1
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#define ARMV7M_EXCP_NMI     2
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#define ARMV7M_EXCP_HARD    3
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#define ARMV7M_EXCP_MEM     4
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#define ARMV7M_EXCP_BUS     5
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#define ARMV7M_EXCP_USAGE   6
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#define ARMV7M_EXCP_SVC     11
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#define ARMV7M_EXCP_DEBUG   12
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#define ARMV7M_EXCP_PENDSV  14
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#define ARMV7M_EXCP_SYSTICK 15
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typedef void ARMWriteCPFunc(void *opaque, int cp_info,
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                            int srcreg, int operand, uint32_t value);
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typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
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                               int dstreg, int operand);
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struct arm_boot_info;
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#define NB_MMU_MODES 2
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/* We currently assume float and double are IEEE single and double
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   precision respectively.
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   Doing runtime conversions is tricky because VFP registers may contain
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   integer values (eg. as the result of a FTOSI instruction).
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   s<2n> maps to the least significant half of d<n>
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   s<2n+1> maps to the most significant half of d<n>
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 */
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typedef struct CPUARMState {
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    /* Regs for current mode.  */
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    uint32_t regs[16];
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    /* Frequently accessed CPSR bits are stored separately for efficiently.
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       This contains all the other bits.  Use cpsr_{read,write} to access
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       the whole CPSR.  */
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    uint32_t uncached_cpsr;
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    uint32_t spsr;
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    /* Banked registers.  */
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    uint32_t banked_spsr[6];
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    uint32_t banked_r13[6];
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    uint32_t banked_r14[6];
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    /* These hold r8-r12.  */
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    uint32_t usr_regs[5];
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    uint32_t fiq_regs[5];
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    /* cpsr flag cache for faster execution */
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    uint32_t CF; /* 0 or 1 */
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    uint32_t VF; /* V is the bit 31. All other bits are undefined */
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    uint32_t NF; /* N is bit 31. All other bits are undefined.  */
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    uint32_t ZF; /* Z set if zero.  */
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    uint32_t QF; /* 0 or 1 */
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    uint32_t GE; /* cpsr[19:16] */
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    uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
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    uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
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    /* System control coprocessor (cp15) */
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    struct {
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        uint32_t c0_cpuid;
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        uint32_t c0_cachetype;
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        uint32_t c0_ccsid[16]; /* Cache size.  */
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        uint32_t c0_clid; /* Cache level.  */
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        uint32_t c0_cssel; /* Cache size selection.  */
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        uint32_t c0_c1[8]; /* Feature registers.  */
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        uint32_t c0_c2[8]; /* Instruction set registers.  */
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        uint32_t c1_sys; /* System control register.  */
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        uint32_t c1_coproc; /* Coprocessor access register.  */
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        uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
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        uint32_t c2_base0; /* MMU translation table base 0.  */
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        uint32_t c2_base1; /* MMU translation table base 1.  */
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        uint32_t c2_control; /* MMU translation table base control.  */
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        uint32_t c2_mask; /* MMU translation table base selection mask.  */
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        uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
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        uint32_t c2_data; /* MPU data cachable bits.  */
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        uint32_t c2_insn; /* MPU instruction cachable bits.  */
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        uint32_t c3; /* MMU domain access control register
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                        MPU write buffer control.  */
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        uint32_t c5_insn; /* Fault status registers.  */
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        uint32_t c5_data;
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        uint32_t c6_region[8]; /* MPU base/size registers.  */
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        uint32_t c6_insn; /* Fault address registers.  */
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        uint32_t c6_data;
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        uint32_t c7_par;  /* Translation result. */
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        uint32_t c9_insn; /* Cache lockdown registers.  */
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        uint32_t c9_data;
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        uint32_t c13_fcse; /* FCSE PID.  */
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        uint32_t c13_context; /* Context ID.  */
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        uint32_t c13_tls1; /* User RW Thread register.  */
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        uint32_t c13_tls2; /* User RO Thread register.  */
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        uint32_t c13_tls3; /* Privileged Thread register.  */
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        uint32_t c15_cpar; /* XScale Coprocessor Access Register */
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        uint32_t c15_ticonfig; /* TI925T configuration byte.  */
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        uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
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        uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
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        uint32_t c15_threadid; /* TI debugger thread-ID.  */
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    } cp15;
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    struct {
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        uint32_t other_sp;
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        uint32_t vecbase;
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        uint32_t basepri;
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        uint32_t control;
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        int current_sp;
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        int exception;
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        int pending_exception;
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    } v7m;
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    /* Thumb-2 EE state.  */
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    uint32_t teecr;
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    uint32_t teehbr;
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    /* Internal CPU feature flags.  */
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    uint32_t features;
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    /* VFP coprocessor state.  */
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    struct {
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        float64 regs[32];
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        uint32_t xregs[16];
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        /* We store these fpcsr fields separately for convenience.  */
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        int vec_len;
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        int vec_stride;
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        /* scratch space when Tn are not sufficient.  */
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        uint32_t scratch[8];
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        /* fp_status is the "normal" fp status. standard_fp_status retains
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         * values corresponding to the ARM "Standard FPSCR Value", ie
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         * default-NaN, flush-to-zero, round-to-nearest and is used by
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         * any operations (generally Neon) which the architecture defines
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         * as controlled by the standard FPSCR value rather than the FPSCR.
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         *
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         * To avoid having to transfer exception bits around, we simply
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         * say that the FPSCR cumulative exception flags are the logical
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         * OR of the flags in the two fp statuses. This relies on the
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         * only thing which needs to read the exception flags being
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         * an explicit FPSCR read.
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         */
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        float_status fp_status;
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        float_status standard_fp_status;
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    } vfp;
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    uint32_t exclusive_addr;
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    uint32_t exclusive_val;
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    uint32_t exclusive_high;
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#if defined(CONFIG_USER_ONLY)
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    uint32_t exclusive_test;
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    uint32_t exclusive_info;
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#endif
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    /* iwMMXt coprocessor state.  */
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    struct {
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        uint64_t regs[16];
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        uint64_t val;
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        uint32_t cregs[16];
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    } iwmmxt;
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#if defined(CONFIG_USER_ONLY)
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    /* For usermode syscall translation.  */
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    int eabi;
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#endif
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    CPU_COMMON
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    /* These fields after the common ones so they are preserved on reset.  */
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    /* Coprocessor IO used by peripherals */
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    struct {
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        ARMReadCPFunc *cp_read;
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        ARMWriteCPFunc *cp_write;
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        void *opaque;
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    } cp[15];
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    void *nvic;
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    struct arm_boot_info *boot_info;
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} CPUARMState;
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CPUARMState *cpu_arm_init(const char *cpu_model);
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void arm_translate_init(void);
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int cpu_arm_exec(CPUARMState *s);
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void cpu_arm_close(CPUARMState *s);
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void do_interrupt(CPUARMState *);
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void switch_mode(CPUARMState *, int);
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uint32_t do_arm_semihosting(CPUARMState *env);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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   signal handlers to inform the virtual CPU of exceptions. non zero
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   is returned if the signal was handled by the virtual CPU.  */
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int cpu_arm_signal_handler(int host_signum, void *pinfo,
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                           void *puc);
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int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
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                              int mmu_idx, int is_softmuu);
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#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
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static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
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{
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  env->cp15.c13_tls2 = newtls;
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}
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#define CPSR_M (0x1f)
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#define CPSR_T (1 << 5)
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#define CPSR_F (1 << 6)
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#define CPSR_I (1 << 7)
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#define CPSR_A (1 << 8)
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#define CPSR_E (1 << 9)
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#define CPSR_IT_2_7 (0xfc00)
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#define CPSR_GE (0xf << 16)
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#define CPSR_RESERVED (0xf << 20)
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#define CPSR_J (1 << 24)
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#define CPSR_IT_0_1 (3 << 25)
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#define CPSR_Q (1 << 27)
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#define CPSR_V (1 << 28)
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#define CPSR_C (1 << 29)
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#define CPSR_Z (1 << 30)
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#define CPSR_N (1 << 31)
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#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
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#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
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#define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
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/* Bits writable in user mode.  */
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#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
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/* Execution state bits.  MRS read as zero, MSR writes ignored.  */
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#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
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/* Return the current CPSR value.  */
271
uint32_t cpsr_read(CPUARMState *env);
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/* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
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void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
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/* Return the current xPSR value.  */
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static inline uint32_t xpsr_read(CPUARMState *env)
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{
278
    int ZF;
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    ZF = (env->ZF == 0);
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    return (env->NF & 0x80000000) | (ZF << 30)
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        | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
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        | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
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        | ((env->condexec_bits & 0xfc) << 8)
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        | env->v7m.exception;
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}
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/* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
288
static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
289
{
290
    if (mask & CPSR_NZCV) {
291
        env->ZF = (~val) & CPSR_Z;
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        env->NF = val;
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        env->CF = (val >> 29) & 1;
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        env->VF = (val << 3) & 0x80000000;
295
    }
296
    if (mask & CPSR_Q)
297
        env->QF = ((val & CPSR_Q) != 0);
298
    if (mask & (1 << 24))
299
        env->thumb = ((val & (1 << 24)) != 0);
300
    if (mask & CPSR_IT_0_1) {
301
        env->condexec_bits &= ~3;
302
        env->condexec_bits |= (val >> 25) & 3;
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    }
304
    if (mask & CPSR_IT_2_7) {
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        env->condexec_bits &= 3;
306
        env->condexec_bits |= (val >> 8) & 0xfc;
307
    }
308
    if (mask & 0x1ff) {
309
        env->v7m.exception = val & 0x1ff;
310
    }
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}
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/* Return the current FPSCR value.  */
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uint32_t vfp_get_fpscr(CPUARMState *env);
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void vfp_set_fpscr(CPUARMState *env, uint32_t val);
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enum arm_cpu_mode {
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  ARM_CPU_MODE_USR = 0x10,
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  ARM_CPU_MODE_FIQ = 0x11,
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  ARM_CPU_MODE_IRQ = 0x12,
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  ARM_CPU_MODE_SVC = 0x13,
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  ARM_CPU_MODE_ABT = 0x17,
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  ARM_CPU_MODE_UND = 0x1b,
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  ARM_CPU_MODE_SYS = 0x1f
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};
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/* VFP system registers.  */
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#define ARM_VFP_FPSID   0
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#define ARM_VFP_FPSCR   1
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#define ARM_VFP_MVFR1   6
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#define ARM_VFP_MVFR0   7
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#define ARM_VFP_FPEXC   8
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#define ARM_VFP_FPINST  9
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#define ARM_VFP_FPINST2 10
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/* iwMMXt coprocessor control registers.  */
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#define ARM_IWMMXT_wCID                0
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#define ARM_IWMMXT_wCon                1
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#define ARM_IWMMXT_wCSSF        2
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#define ARM_IWMMXT_wCASF        3
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#define ARM_IWMMXT_wCGR0        8
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#define ARM_IWMMXT_wCGR1        9
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#define ARM_IWMMXT_wCGR2        10
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#define ARM_IWMMXT_wCGR3        11
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346
enum arm_features {
347
    ARM_FEATURE_VFP,
348
    ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
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    ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
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    ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
351
    ARM_FEATURE_V6,
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    ARM_FEATURE_V6K,
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    ARM_FEATURE_V7,
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    ARM_FEATURE_THUMB2,
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    ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
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    ARM_FEATURE_VFP3,
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    ARM_FEATURE_VFP_FP16,
358
    ARM_FEATURE_NEON,
359
    ARM_FEATURE_DIV,
360
    ARM_FEATURE_M, /* Microcontroller profile.  */
361
    ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
362
    ARM_FEATURE_THUMB2EE,
363
    ARM_FEATURE_V7MP    /* v7 Multiprocessing Extensions */
364
};
365

    
366
static inline int arm_feature(CPUARMState *env, int feature)
367
{
368
    return (env->features & (1u << feature)) != 0;
369
}
370

    
371
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
372

    
373
/* Interface between CPU and Interrupt controller.  */
374
void armv7m_nvic_set_pending(void *opaque, int irq);
375
int armv7m_nvic_acknowledge_irq(void *opaque);
376
void armv7m_nvic_complete_irq(void *opaque, int irq);
377

    
378
void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
379
                       ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
380
                       void *opaque);
381

    
382
/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
383
   Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
384
   conventional cores (ie. Application or Realtime profile).  */
385

    
386
#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
387
#define ARM_CPUID(env) (env->cp15.c0_cpuid)
388

    
389
#define ARM_CPUID_ARM1026     0x4106a262
390
#define ARM_CPUID_ARM926      0x41069265
391
#define ARM_CPUID_ARM946      0x41059461
392
#define ARM_CPUID_TI915T      0x54029152
393
#define ARM_CPUID_TI925T      0x54029252
394
#define ARM_CPUID_PXA250      0x69052100
395
#define ARM_CPUID_PXA255      0x69052d00
396
#define ARM_CPUID_PXA260      0x69052903
397
#define ARM_CPUID_PXA261      0x69052d05
398
#define ARM_CPUID_PXA262      0x69052d06
399
#define ARM_CPUID_PXA270      0x69054110
400
#define ARM_CPUID_PXA270_A0   0x69054110
401
#define ARM_CPUID_PXA270_A1   0x69054111
402
#define ARM_CPUID_PXA270_B0   0x69054112
403
#define ARM_CPUID_PXA270_B1   0x69054113
404
#define ARM_CPUID_PXA270_C0   0x69054114
405
#define ARM_CPUID_PXA270_C5   0x69054117
406
#define ARM_CPUID_ARM1136     0x4117b363
407
#define ARM_CPUID_ARM1136_R2  0x4107b362
408
#define ARM_CPUID_ARM11MPCORE 0x410fb022
409
#define ARM_CPUID_CORTEXA8    0x410fc080
410
#define ARM_CPUID_CORTEXA9    0x410fc090
411
#define ARM_CPUID_CORTEXM3    0x410fc231
412
#define ARM_CPUID_ANY         0xffffffff
413

    
414
#if defined(CONFIG_USER_ONLY)
415
#define TARGET_PAGE_BITS 12
416
#else
417
/* The ARM MMU allows 1k pages.  */
418
/* ??? Linux doesn't actually use these, and they're deprecated in recent
419
   architecture revisions.  Maybe a configure option to disable them.  */
420
#define TARGET_PAGE_BITS 10
421
#endif
422

    
423
#define TARGET_PHYS_ADDR_SPACE_BITS 32
424
#define TARGET_VIRT_ADDR_SPACE_BITS 32
425

    
426
#define cpu_init cpu_arm_init
427
#define cpu_exec cpu_arm_exec
428
#define cpu_gen_code cpu_arm_gen_code
429
#define cpu_signal_handler cpu_arm_signal_handler
430
#define cpu_list arm_cpu_list
431

    
432
#define CPU_SAVE_VERSION 3
433

    
434
/* MMU modes definitions */
435
#define MMU_MODE0_SUFFIX _kernel
436
#define MMU_MODE1_SUFFIX _user
437
#define MMU_USER_IDX 1
438
static inline int cpu_mmu_index (CPUState *env)
439
{
440
    return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
441
}
442

    
443
#if defined(CONFIG_USER_ONLY)
444
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
445
{
446
    if (newsp)
447
        env->regs[13] = newsp;
448
    env->regs[0] = 0;
449
}
450
#endif
451

    
452
#include "cpu-all.h"
453

    
454
/* Bit usage in the TB flags field: */
455
#define ARM_TBFLAG_THUMB_SHIFT      0
456
#define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
457
#define ARM_TBFLAG_VECLEN_SHIFT     1
458
#define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
459
#define ARM_TBFLAG_VECSTRIDE_SHIFT  4
460
#define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
461
#define ARM_TBFLAG_PRIV_SHIFT       6
462
#define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
463
#define ARM_TBFLAG_VFPEN_SHIFT      7
464
#define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
465
#define ARM_TBFLAG_CONDEXEC_SHIFT   8
466
#define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
467
/* Bits 31..16 are currently unused. */
468

    
469
/* some convenience accessor macros */
470
#define ARM_TBFLAG_THUMB(F) \
471
    (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
472
#define ARM_TBFLAG_VECLEN(F) \
473
    (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
474
#define ARM_TBFLAG_VECSTRIDE(F) \
475
    (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
476
#define ARM_TBFLAG_PRIV(F) \
477
    (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
478
#define ARM_TBFLAG_VFPEN(F) \
479
    (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
480
#define ARM_TBFLAG_CONDEXEC(F) \
481
    (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
482

    
483
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
484
                                        target_ulong *cs_base, int *flags)
485
{
486
    int privmode;
487
    *pc = env->regs[15];
488
    *cs_base = 0;
489
    *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
490
        | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
491
        | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
492
        | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT);
493
    if (arm_feature(env, ARM_FEATURE_M)) {
494
        privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
495
    } else {
496
        privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
497
    }
498
    if (privmode) {
499
        *flags |= ARM_TBFLAG_PRIV_MASK;
500
    }
501
    if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
502
        *flags |= ARM_TBFLAG_VFPEN_MASK;
503
    }
504
}
505

    
506
#endif