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1 | 4c9649a9 | j_mayer | /*
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2 | 4c9649a9 | j_mayer | * Alpha emulation cpu definitions for qemu.
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3 | 5fafdf24 | ths | *
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4 | 4c9649a9 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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5 | 4c9649a9 | j_mayer | *
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6 | 4c9649a9 | j_mayer | * This library is free software; you can redistribute it and/or
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7 | 4c9649a9 | j_mayer | * modify it under the terms of the GNU Lesser General Public
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8 | 4c9649a9 | j_mayer | * License as published by the Free Software Foundation; either
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9 | 4c9649a9 | j_mayer | * version 2 of the License, or (at your option) any later version.
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10 | 4c9649a9 | j_mayer | *
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11 | 4c9649a9 | j_mayer | * This library is distributed in the hope that it will be useful,
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12 | 4c9649a9 | j_mayer | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 4c9649a9 | j_mayer | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 4c9649a9 | j_mayer | * Lesser General Public License for more details.
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15 | 4c9649a9 | j_mayer | *
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16 | 4c9649a9 | j_mayer | * You should have received a copy of the GNU Lesser General Public
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17 | 4c9649a9 | j_mayer | * License along with this library; if not, write to the Free Software
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18 | fad6cb1a | aurel32 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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19 | 4c9649a9 | j_mayer | */
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20 | 4c9649a9 | j_mayer | |
21 | 4c9649a9 | j_mayer | #if !defined (__CPU_ALPHA_H__)
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22 | 4c9649a9 | j_mayer | #define __CPU_ALPHA_H__
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23 | 4c9649a9 | j_mayer | |
24 | 4c9649a9 | j_mayer | #include "config.h" |
25 | 4c9649a9 | j_mayer | |
26 | 4c9649a9 | j_mayer | #define TARGET_LONG_BITS 64 |
27 | 4c9649a9 | j_mayer | |
28 | c2764719 | pbrook | #define CPUState struct CPUAlphaState |
29 | c2764719 | pbrook | |
30 | 4c9649a9 | j_mayer | #include "cpu-defs.h" |
31 | 4c9649a9 | j_mayer | |
32 | 4c9649a9 | j_mayer | #include <setjmp.h> |
33 | 4c9649a9 | j_mayer | |
34 | 4c9649a9 | j_mayer | #include "softfloat.h" |
35 | 4c9649a9 | j_mayer | |
36 | 4c9649a9 | j_mayer | #define TARGET_HAS_ICE 1 |
37 | 4c9649a9 | j_mayer | |
38 | f071b4d3 | j_mayer | #define ELF_MACHINE EM_ALPHA
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39 | 4c9649a9 | j_mayer | |
40 | 4c9649a9 | j_mayer | #define ICACHE_LINE_SIZE 32 |
41 | 4c9649a9 | j_mayer | #define DCACHE_LINE_SIZE 32 |
42 | 4c9649a9 | j_mayer | |
43 | 4c9649a9 | j_mayer | #define TARGET_PAGE_BITS 12 |
44 | 4c9649a9 | j_mayer | |
45 | 4c9649a9 | j_mayer | #define VA_BITS 43 |
46 | 4c9649a9 | j_mayer | |
47 | 4c9649a9 | j_mayer | /* Alpha major type */
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48 | 4c9649a9 | j_mayer | enum {
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49 | 4c9649a9 | j_mayer | ALPHA_EV3 = 1,
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50 | 4c9649a9 | j_mayer | ALPHA_EV4 = 2,
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51 | 4c9649a9 | j_mayer | ALPHA_SIM = 3,
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52 | 4c9649a9 | j_mayer | ALPHA_LCA = 4,
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53 | 4c9649a9 | j_mayer | ALPHA_EV5 = 5, /* 21164 */ |
54 | 4c9649a9 | j_mayer | ALPHA_EV45 = 6, /* 21064A */ |
55 | 4c9649a9 | j_mayer | ALPHA_EV56 = 7, /* 21164A */ |
56 | 4c9649a9 | j_mayer | }; |
57 | 4c9649a9 | j_mayer | |
58 | 4c9649a9 | j_mayer | /* EV4 minor type */
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59 | 4c9649a9 | j_mayer | enum {
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60 | 4c9649a9 | j_mayer | ALPHA_EV4_2 = 0,
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61 | 4c9649a9 | j_mayer | ALPHA_EV4_3 = 1,
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62 | 4c9649a9 | j_mayer | }; |
63 | 4c9649a9 | j_mayer | |
64 | 4c9649a9 | j_mayer | /* LCA minor type */
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65 | 4c9649a9 | j_mayer | enum {
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66 | 4c9649a9 | j_mayer | ALPHA_LCA_1 = 1, /* 21066 */ |
67 | 4c9649a9 | j_mayer | ALPHA_LCA_2 = 2, /* 20166 */ |
68 | 4c9649a9 | j_mayer | ALPHA_LCA_3 = 3, /* 21068 */ |
69 | 4c9649a9 | j_mayer | ALPHA_LCA_4 = 4, /* 21068 */ |
70 | 4c9649a9 | j_mayer | ALPHA_LCA_5 = 5, /* 21066A */ |
71 | 4c9649a9 | j_mayer | ALPHA_LCA_6 = 6, /* 21068A */ |
72 | 4c9649a9 | j_mayer | }; |
73 | 4c9649a9 | j_mayer | |
74 | 4c9649a9 | j_mayer | /* EV5 minor type */
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75 | 4c9649a9 | j_mayer | enum {
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76 | 4c9649a9 | j_mayer | ALPHA_EV5_1 = 1, /* Rev BA, CA */ |
77 | 4c9649a9 | j_mayer | ALPHA_EV5_2 = 2, /* Rev DA, EA */ |
78 | 4c9649a9 | j_mayer | ALPHA_EV5_3 = 3, /* Pass 3 */ |
79 | 4c9649a9 | j_mayer | ALPHA_EV5_4 = 4, /* Pass 3.2 */ |
80 | 4c9649a9 | j_mayer | ALPHA_EV5_5 = 5, /* Pass 4 */ |
81 | 4c9649a9 | j_mayer | }; |
82 | 4c9649a9 | j_mayer | |
83 | 4c9649a9 | j_mayer | /* EV45 minor type */
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84 | 4c9649a9 | j_mayer | enum {
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85 | 4c9649a9 | j_mayer | ALPHA_EV45_1 = 1, /* Pass 1 */ |
86 | 4c9649a9 | j_mayer | ALPHA_EV45_2 = 2, /* Pass 1.1 */ |
87 | 4c9649a9 | j_mayer | ALPHA_EV45_3 = 3, /* Pass 2 */ |
88 | 4c9649a9 | j_mayer | }; |
89 | 4c9649a9 | j_mayer | |
90 | 4c9649a9 | j_mayer | /* EV56 minor type */
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91 | 4c9649a9 | j_mayer | enum {
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92 | 4c9649a9 | j_mayer | ALPHA_EV56_1 = 1, /* Pass 1 */ |
93 | 4c9649a9 | j_mayer | ALPHA_EV56_2 = 2, /* Pass 2 */ |
94 | 4c9649a9 | j_mayer | }; |
95 | 4c9649a9 | j_mayer | |
96 | 4c9649a9 | j_mayer | enum {
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97 | 4c9649a9 | j_mayer | IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */ |
98 | 4c9649a9 | j_mayer | IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */ |
99 | 4c9649a9 | j_mayer | IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */ |
100 | 4c9649a9 | j_mayer | IMPLVER_21364 = 3, /* EV7 & EV79 */ |
101 | 4c9649a9 | j_mayer | }; |
102 | 4c9649a9 | j_mayer | |
103 | 4c9649a9 | j_mayer | enum {
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104 | 4c9649a9 | j_mayer | AMASK_BWX = 0x00000001,
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105 | 4c9649a9 | j_mayer | AMASK_FIX = 0x00000002,
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106 | 4c9649a9 | j_mayer | AMASK_CIX = 0x00000004,
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107 | 4c9649a9 | j_mayer | AMASK_MVI = 0x00000100,
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108 | 4c9649a9 | j_mayer | AMASK_TRAP = 0x00000200,
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109 | 4c9649a9 | j_mayer | AMASK_PREFETCH = 0x00001000,
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110 | 4c9649a9 | j_mayer | }; |
111 | 4c9649a9 | j_mayer | |
112 | 4c9649a9 | j_mayer | enum {
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113 | 4c9649a9 | j_mayer | VAX_ROUND_NORMAL = 0,
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114 | 4c9649a9 | j_mayer | VAX_ROUND_CHOPPED, |
115 | 4c9649a9 | j_mayer | }; |
116 | 4c9649a9 | j_mayer | |
117 | 4c9649a9 | j_mayer | enum {
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118 | 4c9649a9 | j_mayer | IEEE_ROUND_NORMAL = 0,
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119 | 4c9649a9 | j_mayer | IEEE_ROUND_DYNAMIC, |
120 | 4c9649a9 | j_mayer | IEEE_ROUND_PLUS, |
121 | 4c9649a9 | j_mayer | IEEE_ROUND_MINUS, |
122 | 4c9649a9 | j_mayer | IEEE_ROUND_CHOPPED, |
123 | 4c9649a9 | j_mayer | }; |
124 | 4c9649a9 | j_mayer | |
125 | 4c9649a9 | j_mayer | /* IEEE floating-point operations encoding */
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126 | 4c9649a9 | j_mayer | /* Trap mode */
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127 | 4c9649a9 | j_mayer | enum {
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128 | 4c9649a9 | j_mayer | FP_TRAP_I = 0x0,
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129 | 4c9649a9 | j_mayer | FP_TRAP_U = 0x1,
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130 | 4c9649a9 | j_mayer | FP_TRAP_S = 0x4,
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131 | 4c9649a9 | j_mayer | FP_TRAP_SU = 0x5,
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132 | 4c9649a9 | j_mayer | FP_TRAP_SUI = 0x7,
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133 | 4c9649a9 | j_mayer | }; |
134 | 4c9649a9 | j_mayer | |
135 | 4c9649a9 | j_mayer | /* Rounding mode */
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136 | 4c9649a9 | j_mayer | enum {
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137 | 4c9649a9 | j_mayer | FP_ROUND_CHOPPED = 0x0,
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138 | 4c9649a9 | j_mayer | FP_ROUND_MINUS = 0x1,
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139 | 4c9649a9 | j_mayer | FP_ROUND_NORMAL = 0x2,
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140 | 4c9649a9 | j_mayer | FP_ROUND_DYNAMIC = 0x3,
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141 | 4c9649a9 | j_mayer | }; |
142 | 4c9649a9 | j_mayer | |
143 | 4c9649a9 | j_mayer | /* Internal processor registers */
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144 | 4c9649a9 | j_mayer | /* XXX: TOFIX: most of those registers are implementation dependant */
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145 | 4c9649a9 | j_mayer | enum {
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146 | 4c9649a9 | j_mayer | /* Ebox IPRs */
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147 | f8cc8534 | aurel32 | IPR_CC = 0xC0, /* 21264 */ |
148 | f8cc8534 | aurel32 | IPR_CC_CTL = 0xC1, /* 21264 */ |
149 | f8cc8534 | aurel32 | #define IPR_CC_CTL_ENA_SHIFT 32 |
150 | f8cc8534 | aurel32 | #define IPR_CC_CTL_COUNTER_MASK 0xfffffff0UL |
151 | f8cc8534 | aurel32 | IPR_VA = 0xC2, /* 21264 */ |
152 | f8cc8534 | aurel32 | IPR_VA_CTL = 0xC4, /* 21264 */ |
153 | f8cc8534 | aurel32 | #define IPR_VA_CTL_VA_48_SHIFT 1 |
154 | f8cc8534 | aurel32 | #define IPR_VA_CTL_VPTB_SHIFT 30 |
155 | f8cc8534 | aurel32 | IPR_VA_FORM = 0xC3, /* 21264 */ |
156 | 4c9649a9 | j_mayer | /* Ibox IPRs */
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157 | f8cc8534 | aurel32 | IPR_ITB_TAG = 0x00, /* 21264 */ |
158 | f8cc8534 | aurel32 | IPR_ITB_PTE = 0x01, /* 21264 */ |
159 | f8cc8534 | aurel32 | IPR_ITB_IAP = 0x02,
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160 | f8cc8534 | aurel32 | IPR_ITB_IA = 0x03, /* 21264 */ |
161 | f8cc8534 | aurel32 | IPR_ITB_IS = 0x04,
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162 | 4c9649a9 | j_mayer | IPR_PMPC = 0x05,
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163 | f8cc8534 | aurel32 | IPR_EXC_ADDR = 0x06, /* 21264 */ |
164 | f8cc8534 | aurel32 | IPR_IVA_FORM = 0x07, /* 21264 */ |
165 | f8cc8534 | aurel32 | IPR_CM = 0x09, /* 21264 */ |
166 | f8cc8534 | aurel32 | #define IPR_CM_SHIFT 3 |
167 | f8cc8534 | aurel32 | #define IPR_CM_MASK (3ULL << IPR_CM_SHIFT) /* 21264 */ |
168 | f8cc8534 | aurel32 | IPR_IER = 0x0A, /* 21264 */ |
169 | f8cc8534 | aurel32 | #define IPR_IER_MASK 0x0000007fffffe000ULL |
170 | f8cc8534 | aurel32 | IPR_IER_CM = 0x0B, /* 21264: = CM | IER */ |
171 | f8cc8534 | aurel32 | IPR_SIRR = 0x0C, /* 21264 */ |
172 | f8cc8534 | aurel32 | #define IPR_SIRR_SHIFT 14 |
173 | f8cc8534 | aurel32 | #define IPR_SIRR_MASK 0x7fff |
174 | f8cc8534 | aurel32 | IPR_ISUM = 0x0D, /* 21264 */ |
175 | f8cc8534 | aurel32 | IPR_HW_INT_CLR = 0x0E, /* 21264 */ |
176 | 4c9649a9 | j_mayer | IPR_EXC_SUM = 0x0F,
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177 | 4c9649a9 | j_mayer | IPR_PAL_BASE = 0x10,
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178 | 4c9649a9 | j_mayer | IPR_I_CTL = 0x11,
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179 | f8cc8534 | aurel32 | #define IPR_I_CTL_CHIP_ID_SHIFT 24 /* 21264 */ |
180 | f8cc8534 | aurel32 | #define IPR_I_CTL_BIST_FAIL (1 << 23) /* 21264 */ |
181 | f8cc8534 | aurel32 | #define IPR_I_CTL_IC_EN_SHIFT 2 /* 21264 */ |
182 | f8cc8534 | aurel32 | #define IPR_I_CTL_SDE1_SHIFT 7 /* 21264 */ |
183 | f8cc8534 | aurel32 | #define IPR_I_CTL_HWE_SHIFT 12 /* 21264 */ |
184 | f8cc8534 | aurel32 | #define IPR_I_CTL_VA_48_SHIFT 15 /* 21264 */ |
185 | f8cc8534 | aurel32 | #define IPR_I_CTL_SPE_SHIFT 3 /* 21264 */ |
186 | f8cc8534 | aurel32 | #define IPR_I_CTL_CALL_PAL_R23_SHIFT 20 /* 21264 */ |
187 | f8cc8534 | aurel32 | IPR_I_STAT = 0x16, /* 21264 */ |
188 | f8cc8534 | aurel32 | IPR_IC_FLUSH = 0x13, /* 21264 */ |
189 | f8cc8534 | aurel32 | IPR_IC_FLUSH_ASM = 0x12, /* 21264 */ |
190 | 4c9649a9 | j_mayer | IPR_CLR_MAP = 0x15,
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191 | 4c9649a9 | j_mayer | IPR_SLEEP = 0x17,
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192 | 4c9649a9 | j_mayer | IPR_PCTX = 0x40,
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193 | f8cc8534 | aurel32 | IPR_PCTX_ASN = 0x01, /* field */ |
194 | f8cc8534 | aurel32 | #define IPR_PCTX_ASN_SHIFT 39 |
195 | f8cc8534 | aurel32 | IPR_PCTX_ASTER = 0x02, /* field */ |
196 | f8cc8534 | aurel32 | #define IPR_PCTX_ASTER_SHIFT 5 |
197 | f8cc8534 | aurel32 | IPR_PCTX_ASTRR = 0x04, /* field */ |
198 | f8cc8534 | aurel32 | #define IPR_PCTX_ASTRR_SHIFT 9 |
199 | f8cc8534 | aurel32 | IPR_PCTX_PPCE = 0x08, /* field */ |
200 | f8cc8534 | aurel32 | #define IPR_PCTX_PPCE_SHIFT 1 |
201 | f8cc8534 | aurel32 | IPR_PCTX_FPE = 0x10, /* field */ |
202 | f8cc8534 | aurel32 | #define IPR_PCTX_FPE_SHIFT 2 |
203 | f8cc8534 | aurel32 | IPR_PCTX_ALL = 0x5f, /* all fields */ |
204 | f8cc8534 | aurel32 | IPR_PCTR_CTL = 0x14, /* 21264 */ |
205 | 4c9649a9 | j_mayer | /* Mbox IPRs */
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206 | f8cc8534 | aurel32 | IPR_DTB_TAG0 = 0x20, /* 21264 */ |
207 | f8cc8534 | aurel32 | IPR_DTB_TAG1 = 0xA0, /* 21264 */ |
208 | f8cc8534 | aurel32 | IPR_DTB_PTE0 = 0x21, /* 21264 */ |
209 | f8cc8534 | aurel32 | IPR_DTB_PTE1 = 0xA1, /* 21264 */ |
210 | 4c9649a9 | j_mayer | IPR_DTB_ALTMODE = 0xA6,
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211 | f8cc8534 | aurel32 | IPR_DTB_ALTMODE0 = 0x26, /* 21264 */ |
212 | f8cc8534 | aurel32 | #define IPR_DTB_ALTMODE_MASK 3 |
213 | 4c9649a9 | j_mayer | IPR_DTB_IAP = 0xA2,
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214 | f8cc8534 | aurel32 | IPR_DTB_IA = 0xA3, /* 21264 */ |
215 | 4c9649a9 | j_mayer | IPR_DTB_IS0 = 0x24,
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216 | 4c9649a9 | j_mayer | IPR_DTB_IS1 = 0xA4,
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217 | f8cc8534 | aurel32 | IPR_DTB_ASN0 = 0x25, /* 21264 */ |
218 | f8cc8534 | aurel32 | IPR_DTB_ASN1 = 0xA5, /* 21264 */ |
219 | f8cc8534 | aurel32 | #define IPR_DTB_ASN_SHIFT 56 |
220 | f8cc8534 | aurel32 | IPR_MM_STAT = 0x27, /* 21264 */ |
221 | f8cc8534 | aurel32 | IPR_M_CTL = 0x28, /* 21264 */ |
222 | f8cc8534 | aurel32 | #define IPR_M_CTL_SPE_SHIFT 1 |
223 | f8cc8534 | aurel32 | #define IPR_M_CTL_SPE_MASK 7 |
224 | 4c9649a9 | j_mayer | IPR_DC_CTL = 0x29,
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225 | f8cc8534 | aurel32 | IPR_DC_STAT = 0x2A, /* 21264 */ |
226 | 4c9649a9 | j_mayer | /* Cbox IPRs */
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227 | 4c9649a9 | j_mayer | IPR_C_DATA = 0x2B,
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228 | 4c9649a9 | j_mayer | IPR_C_SHIFT = 0x2C,
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229 | 4c9649a9 | j_mayer | |
230 | 4c9649a9 | j_mayer | IPR_ASN, |
231 | 4c9649a9 | j_mayer | IPR_ASTEN, |
232 | 4c9649a9 | j_mayer | IPR_ASTSR, |
233 | 4c9649a9 | j_mayer | IPR_DATFX, |
234 | 4c9649a9 | j_mayer | IPR_ESP, |
235 | 4c9649a9 | j_mayer | IPR_FEN, |
236 | 4c9649a9 | j_mayer | IPR_IPIR, |
237 | 4c9649a9 | j_mayer | IPR_IPL, |
238 | 4c9649a9 | j_mayer | IPR_KSP, |
239 | 4c9649a9 | j_mayer | IPR_MCES, |
240 | 4c9649a9 | j_mayer | IPR_PERFMON, |
241 | 4c9649a9 | j_mayer | IPR_PCBB, |
242 | 4c9649a9 | j_mayer | IPR_PRBR, |
243 | 4c9649a9 | j_mayer | IPR_PTBR, |
244 | 4c9649a9 | j_mayer | IPR_SCBB, |
245 | 4c9649a9 | j_mayer | IPR_SISR, |
246 | 4c9649a9 | j_mayer | IPR_SSP, |
247 | 4c9649a9 | j_mayer | IPR_SYSPTBR, |
248 | 4c9649a9 | j_mayer | IPR_TBCHK, |
249 | 4c9649a9 | j_mayer | IPR_TBIA, |
250 | 4c9649a9 | j_mayer | IPR_TBIAP, |
251 | 4c9649a9 | j_mayer | IPR_TBIS, |
252 | 4c9649a9 | j_mayer | IPR_TBISD, |
253 | 4c9649a9 | j_mayer | IPR_TBISI, |
254 | 4c9649a9 | j_mayer | IPR_USP, |
255 | 4c9649a9 | j_mayer | IPR_VIRBND, |
256 | 4c9649a9 | j_mayer | IPR_VPTB, |
257 | 4c9649a9 | j_mayer | IPR_WHAMI, |
258 | 4c9649a9 | j_mayer | IPR_ALT_MODE, |
259 | 4c9649a9 | j_mayer | IPR_LAST, |
260 | 4c9649a9 | j_mayer | }; |
261 | 4c9649a9 | j_mayer | |
262 | 4c9649a9 | j_mayer | typedef struct CPUAlphaState CPUAlphaState; |
263 | 4c9649a9 | j_mayer | |
264 | 4c9649a9 | j_mayer | typedef struct pal_handler_t pal_handler_t; |
265 | 4c9649a9 | j_mayer | struct pal_handler_t {
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266 | 4c9649a9 | j_mayer | /* Reset */
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267 | 4c9649a9 | j_mayer | void (*reset)(CPUAlphaState *env);
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268 | 4c9649a9 | j_mayer | /* Uncorrectable hardware error */
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269 | 4c9649a9 | j_mayer | void (*machine_check)(CPUAlphaState *env);
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270 | 4c9649a9 | j_mayer | /* Arithmetic exception */
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271 | 4c9649a9 | j_mayer | void (*arithmetic)(CPUAlphaState *env);
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272 | 4c9649a9 | j_mayer | /* Interrupt / correctable hardware error */
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273 | 4c9649a9 | j_mayer | void (*interrupt)(CPUAlphaState *env);
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274 | 4c9649a9 | j_mayer | /* Data fault */
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275 | 4c9649a9 | j_mayer | void (*dfault)(CPUAlphaState *env);
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276 | 4c9649a9 | j_mayer | /* DTB miss pal */
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277 | 4c9649a9 | j_mayer | void (*dtb_miss_pal)(CPUAlphaState *env);
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278 | 4c9649a9 | j_mayer | /* DTB miss native */
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279 | 4c9649a9 | j_mayer | void (*dtb_miss_native)(CPUAlphaState *env);
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280 | 4c9649a9 | j_mayer | /* Unaligned access */
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281 | 4c9649a9 | j_mayer | void (*unalign)(CPUAlphaState *env);
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282 | 4c9649a9 | j_mayer | /* ITB miss */
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283 | 4c9649a9 | j_mayer | void (*itb_miss)(CPUAlphaState *env);
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284 | 4c9649a9 | j_mayer | /* Instruction stream access violation */
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285 | 4c9649a9 | j_mayer | void (*itb_acv)(CPUAlphaState *env);
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286 | 4c9649a9 | j_mayer | /* Reserved or privileged opcode */
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287 | 4c9649a9 | j_mayer | void (*opcdec)(CPUAlphaState *env);
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288 | 4c9649a9 | j_mayer | /* Floating point exception */
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289 | 4c9649a9 | j_mayer | void (*fen)(CPUAlphaState *env);
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290 | 4c9649a9 | j_mayer | /* Call pal instruction */
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291 | 4c9649a9 | j_mayer | void (*call_pal)(CPUAlphaState *env, uint32_t palcode);
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292 | 4c9649a9 | j_mayer | }; |
293 | 4c9649a9 | j_mayer | |
294 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 4 |
295 | 6ebbf390 | j_mayer | |
296 | 4c9649a9 | j_mayer | struct CPUAlphaState {
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297 | 4c9649a9 | j_mayer | uint64_t ir[31];
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298 | 4c9649a9 | j_mayer | float64 fir[31];
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299 | 4c9649a9 | j_mayer | float_status fp_status; |
300 | 4c9649a9 | j_mayer | uint64_t fpcr; |
301 | 4c9649a9 | j_mayer | uint64_t pc; |
302 | 4c9649a9 | j_mayer | uint64_t lock; |
303 | 4c9649a9 | j_mayer | uint32_t pcc[2];
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304 | 4c9649a9 | j_mayer | uint64_t ipr[IPR_LAST]; |
305 | 4c9649a9 | j_mayer | uint64_t ps; |
306 | 4c9649a9 | j_mayer | uint64_t unique; |
307 | 4c9649a9 | j_mayer | int saved_mode; /* Used for HW_LD / HW_ST */ |
308 | 6ad02592 | aurel32 | int intr_flag; /* For RC and RS */ |
309 | 4c9649a9 | j_mayer | |
310 | bf9525e9 | j_mayer | #if TARGET_LONG_BITS > HOST_LONG_BITS
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311 | bf9525e9 | j_mayer | /* temporary fixed-point registers
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312 | bf9525e9 | j_mayer | * used to emulate 64 bits target on 32 bits hosts
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313 | 5fafdf24 | ths | */
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314 | 04acd307 | aurel32 | target_ulong t0, t1; |
315 | bf9525e9 | j_mayer | #endif
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316 | 4c9649a9 | j_mayer | |
317 | 4c9649a9 | j_mayer | /* Those resources are used only in Qemu core */
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318 | 4c9649a9 | j_mayer | CPU_COMMON |
319 | 4c9649a9 | j_mayer | |
320 | 4c9649a9 | j_mayer | uint32_t hflags; |
321 | 4c9649a9 | j_mayer | |
322 | 4c9649a9 | j_mayer | int error_code;
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323 | 4c9649a9 | j_mayer | |
324 | 4c9649a9 | j_mayer | uint32_t features; |
325 | 4c9649a9 | j_mayer | uint32_t amask; |
326 | 4c9649a9 | j_mayer | int implver;
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327 | 4c9649a9 | j_mayer | pal_handler_t *pal_handler; |
328 | 4c9649a9 | j_mayer | }; |
329 | 4c9649a9 | j_mayer | |
330 | 9467d44c | ths | #define cpu_init cpu_alpha_init
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331 | 9467d44c | ths | #define cpu_exec cpu_alpha_exec
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332 | 9467d44c | ths | #define cpu_gen_code cpu_alpha_gen_code
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333 | 9467d44c | ths | #define cpu_signal_handler cpu_alpha_signal_handler
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334 | 9467d44c | ths | |
335 | 6ebbf390 | j_mayer | /* MMU modes definitions */
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336 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _kernel
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337 | 6ebbf390 | j_mayer | #define MMU_MODE1_SUFFIX _executive
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338 | 6ebbf390 | j_mayer | #define MMU_MODE2_SUFFIX _supervisor
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339 | 6ebbf390 | j_mayer | #define MMU_MODE3_SUFFIX _user
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340 | 6ebbf390 | j_mayer | #define MMU_USER_IDX 3 |
341 | 6ebbf390 | j_mayer | static inline int cpu_mmu_index (CPUState *env) |
342 | 6ebbf390 | j_mayer | { |
343 | 6ebbf390 | j_mayer | return (env->ps >> 3) & 3; |
344 | 6ebbf390 | j_mayer | } |
345 | 6ebbf390 | j_mayer | |
346 | 6e68e076 | pbrook | #if defined(CONFIG_USER_ONLY)
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347 | 6e68e076 | pbrook | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
348 | 6e68e076 | pbrook | { |
349 | f8ed7070 | pbrook | if (newsp)
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350 | 6e68e076 | pbrook | env->ir[30] = newsp;
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351 | 6e68e076 | pbrook | /* FIXME: Zero syscall return value. */
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352 | 6e68e076 | pbrook | } |
353 | 6e68e076 | pbrook | #endif
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354 | 6e68e076 | pbrook | |
355 | 4c9649a9 | j_mayer | #include "cpu-all.h" |
356 | 622ed360 | aliguori | #include "exec-all.h" |
357 | 4c9649a9 | j_mayer | |
358 | 4c9649a9 | j_mayer | enum {
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359 | 4c9649a9 | j_mayer | FEATURE_ASN = 0x00000001,
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360 | 4c9649a9 | j_mayer | FEATURE_SPS = 0x00000002,
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361 | 4c9649a9 | j_mayer | FEATURE_VIRBND = 0x00000004,
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362 | 4c9649a9 | j_mayer | FEATURE_TBCHK = 0x00000008,
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363 | 4c9649a9 | j_mayer | }; |
364 | 4c9649a9 | j_mayer | |
365 | 4c9649a9 | j_mayer | enum {
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366 | 4c9649a9 | j_mayer | EXCP_RESET = 0x0000,
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367 | 4c9649a9 | j_mayer | EXCP_MCHK = 0x0020,
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368 | 4c9649a9 | j_mayer | EXCP_ARITH = 0x0060,
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369 | 4c9649a9 | j_mayer | EXCP_HW_INTERRUPT = 0x00E0,
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370 | 4c9649a9 | j_mayer | EXCP_DFAULT = 0x01E0,
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371 | 4c9649a9 | j_mayer | EXCP_DTB_MISS_PAL = 0x09E0,
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372 | 4c9649a9 | j_mayer | EXCP_ITB_MISS = 0x03E0,
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373 | 4c9649a9 | j_mayer | EXCP_ITB_ACV = 0x07E0,
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374 | 4c9649a9 | j_mayer | EXCP_DTB_MISS_NATIVE = 0x08E0,
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375 | 4c9649a9 | j_mayer | EXCP_UNALIGN = 0x11E0,
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376 | 4c9649a9 | j_mayer | EXCP_OPCDEC = 0x13E0,
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377 | 4c9649a9 | j_mayer | EXCP_FEN = 0x17E0,
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378 | 4c9649a9 | j_mayer | EXCP_CALL_PAL = 0x2000,
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379 | 4c9649a9 | j_mayer | EXCP_CALL_PALP = 0x3000,
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380 | 4c9649a9 | j_mayer | EXCP_CALL_PALE = 0x4000,
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381 | 4c9649a9 | j_mayer | /* Pseudo exception for console */
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382 | 4c9649a9 | j_mayer | EXCP_CONSOLE_DISPATCH = 0x4001,
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383 | 4c9649a9 | j_mayer | EXCP_CONSOLE_FIXUP = 0x4002,
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384 | 4c9649a9 | j_mayer | }; |
385 | 4c9649a9 | j_mayer | |
386 | 4c9649a9 | j_mayer | /* Arithmetic exception */
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387 | 4c9649a9 | j_mayer | enum {
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388 | 4c9649a9 | j_mayer | EXCP_ARITH_OVERFLOW, |
389 | 4c9649a9 | j_mayer | }; |
390 | 4c9649a9 | j_mayer | |
391 | 4c9649a9 | j_mayer | enum {
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392 | 4c9649a9 | j_mayer | PALCODE_CALL = 0x00000000,
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393 | 4c9649a9 | j_mayer | PALCODE_LD = 0x01000000,
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394 | 4c9649a9 | j_mayer | PALCODE_ST = 0x02000000,
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395 | 4c9649a9 | j_mayer | PALCODE_MFPR = 0x03000000,
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396 | 4c9649a9 | j_mayer | PALCODE_MTPR = 0x04000000,
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397 | 4c9649a9 | j_mayer | PALCODE_REI = 0x05000000,
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398 | 4c9649a9 | j_mayer | PALCODE_INIT = 0xF0000000,
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399 | 4c9649a9 | j_mayer | }; |
400 | 4c9649a9 | j_mayer | |
401 | 4c9649a9 | j_mayer | enum {
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402 | 4c9649a9 | j_mayer | IR_V0 = 0,
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403 | 4c9649a9 | j_mayer | IR_T0 = 1,
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404 | 4c9649a9 | j_mayer | IR_T1 = 2,
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405 | 4c9649a9 | j_mayer | IR_T2 = 3,
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406 | 4c9649a9 | j_mayer | IR_T3 = 4,
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407 | 4c9649a9 | j_mayer | IR_T4 = 5,
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408 | 4c9649a9 | j_mayer | IR_T5 = 6,
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409 | 4c9649a9 | j_mayer | IR_T6 = 7,
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410 | 4c9649a9 | j_mayer | IR_T7 = 8,
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411 | 4c9649a9 | j_mayer | IR_S0 = 9,
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412 | 4c9649a9 | j_mayer | IR_S1 = 10,
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413 | 4c9649a9 | j_mayer | IR_S2 = 11,
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414 | 4c9649a9 | j_mayer | IR_S3 = 12,
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415 | 4c9649a9 | j_mayer | IR_S4 = 13,
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416 | 4c9649a9 | j_mayer | IR_S5 = 14,
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417 | 4c9649a9 | j_mayer | IR_S6 = 15,
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418 | 4c9649a9 | j_mayer | #define IR_FP IR_S6
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419 | 4c9649a9 | j_mayer | IR_A0 = 16,
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420 | 4c9649a9 | j_mayer | IR_A1 = 17,
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421 | 4c9649a9 | j_mayer | IR_A2 = 18,
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422 | 4c9649a9 | j_mayer | IR_A3 = 19,
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423 | 4c9649a9 | j_mayer | IR_A4 = 20,
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424 | 4c9649a9 | j_mayer | IR_A5 = 21,
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425 | 4c9649a9 | j_mayer | IR_T8 = 22,
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426 | 4c9649a9 | j_mayer | IR_T9 = 23,
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427 | 4c9649a9 | j_mayer | IR_T10 = 24,
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428 | 4c9649a9 | j_mayer | IR_T11 = 25,
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429 | 4c9649a9 | j_mayer | IR_RA = 26,
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430 | 4c9649a9 | j_mayer | IR_T12 = 27,
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431 | 4c9649a9 | j_mayer | #define IR_PV IR_T12
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432 | 4c9649a9 | j_mayer | IR_AT = 28,
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433 | 4c9649a9 | j_mayer | IR_GP = 29,
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434 | 4c9649a9 | j_mayer | IR_SP = 30,
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435 | 4c9649a9 | j_mayer | IR_ZERO = 31,
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436 | 4c9649a9 | j_mayer | }; |
437 | 4c9649a9 | j_mayer | |
438 | aaed909a | bellard | CPUAlphaState * cpu_alpha_init (const char *cpu_model); |
439 | e96efcfc | j_mayer | int cpu_alpha_exec(CPUAlphaState *s);
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440 | e96efcfc | j_mayer | /* you can call this signal handler from your SIGBUS and SIGSEGV
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441 | e96efcfc | j_mayer | signal handlers to inform the virtual CPU of exceptions. non zero
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442 | e96efcfc | j_mayer | is returned if the signal was handled by the virtual CPU. */
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443 | 5fafdf24 | ths | int cpu_alpha_signal_handler(int host_signum, void *pinfo, |
444 | e96efcfc | j_mayer | void *puc);
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445 | 95870356 | aurel32 | int cpu_alpha_handle_mmu_fault (CPUState *env, uint64_t address, int rw, |
446 | 95870356 | aurel32 | int mmu_idx, int is_softmmu); |
447 | 95870356 | aurel32 | void do_interrupt (CPUState *env);
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448 | 95870356 | aurel32 | |
449 | 4c9649a9 | j_mayer | int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp); |
450 | 4c9649a9 | j_mayer | int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp); |
451 | 4c9649a9 | j_mayer | void pal_init (CPUState *env);
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452 | 7c9bde45 | aurel32 | #if !defined (CONFIG_USER_ONLY)
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453 | 7c9bde45 | aurel32 | void call_pal (CPUState *env);
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454 | 7c9bde45 | aurel32 | #else
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455 | 4c9649a9 | j_mayer | void call_pal (CPUState *env, int palcode); |
456 | 7c9bde45 | aurel32 | #endif
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457 | 4c9649a9 | j_mayer | |
458 | 622ed360 | aliguori | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
459 | 622ed360 | aliguori | { |
460 | 622ed360 | aliguori | env->pc = tb->pc; |
461 | 622ed360 | aliguori | } |
462 | 2e70f6ef | pbrook | |
463 | 6b917547 | aliguori | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
464 | 6b917547 | aliguori | target_ulong *cs_base, int *flags)
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465 | 6b917547 | aliguori | { |
466 | 6b917547 | aliguori | *pc = env->pc; |
467 | 6b917547 | aliguori | *cs_base = 0;
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468 | 6b917547 | aliguori | *flags = env->ps; |
469 | 6b917547 | aliguori | } |
470 | 6b917547 | aliguori | |
471 | 4c9649a9 | j_mayer | #endif /* !defined (__CPU_ALPHA_H__) */ |