Revision f8cc8534

b/target-alpha/cpu.h
144 144
/* XXX: TOFIX: most of those registers are implementation dependant */
145 145
enum {
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    /* Ebox IPRs */
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    IPR_CC           = 0xC0,
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    IPR_CC_CTL       = 0xC1,
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    IPR_VA           = 0xC2,
150
    IPR_VA_CTL       = 0xC4,
151
    IPR_VA_FORM      = 0xC3,
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    IPR_CC           = 0xC0,            /* 21264 */
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    IPR_CC_CTL       = 0xC1,            /* 21264 */
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#define IPR_CC_CTL_ENA_SHIFT 32
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#define IPR_CC_CTL_COUNTER_MASK 0xfffffff0UL
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    IPR_VA           = 0xC2,            /* 21264 */
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    IPR_VA_CTL       = 0xC4,            /* 21264 */
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#define IPR_VA_CTL_VA_48_SHIFT 1
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#define IPR_VA_CTL_VPTB_SHIFT 30
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    IPR_VA_FORM      = 0xC3,            /* 21264 */
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    /* Ibox IPRs */
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    IPR_ITB_TAG      = 0x00,
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    IPR_ITB_PTE      = 0x01,
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    IPT_ITB_IAP      = 0x02,
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    IPT_ITB_IA       = 0x03,
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    IPT_ITB_IS       = 0x04,
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    IPR_ITB_TAG      = 0x00,            /* 21264 */
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    IPR_ITB_PTE      = 0x01,            /* 21264 */
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    IPR_ITB_IAP      = 0x02,
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    IPR_ITB_IA       = 0x03,            /* 21264 */
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    IPR_ITB_IS       = 0x04,
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    IPR_PMPC         = 0x05,
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    IPR_EXC_ADDR     = 0x06,
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    IPR_IVA_FORM     = 0x07,
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    IPR_CM           = 0x09,
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    IPR_IER          = 0x0A,
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    IPR_SIRR         = 0x0C,
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    IPR_ISUM         = 0x0D,
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    IPR_HW_INT_CLR   = 0x0E,
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    IPR_EXC_ADDR     = 0x06,            /* 21264 */
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    IPR_IVA_FORM     = 0x07,            /* 21264 */
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    IPR_CM           = 0x09,            /* 21264 */
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#define IPR_CM_SHIFT 3
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#define IPR_CM_MASK (3ULL << IPR_CM_SHIFT)      /* 21264 */
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    IPR_IER          = 0x0A,            /* 21264 */
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#define IPR_IER_MASK 0x0000007fffffe000ULL
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    IPR_IER_CM       = 0x0B,            /* 21264: = CM | IER */
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    IPR_SIRR         = 0x0C,            /* 21264 */
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#define IPR_SIRR_SHIFT 14
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#define IPR_SIRR_MASK 0x7fff
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    IPR_ISUM         = 0x0D,            /* 21264 */
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    IPR_HW_INT_CLR   = 0x0E,            /* 21264 */
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    IPR_EXC_SUM      = 0x0F,
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    IPR_PAL_BASE     = 0x10,
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    IPR_I_CTL        = 0x11,
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    IPR_I_STAT       = 0x16,
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    IPR_IC_FLUSH     = 0x13,
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    IPR_IC_FLUSH_ASM = 0x12,
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#define IPR_I_CTL_CHIP_ID_SHIFT 24      /* 21264 */
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#define IPR_I_CTL_BIST_FAIL (1 << 23)   /* 21264 */
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#define IPR_I_CTL_IC_EN_SHIFT 2         /* 21264 */
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#define IPR_I_CTL_SDE1_SHIFT 7          /* 21264 */
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#define IPR_I_CTL_HWE_SHIFT 12          /* 21264 */
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#define IPR_I_CTL_VA_48_SHIFT 15        /* 21264 */
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#define IPR_I_CTL_SPE_SHIFT 3           /* 21264 */
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#define IPR_I_CTL_CALL_PAL_R23_SHIFT 20 /* 21264 */
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    IPR_I_STAT       = 0x16,            /* 21264 */
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    IPR_IC_FLUSH     = 0x13,            /* 21264 */
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    IPR_IC_FLUSH_ASM = 0x12,            /* 21264 */
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    IPR_CLR_MAP      = 0x15,
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    IPR_SLEEP        = 0x17,
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    IPR_PCTX         = 0x40,
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    IPR_PCTR_CTL     = 0x14,
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    IPR_PCTX_ASN       = 0x01,  /* field */
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#define IPR_PCTX_ASN_SHIFT 39
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    IPR_PCTX_ASTER     = 0x02,  /* field */
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#define IPR_PCTX_ASTER_SHIFT 5
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    IPR_PCTX_ASTRR     = 0x04,  /* field */
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#define IPR_PCTX_ASTRR_SHIFT 9
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    IPR_PCTX_PPCE      = 0x08,  /* field */
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#define IPR_PCTX_PPCE_SHIFT 1
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    IPR_PCTX_FPE       = 0x10,  /* field */
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#define IPR_PCTX_FPE_SHIFT 2
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    IPR_PCTX_ALL       = 0x5f,  /* all fields */
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    IPR_PCTR_CTL     = 0x14,            /* 21264 */
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    /* Mbox IPRs */
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    IPR_DTB_TAG0     = 0x20,
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    IPR_DTB_TAG1     = 0xA0,
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    IPR_DTB_PTE0     = 0x21,
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    IPR_DTB_PTE1     = 0xA1,
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    IPR_DTB_TAG0     = 0x20,            /* 21264 */
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    IPR_DTB_TAG1     = 0xA0,            /* 21264 */
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    IPR_DTB_PTE0     = 0x21,            /* 21264 */
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    IPR_DTB_PTE1     = 0xA1,            /* 21264 */
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    IPR_DTB_ALTMODE  = 0xA6,
211
    IPR_DTB_ALTMODE0 = 0x26,            /* 21264 */
212
#define IPR_DTB_ALTMODE_MASK 3
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    IPR_DTB_IAP      = 0xA2,
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    IPR_DTB_IA       = 0xA3,
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    IPR_DTB_IA       = 0xA3,            /* 21264 */
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    IPR_DTB_IS0      = 0x24,
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    IPR_DTB_IS1      = 0xA4,
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    IPR_DTB_ASN0     = 0x25,
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    IPR_DTB_ASN1     = 0xA5,
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    IPR_MM_STAT      = 0x27,
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    IPR_M_CTL        = 0x28,
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    IPR_DTB_ASN0     = 0x25,            /* 21264 */
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    IPR_DTB_ASN1     = 0xA5,            /* 21264 */
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#define IPR_DTB_ASN_SHIFT 56
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    IPR_MM_STAT      = 0x27,            /* 21264 */
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    IPR_M_CTL        = 0x28,            /* 21264 */
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#define IPR_M_CTL_SPE_SHIFT 1
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#define IPR_M_CTL_SPE_MASK 7
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    IPR_DC_CTL       = 0x29,
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    IPR_DC_STAT      = 0x2A,
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    IPR_DC_STAT      = 0x2A,            /* 21264 */
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    /* Cbox IPRs */
193 227
    IPR_C_DATA       = 0x2B,
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    IPR_C_SHIFT      = 0x2C,

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