Statistics
| Branch: | Revision:

root / target-i386 / ops_sse.h @ f8ed7070

History | View | Annotate | Download (34 kB)

1 664e0f19 bellard
/*
2 a35f3ec7 aurel32
 *  MMX/3DNow!/SSE/SSE2/SSE3/PNI support
3 5fafdf24 ths
 *
4 664e0f19 bellard
 *  Copyright (c) 2005 Fabrice Bellard
5 664e0f19 bellard
 *
6 664e0f19 bellard
 * This library is free software; you can redistribute it and/or
7 664e0f19 bellard
 * modify it under the terms of the GNU Lesser General Public
8 664e0f19 bellard
 * License as published by the Free Software Foundation; either
9 664e0f19 bellard
 * version 2 of the License, or (at your option) any later version.
10 664e0f19 bellard
 *
11 664e0f19 bellard
 * This library is distributed in the hope that it will be useful,
12 664e0f19 bellard
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 664e0f19 bellard
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 664e0f19 bellard
 * Lesser General Public License for more details.
15 664e0f19 bellard
 *
16 664e0f19 bellard
 * You should have received a copy of the GNU Lesser General Public
17 664e0f19 bellard
 * License along with this library; if not, write to the Free Software
18 664e0f19 bellard
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19 664e0f19 bellard
 */
20 664e0f19 bellard
#if SHIFT == 0
21 664e0f19 bellard
#define Reg MMXReg
22 664e0f19 bellard
#define XMM_ONLY(x...)
23 664e0f19 bellard
#define B(n) MMX_B(n)
24 664e0f19 bellard
#define W(n) MMX_W(n)
25 664e0f19 bellard
#define L(n) MMX_L(n)
26 664e0f19 bellard
#define Q(n) q
27 664e0f19 bellard
#define SUFFIX _mmx
28 664e0f19 bellard
#else
29 664e0f19 bellard
#define Reg XMMReg
30 664e0f19 bellard
#define XMM_ONLY(x...) x
31 664e0f19 bellard
#define B(n) XMM_B(n)
32 664e0f19 bellard
#define W(n) XMM_W(n)
33 664e0f19 bellard
#define L(n) XMM_L(n)
34 664e0f19 bellard
#define Q(n) XMM_Q(n)
35 664e0f19 bellard
#define SUFFIX _xmm
36 664e0f19 bellard
#endif
37 664e0f19 bellard
38 5af45186 bellard
void glue(helper_psrlw, SUFFIX)(Reg *d, Reg *s)
39 664e0f19 bellard
{
40 664e0f19 bellard
    int shift;
41 664e0f19 bellard
42 664e0f19 bellard
    if (s->Q(0) > 15) {
43 664e0f19 bellard
        d->Q(0) = 0;
44 664e0f19 bellard
#if SHIFT == 1
45 664e0f19 bellard
        d->Q(1) = 0;
46 664e0f19 bellard
#endif
47 664e0f19 bellard
    } else {
48 664e0f19 bellard
        shift = s->B(0);
49 664e0f19 bellard
        d->W(0) >>= shift;
50 664e0f19 bellard
        d->W(1) >>= shift;
51 664e0f19 bellard
        d->W(2) >>= shift;
52 664e0f19 bellard
        d->W(3) >>= shift;
53 664e0f19 bellard
#if SHIFT == 1
54 664e0f19 bellard
        d->W(4) >>= shift;
55 664e0f19 bellard
        d->W(5) >>= shift;
56 664e0f19 bellard
        d->W(6) >>= shift;
57 664e0f19 bellard
        d->W(7) >>= shift;
58 664e0f19 bellard
#endif
59 664e0f19 bellard
    }
60 0523c6b7 bellard
    FORCE_RET();
61 664e0f19 bellard
}
62 664e0f19 bellard
63 5af45186 bellard
void glue(helper_psraw, SUFFIX)(Reg *d, Reg *s)
64 664e0f19 bellard
{
65 664e0f19 bellard
    int shift;
66 664e0f19 bellard
67 664e0f19 bellard
    if (s->Q(0) > 15) {
68 664e0f19 bellard
        shift = 15;
69 664e0f19 bellard
    } else {
70 664e0f19 bellard
        shift = s->B(0);
71 664e0f19 bellard
    }
72 664e0f19 bellard
    d->W(0) = (int16_t)d->W(0) >> shift;
73 664e0f19 bellard
    d->W(1) = (int16_t)d->W(1) >> shift;
74 664e0f19 bellard
    d->W(2) = (int16_t)d->W(2) >> shift;
75 664e0f19 bellard
    d->W(3) = (int16_t)d->W(3) >> shift;
76 664e0f19 bellard
#if SHIFT == 1
77 664e0f19 bellard
    d->W(4) = (int16_t)d->W(4) >> shift;
78 664e0f19 bellard
    d->W(5) = (int16_t)d->W(5) >> shift;
79 664e0f19 bellard
    d->W(6) = (int16_t)d->W(6) >> shift;
80 664e0f19 bellard
    d->W(7) = (int16_t)d->W(7) >> shift;
81 664e0f19 bellard
#endif
82 664e0f19 bellard
}
83 664e0f19 bellard
84 5af45186 bellard
void glue(helper_psllw, SUFFIX)(Reg *d, Reg *s)
85 664e0f19 bellard
{
86 664e0f19 bellard
    int shift;
87 664e0f19 bellard
88 664e0f19 bellard
    if (s->Q(0) > 15) {
89 664e0f19 bellard
        d->Q(0) = 0;
90 664e0f19 bellard
#if SHIFT == 1
91 664e0f19 bellard
        d->Q(1) = 0;
92 664e0f19 bellard
#endif
93 664e0f19 bellard
    } else {
94 664e0f19 bellard
        shift = s->B(0);
95 664e0f19 bellard
        d->W(0) <<= shift;
96 664e0f19 bellard
        d->W(1) <<= shift;
97 664e0f19 bellard
        d->W(2) <<= shift;
98 664e0f19 bellard
        d->W(3) <<= shift;
99 664e0f19 bellard
#if SHIFT == 1
100 664e0f19 bellard
        d->W(4) <<= shift;
101 664e0f19 bellard
        d->W(5) <<= shift;
102 664e0f19 bellard
        d->W(6) <<= shift;
103 664e0f19 bellard
        d->W(7) <<= shift;
104 664e0f19 bellard
#endif
105 664e0f19 bellard
    }
106 0523c6b7 bellard
    FORCE_RET();
107 664e0f19 bellard
}
108 664e0f19 bellard
109 5af45186 bellard
void glue(helper_psrld, SUFFIX)(Reg *d, Reg *s)
110 664e0f19 bellard
{
111 664e0f19 bellard
    int shift;
112 664e0f19 bellard
113 664e0f19 bellard
    if (s->Q(0) > 31) {
114 664e0f19 bellard
        d->Q(0) = 0;
115 664e0f19 bellard
#if SHIFT == 1
116 664e0f19 bellard
        d->Q(1) = 0;
117 664e0f19 bellard
#endif
118 664e0f19 bellard
    } else {
119 664e0f19 bellard
        shift = s->B(0);
120 664e0f19 bellard
        d->L(0) >>= shift;
121 664e0f19 bellard
        d->L(1) >>= shift;
122 664e0f19 bellard
#if SHIFT == 1
123 664e0f19 bellard
        d->L(2) >>= shift;
124 664e0f19 bellard
        d->L(3) >>= shift;
125 664e0f19 bellard
#endif
126 664e0f19 bellard
    }
127 0523c6b7 bellard
    FORCE_RET();
128 664e0f19 bellard
}
129 664e0f19 bellard
130 5af45186 bellard
void glue(helper_psrad, SUFFIX)(Reg *d, Reg *s)
131 664e0f19 bellard
{
132 664e0f19 bellard
    int shift;
133 664e0f19 bellard
134 664e0f19 bellard
    if (s->Q(0) > 31) {
135 664e0f19 bellard
        shift = 31;
136 664e0f19 bellard
    } else {
137 664e0f19 bellard
        shift = s->B(0);
138 664e0f19 bellard
    }
139 664e0f19 bellard
    d->L(0) = (int32_t)d->L(0) >> shift;
140 664e0f19 bellard
    d->L(1) = (int32_t)d->L(1) >> shift;
141 664e0f19 bellard
#if SHIFT == 1
142 664e0f19 bellard
    d->L(2) = (int32_t)d->L(2) >> shift;
143 664e0f19 bellard
    d->L(3) = (int32_t)d->L(3) >> shift;
144 664e0f19 bellard
#endif
145 664e0f19 bellard
}
146 664e0f19 bellard
147 5af45186 bellard
void glue(helper_pslld, SUFFIX)(Reg *d, Reg *s)
148 664e0f19 bellard
{
149 664e0f19 bellard
    int shift;
150 664e0f19 bellard
151 664e0f19 bellard
    if (s->Q(0) > 31) {
152 664e0f19 bellard
        d->Q(0) = 0;
153 664e0f19 bellard
#if SHIFT == 1
154 664e0f19 bellard
        d->Q(1) = 0;
155 664e0f19 bellard
#endif
156 664e0f19 bellard
    } else {
157 664e0f19 bellard
        shift = s->B(0);
158 664e0f19 bellard
        d->L(0) <<= shift;
159 664e0f19 bellard
        d->L(1) <<= shift;
160 664e0f19 bellard
#if SHIFT == 1
161 664e0f19 bellard
        d->L(2) <<= shift;
162 664e0f19 bellard
        d->L(3) <<= shift;
163 664e0f19 bellard
#endif
164 664e0f19 bellard
    }
165 0523c6b7 bellard
    FORCE_RET();
166 664e0f19 bellard
}
167 664e0f19 bellard
168 5af45186 bellard
void glue(helper_psrlq, SUFFIX)(Reg *d, Reg *s)
169 664e0f19 bellard
{
170 664e0f19 bellard
    int shift;
171 664e0f19 bellard
172 664e0f19 bellard
    if (s->Q(0) > 63) {
173 664e0f19 bellard
        d->Q(0) = 0;
174 664e0f19 bellard
#if SHIFT == 1
175 664e0f19 bellard
        d->Q(1) = 0;
176 664e0f19 bellard
#endif
177 664e0f19 bellard
    } else {
178 664e0f19 bellard
        shift = s->B(0);
179 664e0f19 bellard
        d->Q(0) >>= shift;
180 664e0f19 bellard
#if SHIFT == 1
181 664e0f19 bellard
        d->Q(1) >>= shift;
182 664e0f19 bellard
#endif
183 664e0f19 bellard
    }
184 0523c6b7 bellard
    FORCE_RET();
185 664e0f19 bellard
}
186 664e0f19 bellard
187 5af45186 bellard
void glue(helper_psllq, SUFFIX)(Reg *d, Reg *s)
188 664e0f19 bellard
{
189 664e0f19 bellard
    int shift;
190 664e0f19 bellard
191 664e0f19 bellard
    if (s->Q(0) > 63) {
192 664e0f19 bellard
        d->Q(0) = 0;
193 664e0f19 bellard
#if SHIFT == 1
194 664e0f19 bellard
        d->Q(1) = 0;
195 664e0f19 bellard
#endif
196 664e0f19 bellard
    } else {
197 664e0f19 bellard
        shift = s->B(0);
198 664e0f19 bellard
        d->Q(0) <<= shift;
199 664e0f19 bellard
#if SHIFT == 1
200 664e0f19 bellard
        d->Q(1) <<= shift;
201 664e0f19 bellard
#endif
202 664e0f19 bellard
    }
203 0523c6b7 bellard
    FORCE_RET();
204 664e0f19 bellard
}
205 664e0f19 bellard
206 664e0f19 bellard
#if SHIFT == 1
207 5af45186 bellard
void glue(helper_psrldq, SUFFIX)(Reg *d, Reg *s)
208 664e0f19 bellard
{
209 664e0f19 bellard
    int shift, i;
210 664e0f19 bellard
211 664e0f19 bellard
    shift = s->L(0);
212 664e0f19 bellard
    if (shift > 16)
213 664e0f19 bellard
        shift = 16;
214 664e0f19 bellard
    for(i = 0; i < 16 - shift; i++)
215 664e0f19 bellard
        d->B(i) = d->B(i + shift);
216 664e0f19 bellard
    for(i = 16 - shift; i < 16; i++)
217 664e0f19 bellard
        d->B(i) = 0;
218 664e0f19 bellard
    FORCE_RET();
219 664e0f19 bellard
}
220 664e0f19 bellard
221 5af45186 bellard
void glue(helper_pslldq, SUFFIX)(Reg *d, Reg *s)
222 664e0f19 bellard
{
223 664e0f19 bellard
    int shift, i;
224 664e0f19 bellard
225 664e0f19 bellard
    shift = s->L(0);
226 664e0f19 bellard
    if (shift > 16)
227 664e0f19 bellard
        shift = 16;
228 664e0f19 bellard
    for(i = 15; i >= shift; i--)
229 664e0f19 bellard
        d->B(i) = d->B(i - shift);
230 664e0f19 bellard
    for(i = 0; i < shift; i++)
231 664e0f19 bellard
        d->B(i) = 0;
232 664e0f19 bellard
    FORCE_RET();
233 664e0f19 bellard
}
234 664e0f19 bellard
#endif
235 664e0f19 bellard
236 5af45186 bellard
#define SSE_HELPER_B(name, F)\
237 5af45186 bellard
void glue(name, SUFFIX) (Reg *d, Reg *s)\
238 664e0f19 bellard
{\
239 664e0f19 bellard
    d->B(0) = F(d->B(0), s->B(0));\
240 664e0f19 bellard
    d->B(1) = F(d->B(1), s->B(1));\
241 664e0f19 bellard
    d->B(2) = F(d->B(2), s->B(2));\
242 664e0f19 bellard
    d->B(3) = F(d->B(3), s->B(3));\
243 664e0f19 bellard
    d->B(4) = F(d->B(4), s->B(4));\
244 664e0f19 bellard
    d->B(5) = F(d->B(5), s->B(5));\
245 664e0f19 bellard
    d->B(6) = F(d->B(6), s->B(6));\
246 664e0f19 bellard
    d->B(7) = F(d->B(7), s->B(7));\
247 664e0f19 bellard
    XMM_ONLY(\
248 664e0f19 bellard
    d->B(8) = F(d->B(8), s->B(8));\
249 664e0f19 bellard
    d->B(9) = F(d->B(9), s->B(9));\
250 664e0f19 bellard
    d->B(10) = F(d->B(10), s->B(10));\
251 664e0f19 bellard
    d->B(11) = F(d->B(11), s->B(11));\
252 664e0f19 bellard
    d->B(12) = F(d->B(12), s->B(12));\
253 664e0f19 bellard
    d->B(13) = F(d->B(13), s->B(13));\
254 664e0f19 bellard
    d->B(14) = F(d->B(14), s->B(14));\
255 664e0f19 bellard
    d->B(15) = F(d->B(15), s->B(15));\
256 664e0f19 bellard
    )\
257 664e0f19 bellard
}
258 664e0f19 bellard
259 5af45186 bellard
#define SSE_HELPER_W(name, F)\
260 5af45186 bellard
void glue(name, SUFFIX) (Reg *d, Reg *s)\
261 664e0f19 bellard
{\
262 664e0f19 bellard
    d->W(0) = F(d->W(0), s->W(0));\
263 664e0f19 bellard
    d->W(1) = F(d->W(1), s->W(1));\
264 664e0f19 bellard
    d->W(2) = F(d->W(2), s->W(2));\
265 664e0f19 bellard
    d->W(3) = F(d->W(3), s->W(3));\
266 664e0f19 bellard
    XMM_ONLY(\
267 664e0f19 bellard
    d->W(4) = F(d->W(4), s->W(4));\
268 664e0f19 bellard
    d->W(5) = F(d->W(5), s->W(5));\
269 664e0f19 bellard
    d->W(6) = F(d->W(6), s->W(6));\
270 664e0f19 bellard
    d->W(7) = F(d->W(7), s->W(7));\
271 664e0f19 bellard
    )\
272 664e0f19 bellard
}
273 664e0f19 bellard
274 5af45186 bellard
#define SSE_HELPER_L(name, F)\
275 5af45186 bellard
void glue(name, SUFFIX) (Reg *d, Reg *s)\
276 664e0f19 bellard
{\
277 664e0f19 bellard
    d->L(0) = F(d->L(0), s->L(0));\
278 664e0f19 bellard
    d->L(1) = F(d->L(1), s->L(1));\
279 664e0f19 bellard
    XMM_ONLY(\
280 664e0f19 bellard
    d->L(2) = F(d->L(2), s->L(2));\
281 664e0f19 bellard
    d->L(3) = F(d->L(3), s->L(3));\
282 664e0f19 bellard
    )\
283 664e0f19 bellard
}
284 664e0f19 bellard
285 5af45186 bellard
#define SSE_HELPER_Q(name, F)\
286 5af45186 bellard
void glue(name, SUFFIX) (Reg *d, Reg *s)\
287 664e0f19 bellard
{\
288 664e0f19 bellard
    d->Q(0) = F(d->Q(0), s->Q(0));\
289 664e0f19 bellard
    XMM_ONLY(\
290 664e0f19 bellard
    d->Q(1) = F(d->Q(1), s->Q(1));\
291 664e0f19 bellard
    )\
292 664e0f19 bellard
}
293 664e0f19 bellard
294 664e0f19 bellard
#if SHIFT == 0
295 664e0f19 bellard
static inline int satub(int x)
296 664e0f19 bellard
{
297 664e0f19 bellard
    if (x < 0)
298 664e0f19 bellard
        return 0;
299 664e0f19 bellard
    else if (x > 255)
300 664e0f19 bellard
        return 255;
301 664e0f19 bellard
    else
302 664e0f19 bellard
        return x;
303 664e0f19 bellard
}
304 664e0f19 bellard
305 664e0f19 bellard
static inline int satuw(int x)
306 664e0f19 bellard
{
307 664e0f19 bellard
    if (x < 0)
308 664e0f19 bellard
        return 0;
309 664e0f19 bellard
    else if (x > 65535)
310 664e0f19 bellard
        return 65535;
311 664e0f19 bellard
    else
312 664e0f19 bellard
        return x;
313 664e0f19 bellard
}
314 664e0f19 bellard
315 664e0f19 bellard
static inline int satsb(int x)
316 664e0f19 bellard
{
317 664e0f19 bellard
    if (x < -128)
318 664e0f19 bellard
        return -128;
319 664e0f19 bellard
    else if (x > 127)
320 664e0f19 bellard
        return 127;
321 664e0f19 bellard
    else
322 664e0f19 bellard
        return x;
323 664e0f19 bellard
}
324 664e0f19 bellard
325 664e0f19 bellard
static inline int satsw(int x)
326 664e0f19 bellard
{
327 664e0f19 bellard
    if (x < -32768)
328 664e0f19 bellard
        return -32768;
329 664e0f19 bellard
    else if (x > 32767)
330 664e0f19 bellard
        return 32767;
331 664e0f19 bellard
    else
332 664e0f19 bellard
        return x;
333 664e0f19 bellard
}
334 664e0f19 bellard
335 664e0f19 bellard
#define FADD(a, b) ((a) + (b))
336 664e0f19 bellard
#define FADDUB(a, b) satub((a) + (b))
337 664e0f19 bellard
#define FADDUW(a, b) satuw((a) + (b))
338 664e0f19 bellard
#define FADDSB(a, b) satsb((int8_t)(a) + (int8_t)(b))
339 664e0f19 bellard
#define FADDSW(a, b) satsw((int16_t)(a) + (int16_t)(b))
340 664e0f19 bellard
341 664e0f19 bellard
#define FSUB(a, b) ((a) - (b))
342 664e0f19 bellard
#define FSUBUB(a, b) satub((a) - (b))
343 664e0f19 bellard
#define FSUBUW(a, b) satuw((a) - (b))
344 664e0f19 bellard
#define FSUBSB(a, b) satsb((int8_t)(a) - (int8_t)(b))
345 664e0f19 bellard
#define FSUBSW(a, b) satsw((int16_t)(a) - (int16_t)(b))
346 664e0f19 bellard
#define FMINUB(a, b) ((a) < (b)) ? (a) : (b)
347 664e0f19 bellard
#define FMINSW(a, b) ((int16_t)(a) < (int16_t)(b)) ? (a) : (b)
348 664e0f19 bellard
#define FMAXUB(a, b) ((a) > (b)) ? (a) : (b)
349 664e0f19 bellard
#define FMAXSW(a, b) ((int16_t)(a) > (int16_t)(b)) ? (a) : (b)
350 664e0f19 bellard
351 664e0f19 bellard
#define FAND(a, b) (a) & (b)
352 664e0f19 bellard
#define FANDN(a, b) ((~(a)) & (b))
353 664e0f19 bellard
#define FOR(a, b) (a) | (b)
354 664e0f19 bellard
#define FXOR(a, b) (a) ^ (b)
355 664e0f19 bellard
356 664e0f19 bellard
#define FCMPGTB(a, b) (int8_t)(a) > (int8_t)(b) ? -1 : 0
357 664e0f19 bellard
#define FCMPGTW(a, b) (int16_t)(a) > (int16_t)(b) ? -1 : 0
358 664e0f19 bellard
#define FCMPGTL(a, b) (int32_t)(a) > (int32_t)(b) ? -1 : 0
359 664e0f19 bellard
#define FCMPEQ(a, b) (a) == (b) ? -1 : 0
360 664e0f19 bellard
361 664e0f19 bellard
#define FMULLW(a, b) (a) * (b)
362 a35f3ec7 aurel32
#define FMULHRW(a, b) ((int16_t)(a) * (int16_t)(b) + 0x8000) >> 16
363 664e0f19 bellard
#define FMULHUW(a, b) (a) * (b) >> 16
364 664e0f19 bellard
#define FMULHW(a, b) (int16_t)(a) * (int16_t)(b) >> 16
365 664e0f19 bellard
366 664e0f19 bellard
#define FAVG(a, b) ((a) + (b) + 1) >> 1
367 664e0f19 bellard
#endif
368 664e0f19 bellard
369 5af45186 bellard
SSE_HELPER_B(helper_paddb, FADD)
370 5af45186 bellard
SSE_HELPER_W(helper_paddw, FADD)
371 5af45186 bellard
SSE_HELPER_L(helper_paddl, FADD)
372 5af45186 bellard
SSE_HELPER_Q(helper_paddq, FADD)
373 664e0f19 bellard
374 5af45186 bellard
SSE_HELPER_B(helper_psubb, FSUB)
375 5af45186 bellard
SSE_HELPER_W(helper_psubw, FSUB)
376 5af45186 bellard
SSE_HELPER_L(helper_psubl, FSUB)
377 5af45186 bellard
SSE_HELPER_Q(helper_psubq, FSUB)
378 664e0f19 bellard
379 5af45186 bellard
SSE_HELPER_B(helper_paddusb, FADDUB)
380 5af45186 bellard
SSE_HELPER_B(helper_paddsb, FADDSB)
381 5af45186 bellard
SSE_HELPER_B(helper_psubusb, FSUBUB)
382 5af45186 bellard
SSE_HELPER_B(helper_psubsb, FSUBSB)
383 664e0f19 bellard
384 5af45186 bellard
SSE_HELPER_W(helper_paddusw, FADDUW)
385 5af45186 bellard
SSE_HELPER_W(helper_paddsw, FADDSW)
386 5af45186 bellard
SSE_HELPER_W(helper_psubusw, FSUBUW)
387 5af45186 bellard
SSE_HELPER_W(helper_psubsw, FSUBSW)
388 664e0f19 bellard
389 5af45186 bellard
SSE_HELPER_B(helper_pminub, FMINUB)
390 5af45186 bellard
SSE_HELPER_B(helper_pmaxub, FMAXUB)
391 664e0f19 bellard
392 5af45186 bellard
SSE_HELPER_W(helper_pminsw, FMINSW)
393 5af45186 bellard
SSE_HELPER_W(helper_pmaxsw, FMAXSW)
394 664e0f19 bellard
395 5af45186 bellard
SSE_HELPER_Q(helper_pand, FAND)
396 5af45186 bellard
SSE_HELPER_Q(helper_pandn, FANDN)
397 5af45186 bellard
SSE_HELPER_Q(helper_por, FOR)
398 5af45186 bellard
SSE_HELPER_Q(helper_pxor, FXOR)
399 664e0f19 bellard
400 5af45186 bellard
SSE_HELPER_B(helper_pcmpgtb, FCMPGTB)
401 5af45186 bellard
SSE_HELPER_W(helper_pcmpgtw, FCMPGTW)
402 5af45186 bellard
SSE_HELPER_L(helper_pcmpgtl, FCMPGTL)
403 664e0f19 bellard
404 5af45186 bellard
SSE_HELPER_B(helper_pcmpeqb, FCMPEQ)
405 5af45186 bellard
SSE_HELPER_W(helper_pcmpeqw, FCMPEQ)
406 5af45186 bellard
SSE_HELPER_L(helper_pcmpeql, FCMPEQ)
407 664e0f19 bellard
408 5af45186 bellard
SSE_HELPER_W(helper_pmullw, FMULLW)
409 a35f3ec7 aurel32
#if SHIFT == 0
410 5af45186 bellard
SSE_HELPER_W(helper_pmulhrw, FMULHRW)
411 a35f3ec7 aurel32
#endif
412 5af45186 bellard
SSE_HELPER_W(helper_pmulhuw, FMULHUW)
413 5af45186 bellard
SSE_HELPER_W(helper_pmulhw, FMULHW)
414 664e0f19 bellard
415 5af45186 bellard
SSE_HELPER_B(helper_pavgb, FAVG)
416 5af45186 bellard
SSE_HELPER_W(helper_pavgw, FAVG)
417 664e0f19 bellard
418 5af45186 bellard
void glue(helper_pmuludq, SUFFIX) (Reg *d, Reg *s)
419 664e0f19 bellard
{
420 664e0f19 bellard
    d->Q(0) = (uint64_t)s->L(0) * (uint64_t)d->L(0);
421 664e0f19 bellard
#if SHIFT == 1
422 664e0f19 bellard
    d->Q(1) = (uint64_t)s->L(2) * (uint64_t)d->L(2);
423 664e0f19 bellard
#endif
424 664e0f19 bellard
}
425 664e0f19 bellard
426 5af45186 bellard
void glue(helper_pmaddwd, SUFFIX) (Reg *d, Reg *s)
427 664e0f19 bellard
{
428 664e0f19 bellard
    int i;
429 664e0f19 bellard
430 664e0f19 bellard
    for(i = 0; i < (2 << SHIFT); i++) {
431 664e0f19 bellard
        d->L(i) = (int16_t)s->W(2*i) * (int16_t)d->W(2*i) +
432 664e0f19 bellard
            (int16_t)s->W(2*i+1) * (int16_t)d->W(2*i+1);
433 664e0f19 bellard
    }
434 0523c6b7 bellard
    FORCE_RET();
435 664e0f19 bellard
}
436 664e0f19 bellard
437 664e0f19 bellard
#if SHIFT == 0
438 664e0f19 bellard
static inline int abs1(int a)
439 664e0f19 bellard
{
440 664e0f19 bellard
    if (a < 0)
441 664e0f19 bellard
        return -a;
442 664e0f19 bellard
    else
443 664e0f19 bellard
        return a;
444 664e0f19 bellard
}
445 664e0f19 bellard
#endif
446 5af45186 bellard
void glue(helper_psadbw, SUFFIX) (Reg *d, Reg *s)
447 664e0f19 bellard
{
448 664e0f19 bellard
    unsigned int val;
449 664e0f19 bellard
450 664e0f19 bellard
    val = 0;
451 664e0f19 bellard
    val += abs1(d->B(0) - s->B(0));
452 664e0f19 bellard
    val += abs1(d->B(1) - s->B(1));
453 664e0f19 bellard
    val += abs1(d->B(2) - s->B(2));
454 664e0f19 bellard
    val += abs1(d->B(3) - s->B(3));
455 664e0f19 bellard
    val += abs1(d->B(4) - s->B(4));
456 664e0f19 bellard
    val += abs1(d->B(5) - s->B(5));
457 664e0f19 bellard
    val += abs1(d->B(6) - s->B(6));
458 664e0f19 bellard
    val += abs1(d->B(7) - s->B(7));
459 664e0f19 bellard
    d->Q(0) = val;
460 664e0f19 bellard
#if SHIFT == 1
461 664e0f19 bellard
    val = 0;
462 664e0f19 bellard
    val += abs1(d->B(8) - s->B(8));
463 664e0f19 bellard
    val += abs1(d->B(9) - s->B(9));
464 664e0f19 bellard
    val += abs1(d->B(10) - s->B(10));
465 664e0f19 bellard
    val += abs1(d->B(11) - s->B(11));
466 664e0f19 bellard
    val += abs1(d->B(12) - s->B(12));
467 664e0f19 bellard
    val += abs1(d->B(13) - s->B(13));
468 664e0f19 bellard
    val += abs1(d->B(14) - s->B(14));
469 664e0f19 bellard
    val += abs1(d->B(15) - s->B(15));
470 664e0f19 bellard
    d->Q(1) = val;
471 664e0f19 bellard
#endif
472 664e0f19 bellard
}
473 664e0f19 bellard
474 b8b6a50b bellard
void glue(helper_maskmov, SUFFIX) (Reg *d, Reg *s, target_ulong a0)
475 664e0f19 bellard
{
476 664e0f19 bellard
    int i;
477 664e0f19 bellard
    for(i = 0; i < (8 << SHIFT); i++) {
478 664e0f19 bellard
        if (s->B(i) & 0x80)
479 b8b6a50b bellard
            stb(a0 + i, d->B(i));
480 664e0f19 bellard
    }
481 0523c6b7 bellard
    FORCE_RET();
482 664e0f19 bellard
}
483 664e0f19 bellard
484 5af45186 bellard
void glue(helper_movl_mm_T0, SUFFIX) (Reg *d, uint32_t val)
485 664e0f19 bellard
{
486 5af45186 bellard
    d->L(0) = val;
487 664e0f19 bellard
    d->L(1) = 0;
488 664e0f19 bellard
#if SHIFT == 1
489 664e0f19 bellard
    d->Q(1) = 0;
490 664e0f19 bellard
#endif
491 664e0f19 bellard
}
492 664e0f19 bellard
493 dabd98dd bellard
#ifdef TARGET_X86_64
494 5af45186 bellard
void glue(helper_movq_mm_T0, SUFFIX) (Reg *d, uint64_t val)
495 dabd98dd bellard
{
496 5af45186 bellard
    d->Q(0) = val;
497 dabd98dd bellard
#if SHIFT == 1
498 dabd98dd bellard
    d->Q(1) = 0;
499 dabd98dd bellard
#endif
500 dabd98dd bellard
}
501 dabd98dd bellard
#endif
502 dabd98dd bellard
503 664e0f19 bellard
#if SHIFT == 0
504 5af45186 bellard
void glue(helper_pshufw, SUFFIX) (Reg *d, Reg *s, int order)
505 664e0f19 bellard
{
506 5af45186 bellard
    Reg r;
507 664e0f19 bellard
    r.W(0) = s->W(order & 3);
508 664e0f19 bellard
    r.W(1) = s->W((order >> 2) & 3);
509 664e0f19 bellard
    r.W(2) = s->W((order >> 4) & 3);
510 664e0f19 bellard
    r.W(3) = s->W((order >> 6) & 3);
511 664e0f19 bellard
    *d = r;
512 664e0f19 bellard
}
513 664e0f19 bellard
#else
514 5af45186 bellard
void helper_shufps(Reg *d, Reg *s, int order)
515 d52cf7a6 bellard
{
516 5af45186 bellard
    Reg r;
517 d52cf7a6 bellard
    r.L(0) = d->L(order & 3);
518 d52cf7a6 bellard
    r.L(1) = d->L((order >> 2) & 3);
519 d52cf7a6 bellard
    r.L(2) = s->L((order >> 4) & 3);
520 d52cf7a6 bellard
    r.L(3) = s->L((order >> 6) & 3);
521 d52cf7a6 bellard
    *d = r;
522 d52cf7a6 bellard
}
523 d52cf7a6 bellard
524 5af45186 bellard
void helper_shufpd(Reg *d, Reg *s, int order)
525 664e0f19 bellard
{
526 5af45186 bellard
    Reg r;
527 d52cf7a6 bellard
    r.Q(0) = d->Q(order & 1);
528 664e0f19 bellard
    r.Q(1) = s->Q((order >> 1) & 1);
529 664e0f19 bellard
    *d = r;
530 664e0f19 bellard
}
531 664e0f19 bellard
532 5af45186 bellard
void glue(helper_pshufd, SUFFIX) (Reg *d, Reg *s, int order)
533 664e0f19 bellard
{
534 5af45186 bellard
    Reg r;
535 664e0f19 bellard
    r.L(0) = s->L(order & 3);
536 664e0f19 bellard
    r.L(1) = s->L((order >> 2) & 3);
537 664e0f19 bellard
    r.L(2) = s->L((order >> 4) & 3);
538 664e0f19 bellard
    r.L(3) = s->L((order >> 6) & 3);
539 664e0f19 bellard
    *d = r;
540 664e0f19 bellard
}
541 664e0f19 bellard
542 5af45186 bellard
void glue(helper_pshuflw, SUFFIX) (Reg *d, Reg *s, int order)
543 664e0f19 bellard
{
544 5af45186 bellard
    Reg r;
545 664e0f19 bellard
    r.W(0) = s->W(order & 3);
546 664e0f19 bellard
    r.W(1) = s->W((order >> 2) & 3);
547 664e0f19 bellard
    r.W(2) = s->W((order >> 4) & 3);
548 664e0f19 bellard
    r.W(3) = s->W((order >> 6) & 3);
549 664e0f19 bellard
    r.Q(1) = s->Q(1);
550 664e0f19 bellard
    *d = r;
551 664e0f19 bellard
}
552 664e0f19 bellard
553 5af45186 bellard
void glue(helper_pshufhw, SUFFIX) (Reg *d, Reg *s, int order)
554 664e0f19 bellard
{
555 5af45186 bellard
    Reg r;
556 664e0f19 bellard
    r.Q(0) = s->Q(0);
557 664e0f19 bellard
    r.W(4) = s->W(4 + (order & 3));
558 664e0f19 bellard
    r.W(5) = s->W(4 + ((order >> 2) & 3));
559 664e0f19 bellard
    r.W(6) = s->W(4 + ((order >> 4) & 3));
560 664e0f19 bellard
    r.W(7) = s->W(4 + ((order >> 6) & 3));
561 664e0f19 bellard
    *d = r;
562 664e0f19 bellard
}
563 664e0f19 bellard
#endif
564 664e0f19 bellard
565 664e0f19 bellard
#if SHIFT == 1
566 664e0f19 bellard
/* FPU ops */
567 664e0f19 bellard
/* XXX: not accurate */
568 664e0f19 bellard
569 5af45186 bellard
#define SSE_HELPER_S(name, F)\
570 5af45186 bellard
void helper_ ## name ## ps (Reg *d, Reg *s)\
571 664e0f19 bellard
{\
572 7a0e1f41 bellard
    d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0));\
573 7a0e1f41 bellard
    d->XMM_S(1) = F(32, d->XMM_S(1), s->XMM_S(1));\
574 7a0e1f41 bellard
    d->XMM_S(2) = F(32, d->XMM_S(2), s->XMM_S(2));\
575 7a0e1f41 bellard
    d->XMM_S(3) = F(32, d->XMM_S(3), s->XMM_S(3));\
576 664e0f19 bellard
}\
577 664e0f19 bellard
\
578 5af45186 bellard
void helper_ ## name ## ss (Reg *d, Reg *s)\
579 664e0f19 bellard
{\
580 7a0e1f41 bellard
    d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0));\
581 664e0f19 bellard
}\
582 5af45186 bellard
void helper_ ## name ## pd (Reg *d, Reg *s)\
583 664e0f19 bellard
{\
584 7a0e1f41 bellard
    d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0));\
585 7a0e1f41 bellard
    d->XMM_D(1) = F(64, d->XMM_D(1), s->XMM_D(1));\
586 664e0f19 bellard
}\
587 664e0f19 bellard
\
588 5af45186 bellard
void helper_ ## name ## sd (Reg *d, Reg *s)\
589 664e0f19 bellard
{\
590 7a0e1f41 bellard
    d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0));\
591 664e0f19 bellard
}
592 664e0f19 bellard
593 7a0e1f41 bellard
#define FPU_ADD(size, a, b) float ## size ## _add(a, b, &env->sse_status)
594 7a0e1f41 bellard
#define FPU_SUB(size, a, b) float ## size ## _sub(a, b, &env->sse_status)
595 7a0e1f41 bellard
#define FPU_MUL(size, a, b) float ## size ## _mul(a, b, &env->sse_status)
596 7a0e1f41 bellard
#define FPU_DIV(size, a, b) float ## size ## _div(a, b, &env->sse_status)
597 7a0e1f41 bellard
#define FPU_MIN(size, a, b) (a) < (b) ? (a) : (b)
598 7a0e1f41 bellard
#define FPU_MAX(size, a, b) (a) > (b) ? (a) : (b)
599 7a0e1f41 bellard
#define FPU_SQRT(size, a, b) float ## size ## _sqrt(b, &env->sse_status)
600 664e0f19 bellard
601 5af45186 bellard
SSE_HELPER_S(add, FPU_ADD)
602 5af45186 bellard
SSE_HELPER_S(sub, FPU_SUB)
603 5af45186 bellard
SSE_HELPER_S(mul, FPU_MUL)
604 5af45186 bellard
SSE_HELPER_S(div, FPU_DIV)
605 5af45186 bellard
SSE_HELPER_S(min, FPU_MIN)
606 5af45186 bellard
SSE_HELPER_S(max, FPU_MAX)
607 5af45186 bellard
SSE_HELPER_S(sqrt, FPU_SQRT)
608 664e0f19 bellard
609 664e0f19 bellard
610 664e0f19 bellard
/* float to float conversions */
611 5af45186 bellard
void helper_cvtps2pd(Reg *d, Reg *s)
612 664e0f19 bellard
{
613 8422b113 bellard
    float32 s0, s1;
614 664e0f19 bellard
    s0 = s->XMM_S(0);
615 664e0f19 bellard
    s1 = s->XMM_S(1);
616 7a0e1f41 bellard
    d->XMM_D(0) = float32_to_float64(s0, &env->sse_status);
617 7a0e1f41 bellard
    d->XMM_D(1) = float32_to_float64(s1, &env->sse_status);
618 664e0f19 bellard
}
619 664e0f19 bellard
620 5af45186 bellard
void helper_cvtpd2ps(Reg *d, Reg *s)
621 664e0f19 bellard
{
622 7a0e1f41 bellard
    d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status);
623 7a0e1f41 bellard
    d->XMM_S(1) = float64_to_float32(s->XMM_D(1), &env->sse_status);
624 664e0f19 bellard
    d->Q(1) = 0;
625 664e0f19 bellard
}
626 664e0f19 bellard
627 5af45186 bellard
void helper_cvtss2sd(Reg *d, Reg *s)
628 664e0f19 bellard
{
629 7a0e1f41 bellard
    d->XMM_D(0) = float32_to_float64(s->XMM_S(0), &env->sse_status);
630 664e0f19 bellard
}
631 664e0f19 bellard
632 5af45186 bellard
void helper_cvtsd2ss(Reg *d, Reg *s)
633 664e0f19 bellard
{
634 7a0e1f41 bellard
    d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status);
635 664e0f19 bellard
}
636 664e0f19 bellard
637 664e0f19 bellard
/* integer to float */
638 5af45186 bellard
void helper_cvtdq2ps(Reg *d, Reg *s)
639 664e0f19 bellard
{
640 7a0e1f41 bellard
    d->XMM_S(0) = int32_to_float32(s->XMM_L(0), &env->sse_status);
641 7a0e1f41 bellard
    d->XMM_S(1) = int32_to_float32(s->XMM_L(1), &env->sse_status);
642 7a0e1f41 bellard
    d->XMM_S(2) = int32_to_float32(s->XMM_L(2), &env->sse_status);
643 7a0e1f41 bellard
    d->XMM_S(3) = int32_to_float32(s->XMM_L(3), &env->sse_status);
644 664e0f19 bellard
}
645 664e0f19 bellard
646 5af45186 bellard
void helper_cvtdq2pd(Reg *d, Reg *s)
647 664e0f19 bellard
{
648 664e0f19 bellard
    int32_t l0, l1;
649 664e0f19 bellard
    l0 = (int32_t)s->XMM_L(0);
650 664e0f19 bellard
    l1 = (int32_t)s->XMM_L(1);
651 7a0e1f41 bellard
    d->XMM_D(0) = int32_to_float64(l0, &env->sse_status);
652 7a0e1f41 bellard
    d->XMM_D(1) = int32_to_float64(l1, &env->sse_status);
653 664e0f19 bellard
}
654 664e0f19 bellard
655 5af45186 bellard
void helper_cvtpi2ps(XMMReg *d, MMXReg *s)
656 664e0f19 bellard
{
657 7a0e1f41 bellard
    d->XMM_S(0) = int32_to_float32(s->MMX_L(0), &env->sse_status);
658 7a0e1f41 bellard
    d->XMM_S(1) = int32_to_float32(s->MMX_L(1), &env->sse_status);
659 664e0f19 bellard
}
660 664e0f19 bellard
661 5af45186 bellard
void helper_cvtpi2pd(XMMReg *d, MMXReg *s)
662 664e0f19 bellard
{
663 7a0e1f41 bellard
    d->XMM_D(0) = int32_to_float64(s->MMX_L(0), &env->sse_status);
664 7a0e1f41 bellard
    d->XMM_D(1) = int32_to_float64(s->MMX_L(1), &env->sse_status);
665 664e0f19 bellard
}
666 664e0f19 bellard
667 5af45186 bellard
void helper_cvtsi2ss(XMMReg *d, uint32_t val)
668 664e0f19 bellard
{
669 5af45186 bellard
    d->XMM_S(0) = int32_to_float32(val, &env->sse_status);
670 664e0f19 bellard
}
671 664e0f19 bellard
672 5af45186 bellard
void helper_cvtsi2sd(XMMReg *d, uint32_t val)
673 664e0f19 bellard
{
674 5af45186 bellard
    d->XMM_D(0) = int32_to_float64(val, &env->sse_status);
675 664e0f19 bellard
}
676 664e0f19 bellard
677 664e0f19 bellard
#ifdef TARGET_X86_64
678 5af45186 bellard
void helper_cvtsq2ss(XMMReg *d, uint64_t val)
679 664e0f19 bellard
{
680 5af45186 bellard
    d->XMM_S(0) = int64_to_float32(val, &env->sse_status);
681 664e0f19 bellard
}
682 664e0f19 bellard
683 5af45186 bellard
void helper_cvtsq2sd(XMMReg *d, uint64_t val)
684 664e0f19 bellard
{
685 5af45186 bellard
    d->XMM_D(0) = int64_to_float64(val, &env->sse_status);
686 664e0f19 bellard
}
687 664e0f19 bellard
#endif
688 664e0f19 bellard
689 664e0f19 bellard
/* float to integer */
690 5af45186 bellard
void helper_cvtps2dq(XMMReg *d, XMMReg *s)
691 664e0f19 bellard
{
692 7a0e1f41 bellard
    d->XMM_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status);
693 7a0e1f41 bellard
    d->XMM_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status);
694 7a0e1f41 bellard
    d->XMM_L(2) = float32_to_int32(s->XMM_S(2), &env->sse_status);
695 7a0e1f41 bellard
    d->XMM_L(3) = float32_to_int32(s->XMM_S(3), &env->sse_status);
696 664e0f19 bellard
}
697 664e0f19 bellard
698 5af45186 bellard
void helper_cvtpd2dq(XMMReg *d, XMMReg *s)
699 664e0f19 bellard
{
700 7a0e1f41 bellard
    d->XMM_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status);
701 7a0e1f41 bellard
    d->XMM_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status);
702 664e0f19 bellard
    d->XMM_Q(1) = 0;
703 664e0f19 bellard
}
704 664e0f19 bellard
705 5af45186 bellard
void helper_cvtps2pi(MMXReg *d, XMMReg *s)
706 664e0f19 bellard
{
707 7a0e1f41 bellard
    d->MMX_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status);
708 7a0e1f41 bellard
    d->MMX_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status);
709 664e0f19 bellard
}
710 664e0f19 bellard
711 5af45186 bellard
void helper_cvtpd2pi(MMXReg *d, XMMReg *s)
712 664e0f19 bellard
{
713 7a0e1f41 bellard
    d->MMX_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status);
714 7a0e1f41 bellard
    d->MMX_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status);
715 664e0f19 bellard
}
716 664e0f19 bellard
717 5af45186 bellard
int32_t helper_cvtss2si(XMMReg *s)
718 664e0f19 bellard
{
719 5af45186 bellard
    return float32_to_int32(s->XMM_S(0), &env->sse_status);
720 664e0f19 bellard
}
721 664e0f19 bellard
722 5af45186 bellard
int32_t helper_cvtsd2si(XMMReg *s)
723 664e0f19 bellard
{
724 5af45186 bellard
    return float64_to_int32(s->XMM_D(0), &env->sse_status);
725 664e0f19 bellard
}
726 664e0f19 bellard
727 664e0f19 bellard
#ifdef TARGET_X86_64
728 5af45186 bellard
int64_t helper_cvtss2sq(XMMReg *s)
729 664e0f19 bellard
{
730 5af45186 bellard
    return float32_to_int64(s->XMM_S(0), &env->sse_status);
731 664e0f19 bellard
}
732 664e0f19 bellard
733 5af45186 bellard
int64_t helper_cvtsd2sq(XMMReg *s)
734 664e0f19 bellard
{
735 5af45186 bellard
    return float64_to_int64(s->XMM_D(0), &env->sse_status);
736 664e0f19 bellard
}
737 664e0f19 bellard
#endif
738 664e0f19 bellard
739 664e0f19 bellard
/* float to integer truncated */
740 5af45186 bellard
void helper_cvttps2dq(XMMReg *d, XMMReg *s)
741 664e0f19 bellard
{
742 7a0e1f41 bellard
    d->XMM_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
743 7a0e1f41 bellard
    d->XMM_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status);
744 7a0e1f41 bellard
    d->XMM_L(2) = float32_to_int32_round_to_zero(s->XMM_S(2), &env->sse_status);
745 7a0e1f41 bellard
    d->XMM_L(3) = float32_to_int32_round_to_zero(s->XMM_S(3), &env->sse_status);
746 664e0f19 bellard
}
747 664e0f19 bellard
748 5af45186 bellard
void helper_cvttpd2dq(XMMReg *d, XMMReg *s)
749 664e0f19 bellard
{
750 7a0e1f41 bellard
    d->XMM_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
751 7a0e1f41 bellard
    d->XMM_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status);
752 664e0f19 bellard
    d->XMM_Q(1) = 0;
753 664e0f19 bellard
}
754 664e0f19 bellard
755 5af45186 bellard
void helper_cvttps2pi(MMXReg *d, XMMReg *s)
756 664e0f19 bellard
{
757 7a0e1f41 bellard
    d->MMX_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
758 7a0e1f41 bellard
    d->MMX_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status);
759 664e0f19 bellard
}
760 664e0f19 bellard
761 5af45186 bellard
void helper_cvttpd2pi(MMXReg *d, XMMReg *s)
762 664e0f19 bellard
{
763 7a0e1f41 bellard
    d->MMX_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
764 7a0e1f41 bellard
    d->MMX_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status);
765 664e0f19 bellard
}
766 664e0f19 bellard
767 5af45186 bellard
int32_t helper_cvttss2si(XMMReg *s)
768 664e0f19 bellard
{
769 5af45186 bellard
    return float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
770 664e0f19 bellard
}
771 664e0f19 bellard
772 5af45186 bellard
int32_t helper_cvttsd2si(XMMReg *s)
773 664e0f19 bellard
{
774 5af45186 bellard
    return float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
775 664e0f19 bellard
}
776 664e0f19 bellard
777 664e0f19 bellard
#ifdef TARGET_X86_64
778 5af45186 bellard
int64_t helper_cvttss2sq(XMMReg *s)
779 664e0f19 bellard
{
780 5af45186 bellard
    return float32_to_int64_round_to_zero(s->XMM_S(0), &env->sse_status);
781 664e0f19 bellard
}
782 664e0f19 bellard
783 5af45186 bellard
int64_t helper_cvttsd2sq(XMMReg *s)
784 664e0f19 bellard
{
785 5af45186 bellard
    return float64_to_int64_round_to_zero(s->XMM_D(0), &env->sse_status);
786 664e0f19 bellard
}
787 664e0f19 bellard
#endif
788 664e0f19 bellard
789 5af45186 bellard
void helper_rsqrtps(XMMReg *d, XMMReg *s)
790 664e0f19 bellard
{
791 664e0f19 bellard
    d->XMM_S(0) = approx_rsqrt(s->XMM_S(0));
792 664e0f19 bellard
    d->XMM_S(1) = approx_rsqrt(s->XMM_S(1));
793 664e0f19 bellard
    d->XMM_S(2) = approx_rsqrt(s->XMM_S(2));
794 664e0f19 bellard
    d->XMM_S(3) = approx_rsqrt(s->XMM_S(3));
795 664e0f19 bellard
}
796 664e0f19 bellard
797 5af45186 bellard
void helper_rsqrtss(XMMReg *d, XMMReg *s)
798 664e0f19 bellard
{
799 664e0f19 bellard
    d->XMM_S(0) = approx_rsqrt(s->XMM_S(0));
800 664e0f19 bellard
}
801 664e0f19 bellard
802 5af45186 bellard
void helper_rcpps(XMMReg *d, XMMReg *s)
803 664e0f19 bellard
{
804 664e0f19 bellard
    d->XMM_S(0) = approx_rcp(s->XMM_S(0));
805 664e0f19 bellard
    d->XMM_S(1) = approx_rcp(s->XMM_S(1));
806 664e0f19 bellard
    d->XMM_S(2) = approx_rcp(s->XMM_S(2));
807 664e0f19 bellard
    d->XMM_S(3) = approx_rcp(s->XMM_S(3));
808 664e0f19 bellard
}
809 664e0f19 bellard
810 5af45186 bellard
void helper_rcpss(XMMReg *d, XMMReg *s)
811 664e0f19 bellard
{
812 664e0f19 bellard
    d->XMM_S(0) = approx_rcp(s->XMM_S(0));
813 664e0f19 bellard
}
814 664e0f19 bellard
815 5af45186 bellard
void helper_haddps(XMMReg *d, XMMReg *s)
816 664e0f19 bellard
{
817 664e0f19 bellard
    XMMReg r;
818 664e0f19 bellard
    r.XMM_S(0) = d->XMM_S(0) + d->XMM_S(1);
819 664e0f19 bellard
    r.XMM_S(1) = d->XMM_S(2) + d->XMM_S(3);
820 664e0f19 bellard
    r.XMM_S(2) = s->XMM_S(0) + s->XMM_S(1);
821 664e0f19 bellard
    r.XMM_S(3) = s->XMM_S(2) + s->XMM_S(3);
822 664e0f19 bellard
    *d = r;
823 664e0f19 bellard
}
824 664e0f19 bellard
825 5af45186 bellard
void helper_haddpd(XMMReg *d, XMMReg *s)
826 664e0f19 bellard
{
827 664e0f19 bellard
    XMMReg r;
828 664e0f19 bellard
    r.XMM_D(0) = d->XMM_D(0) + d->XMM_D(1);
829 664e0f19 bellard
    r.XMM_D(1) = s->XMM_D(0) + s->XMM_D(1);
830 664e0f19 bellard
    *d = r;
831 664e0f19 bellard
}
832 664e0f19 bellard
833 5af45186 bellard
void helper_hsubps(XMMReg *d, XMMReg *s)
834 664e0f19 bellard
{
835 664e0f19 bellard
    XMMReg r;
836 664e0f19 bellard
    r.XMM_S(0) = d->XMM_S(0) - d->XMM_S(1);
837 664e0f19 bellard
    r.XMM_S(1) = d->XMM_S(2) - d->XMM_S(3);
838 664e0f19 bellard
    r.XMM_S(2) = s->XMM_S(0) - s->XMM_S(1);
839 664e0f19 bellard
    r.XMM_S(3) = s->XMM_S(2) - s->XMM_S(3);
840 664e0f19 bellard
    *d = r;
841 664e0f19 bellard
}
842 664e0f19 bellard
843 5af45186 bellard
void helper_hsubpd(XMMReg *d, XMMReg *s)
844 664e0f19 bellard
{
845 664e0f19 bellard
    XMMReg r;
846 664e0f19 bellard
    r.XMM_D(0) = d->XMM_D(0) - d->XMM_D(1);
847 664e0f19 bellard
    r.XMM_D(1) = s->XMM_D(0) - s->XMM_D(1);
848 664e0f19 bellard
    *d = r;
849 664e0f19 bellard
}
850 664e0f19 bellard
851 5af45186 bellard
void helper_addsubps(XMMReg *d, XMMReg *s)
852 664e0f19 bellard
{
853 664e0f19 bellard
    d->XMM_S(0) = d->XMM_S(0) - s->XMM_S(0);
854 664e0f19 bellard
    d->XMM_S(1) = d->XMM_S(1) + s->XMM_S(1);
855 664e0f19 bellard
    d->XMM_S(2) = d->XMM_S(2) - s->XMM_S(2);
856 664e0f19 bellard
    d->XMM_S(3) = d->XMM_S(3) + s->XMM_S(3);
857 664e0f19 bellard
}
858 664e0f19 bellard
859 5af45186 bellard
void helper_addsubpd(XMMReg *d, XMMReg *s)
860 664e0f19 bellard
{
861 664e0f19 bellard
    d->XMM_D(0) = d->XMM_D(0) - s->XMM_D(0);
862 664e0f19 bellard
    d->XMM_D(1) = d->XMM_D(1) + s->XMM_D(1);
863 664e0f19 bellard
}
864 664e0f19 bellard
865 664e0f19 bellard
/* XXX: unordered */
866 5af45186 bellard
#define SSE_HELPER_CMP(name, F)\
867 5af45186 bellard
void helper_ ## name ## ps (Reg *d, Reg *s)\
868 664e0f19 bellard
{\
869 8422b113 bellard
    d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0));\
870 8422b113 bellard
    d->XMM_L(1) = F(32, d->XMM_S(1), s->XMM_S(1));\
871 8422b113 bellard
    d->XMM_L(2) = F(32, d->XMM_S(2), s->XMM_S(2));\
872 8422b113 bellard
    d->XMM_L(3) = F(32, d->XMM_S(3), s->XMM_S(3));\
873 664e0f19 bellard
}\
874 664e0f19 bellard
\
875 5af45186 bellard
void helper_ ## name ## ss (Reg *d, Reg *s)\
876 664e0f19 bellard
{\
877 8422b113 bellard
    d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0));\
878 664e0f19 bellard
}\
879 5af45186 bellard
void helper_ ## name ## pd (Reg *d, Reg *s)\
880 664e0f19 bellard
{\
881 8422b113 bellard
    d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0));\
882 8422b113 bellard
    d->XMM_Q(1) = F(64, d->XMM_D(1), s->XMM_D(1));\
883 664e0f19 bellard
}\
884 664e0f19 bellard
\
885 5af45186 bellard
void helper_ ## name ## sd (Reg *d, Reg *s)\
886 664e0f19 bellard
{\
887 8422b113 bellard
    d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0));\
888 664e0f19 bellard
}
889 664e0f19 bellard
890 8422b113 bellard
#define FPU_CMPEQ(size, a, b) float ## size ## _eq(a, b, &env->sse_status) ? -1 : 0
891 8422b113 bellard
#define FPU_CMPLT(size, a, b) float ## size ## _lt(a, b, &env->sse_status) ? -1 : 0
892 8422b113 bellard
#define FPU_CMPLE(size, a, b) float ## size ## _le(a, b, &env->sse_status) ? -1 : 0
893 8422b113 bellard
#define FPU_CMPUNORD(size, a, b) float ## size ## _unordered(a, b, &env->sse_status) ? - 1 : 0
894 8422b113 bellard
#define FPU_CMPNEQ(size, a, b) float ## size ## _eq(a, b, &env->sse_status) ? 0 : -1
895 8422b113 bellard
#define FPU_CMPNLT(size, a, b) float ## size ## _lt(a, b, &env->sse_status) ? 0 : -1
896 8422b113 bellard
#define FPU_CMPNLE(size, a, b) float ## size ## _le(a, b, &env->sse_status) ? 0 : -1
897 8422b113 bellard
#define FPU_CMPORD(size, a, b) float ## size ## _unordered(a, b, &env->sse_status) ? 0 : -1
898 664e0f19 bellard
899 5af45186 bellard
SSE_HELPER_CMP(cmpeq, FPU_CMPEQ)
900 5af45186 bellard
SSE_HELPER_CMP(cmplt, FPU_CMPLT)
901 5af45186 bellard
SSE_HELPER_CMP(cmple, FPU_CMPLE)
902 5af45186 bellard
SSE_HELPER_CMP(cmpunord, FPU_CMPUNORD)
903 5af45186 bellard
SSE_HELPER_CMP(cmpneq, FPU_CMPNEQ)
904 5af45186 bellard
SSE_HELPER_CMP(cmpnlt, FPU_CMPNLT)
905 5af45186 bellard
SSE_HELPER_CMP(cmpnle, FPU_CMPNLE)
906 5af45186 bellard
SSE_HELPER_CMP(cmpord, FPU_CMPORD)
907 664e0f19 bellard
908 43fb823b bellard
const int comis_eflags[4] = {CC_C, CC_Z, 0, CC_Z | CC_P | CC_C};
909 43fb823b bellard
910 5af45186 bellard
void helper_ucomiss(Reg *d, Reg *s)
911 664e0f19 bellard
{
912 43fb823b bellard
    int ret;
913 8422b113 bellard
    float32 s0, s1;
914 664e0f19 bellard
915 664e0f19 bellard
    s0 = d->XMM_S(0);
916 664e0f19 bellard
    s1 = s->XMM_S(0);
917 43fb823b bellard
    ret = float32_compare_quiet(s0, s1, &env->sse_status);
918 43fb823b bellard
    CC_SRC = comis_eflags[ret + 1];
919 664e0f19 bellard
    FORCE_RET();
920 664e0f19 bellard
}
921 664e0f19 bellard
922 5af45186 bellard
void helper_comiss(Reg *d, Reg *s)
923 664e0f19 bellard
{
924 43fb823b bellard
    int ret;
925 8422b113 bellard
    float32 s0, s1;
926 664e0f19 bellard
927 664e0f19 bellard
    s0 = d->XMM_S(0);
928 664e0f19 bellard
    s1 = s->XMM_S(0);
929 43fb823b bellard
    ret = float32_compare(s0, s1, &env->sse_status);
930 43fb823b bellard
    CC_SRC = comis_eflags[ret + 1];
931 664e0f19 bellard
    FORCE_RET();
932 664e0f19 bellard
}
933 664e0f19 bellard
934 5af45186 bellard
void helper_ucomisd(Reg *d, Reg *s)
935 664e0f19 bellard
{
936 43fb823b bellard
    int ret;
937 8422b113 bellard
    float64 d0, d1;
938 664e0f19 bellard
939 664e0f19 bellard
    d0 = d->XMM_D(0);
940 664e0f19 bellard
    d1 = s->XMM_D(0);
941 43fb823b bellard
    ret = float64_compare_quiet(d0, d1, &env->sse_status);
942 43fb823b bellard
    CC_SRC = comis_eflags[ret + 1];
943 664e0f19 bellard
    FORCE_RET();
944 664e0f19 bellard
}
945 664e0f19 bellard
946 5af45186 bellard
void helper_comisd(Reg *d, Reg *s)
947 664e0f19 bellard
{
948 43fb823b bellard
    int ret;
949 8422b113 bellard
    float64 d0, d1;
950 664e0f19 bellard
951 664e0f19 bellard
    d0 = d->XMM_D(0);
952 664e0f19 bellard
    d1 = s->XMM_D(0);
953 43fb823b bellard
    ret = float64_compare(d0, d1, &env->sse_status);
954 43fb823b bellard
    CC_SRC = comis_eflags[ret + 1];
955 664e0f19 bellard
    FORCE_RET();
956 664e0f19 bellard
}
957 664e0f19 bellard
958 5af45186 bellard
uint32_t helper_movmskps(Reg *s)
959 664e0f19 bellard
{
960 664e0f19 bellard
    int b0, b1, b2, b3;
961 664e0f19 bellard
    b0 = s->XMM_L(0) >> 31;
962 664e0f19 bellard
    b1 = s->XMM_L(1) >> 31;
963 664e0f19 bellard
    b2 = s->XMM_L(2) >> 31;
964 664e0f19 bellard
    b3 = s->XMM_L(3) >> 31;
965 5af45186 bellard
    return b0 | (b1 << 1) | (b2 << 2) | (b3 << 3);
966 664e0f19 bellard
}
967 664e0f19 bellard
968 5af45186 bellard
uint32_t helper_movmskpd(Reg *s)
969 664e0f19 bellard
{
970 664e0f19 bellard
    int b0, b1;
971 664e0f19 bellard
    b0 = s->XMM_L(1) >> 31;
972 664e0f19 bellard
    b1 = s->XMM_L(3) >> 31;
973 5af45186 bellard
    return b0 | (b1 << 1);
974 664e0f19 bellard
}
975 664e0f19 bellard
976 664e0f19 bellard
#endif
977 664e0f19 bellard
978 5af45186 bellard
uint32_t glue(helper_pmovmskb, SUFFIX)(Reg *s)
979 5af45186 bellard
{
980 5af45186 bellard
    uint32_t val;
981 5af45186 bellard
    val = 0;
982 5af45186 bellard
    val |= (s->XMM_B(0) >> 7);
983 5af45186 bellard
    val |= (s->XMM_B(1) >> 6) & 0x02;
984 5af45186 bellard
    val |= (s->XMM_B(2) >> 5) & 0x04;
985 5af45186 bellard
    val |= (s->XMM_B(3) >> 4) & 0x08;
986 5af45186 bellard
    val |= (s->XMM_B(4) >> 3) & 0x10;
987 5af45186 bellard
    val |= (s->XMM_B(5) >> 2) & 0x20;
988 5af45186 bellard
    val |= (s->XMM_B(6) >> 1) & 0x40;
989 5af45186 bellard
    val |= (s->XMM_B(7)) & 0x80;
990 664e0f19 bellard
#if SHIFT == 1
991 5af45186 bellard
    val |= (s->XMM_B(8) << 1) & 0x0100;
992 5af45186 bellard
    val |= (s->XMM_B(9) << 2) & 0x0200;
993 5af45186 bellard
    val |= (s->XMM_B(10) << 3) & 0x0400;
994 5af45186 bellard
    val |= (s->XMM_B(11) << 4) & 0x0800;
995 5af45186 bellard
    val |= (s->XMM_B(12) << 5) & 0x1000;
996 5af45186 bellard
    val |= (s->XMM_B(13) << 6) & 0x2000;
997 5af45186 bellard
    val |= (s->XMM_B(14) << 7) & 0x4000;
998 5af45186 bellard
    val |= (s->XMM_B(15) << 8) & 0x8000;
999 664e0f19 bellard
#endif
1000 5af45186 bellard
    return val;
1001 664e0f19 bellard
}
1002 664e0f19 bellard
1003 5af45186 bellard
void glue(helper_packsswb, SUFFIX) (Reg *d, Reg *s)
1004 664e0f19 bellard
{
1005 5af45186 bellard
    Reg r;
1006 664e0f19 bellard
1007 664e0f19 bellard
    r.B(0) = satsb((int16_t)d->W(0));
1008 664e0f19 bellard
    r.B(1) = satsb((int16_t)d->W(1));
1009 664e0f19 bellard
    r.B(2) = satsb((int16_t)d->W(2));
1010 664e0f19 bellard
    r.B(3) = satsb((int16_t)d->W(3));
1011 664e0f19 bellard
#if SHIFT == 1
1012 664e0f19 bellard
    r.B(4) = satsb((int16_t)d->W(4));
1013 664e0f19 bellard
    r.B(5) = satsb((int16_t)d->W(5));
1014 664e0f19 bellard
    r.B(6) = satsb((int16_t)d->W(6));
1015 664e0f19 bellard
    r.B(7) = satsb((int16_t)d->W(7));
1016 664e0f19 bellard
#endif
1017 664e0f19 bellard
    r.B((4 << SHIFT) + 0) = satsb((int16_t)s->W(0));
1018 664e0f19 bellard
    r.B((4 << SHIFT) + 1) = satsb((int16_t)s->W(1));
1019 664e0f19 bellard
    r.B((4 << SHIFT) + 2) = satsb((int16_t)s->W(2));
1020 664e0f19 bellard
    r.B((4 << SHIFT) + 3) = satsb((int16_t)s->W(3));
1021 664e0f19 bellard
#if SHIFT == 1
1022 664e0f19 bellard
    r.B(12) = satsb((int16_t)s->W(4));
1023 664e0f19 bellard
    r.B(13) = satsb((int16_t)s->W(5));
1024 664e0f19 bellard
    r.B(14) = satsb((int16_t)s->W(6));
1025 664e0f19 bellard
    r.B(15) = satsb((int16_t)s->W(7));
1026 664e0f19 bellard
#endif
1027 664e0f19 bellard
    *d = r;
1028 664e0f19 bellard
}
1029 664e0f19 bellard
1030 5af45186 bellard
void glue(helper_packuswb, SUFFIX) (Reg *d, Reg *s)
1031 664e0f19 bellard
{
1032 5af45186 bellard
    Reg r;
1033 664e0f19 bellard
1034 664e0f19 bellard
    r.B(0) = satub((int16_t)d->W(0));
1035 664e0f19 bellard
    r.B(1) = satub((int16_t)d->W(1));
1036 664e0f19 bellard
    r.B(2) = satub((int16_t)d->W(2));
1037 664e0f19 bellard
    r.B(3) = satub((int16_t)d->W(3));
1038 664e0f19 bellard
#if SHIFT == 1
1039 664e0f19 bellard
    r.B(4) = satub((int16_t)d->W(4));
1040 664e0f19 bellard
    r.B(5) = satub((int16_t)d->W(5));
1041 664e0f19 bellard
    r.B(6) = satub((int16_t)d->W(6));
1042 664e0f19 bellard
    r.B(7) = satub((int16_t)d->W(7));
1043 664e0f19 bellard
#endif
1044 664e0f19 bellard
    r.B((4 << SHIFT) + 0) = satub((int16_t)s->W(0));
1045 664e0f19 bellard
    r.B((4 << SHIFT) + 1) = satub((int16_t)s->W(1));
1046 664e0f19 bellard
    r.B((4 << SHIFT) + 2) = satub((int16_t)s->W(2));
1047 664e0f19 bellard
    r.B((4 << SHIFT) + 3) = satub((int16_t)s->W(3));
1048 664e0f19 bellard
#if SHIFT == 1
1049 664e0f19 bellard
    r.B(12) = satub((int16_t)s->W(4));
1050 664e0f19 bellard
    r.B(13) = satub((int16_t)s->W(5));
1051 664e0f19 bellard
    r.B(14) = satub((int16_t)s->W(6));
1052 664e0f19 bellard
    r.B(15) = satub((int16_t)s->W(7));
1053 664e0f19 bellard
#endif
1054 664e0f19 bellard
    *d = r;
1055 664e0f19 bellard
}
1056 664e0f19 bellard
1057 5af45186 bellard
void glue(helper_packssdw, SUFFIX) (Reg *d, Reg *s)
1058 664e0f19 bellard
{
1059 5af45186 bellard
    Reg r;
1060 664e0f19 bellard
1061 664e0f19 bellard
    r.W(0) = satsw(d->L(0));
1062 664e0f19 bellard
    r.W(1) = satsw(d->L(1));
1063 664e0f19 bellard
#if SHIFT == 1
1064 664e0f19 bellard
    r.W(2) = satsw(d->L(2));
1065 664e0f19 bellard
    r.W(3) = satsw(d->L(3));
1066 664e0f19 bellard
#endif
1067 664e0f19 bellard
    r.W((2 << SHIFT) + 0) = satsw(s->L(0));
1068 664e0f19 bellard
    r.W((2 << SHIFT) + 1) = satsw(s->L(1));
1069 664e0f19 bellard
#if SHIFT == 1
1070 664e0f19 bellard
    r.W(6) = satsw(s->L(2));
1071 664e0f19 bellard
    r.W(7) = satsw(s->L(3));
1072 664e0f19 bellard
#endif
1073 664e0f19 bellard
    *d = r;
1074 664e0f19 bellard
}
1075 664e0f19 bellard
1076 664e0f19 bellard
#define UNPCK_OP(base_name, base)                               \
1077 664e0f19 bellard
                                                                \
1078 5af45186 bellard
void glue(helper_punpck ## base_name ## bw, SUFFIX) (Reg *d, Reg *s)   \
1079 664e0f19 bellard
{                                                               \
1080 5af45186 bellard
    Reg r;                                              \
1081 664e0f19 bellard
                                                                \
1082 664e0f19 bellard
    r.B(0) = d->B((base << (SHIFT + 2)) + 0);                   \
1083 664e0f19 bellard
    r.B(1) = s->B((base << (SHIFT + 2)) + 0);                   \
1084 664e0f19 bellard
    r.B(2) = d->B((base << (SHIFT + 2)) + 1);                   \
1085 664e0f19 bellard
    r.B(3) = s->B((base << (SHIFT + 2)) + 1);                   \
1086 664e0f19 bellard
    r.B(4) = d->B((base << (SHIFT + 2)) + 2);                   \
1087 664e0f19 bellard
    r.B(5) = s->B((base << (SHIFT + 2)) + 2);                   \
1088 664e0f19 bellard
    r.B(6) = d->B((base << (SHIFT + 2)) + 3);                   \
1089 664e0f19 bellard
    r.B(7) = s->B((base << (SHIFT + 2)) + 3);                   \
1090 664e0f19 bellard
XMM_ONLY(                                                       \
1091 664e0f19 bellard
    r.B(8) = d->B((base << (SHIFT + 2)) + 4);                   \
1092 664e0f19 bellard
    r.B(9) = s->B((base << (SHIFT + 2)) + 4);                   \
1093 664e0f19 bellard
    r.B(10) = d->B((base << (SHIFT + 2)) + 5);                  \
1094 664e0f19 bellard
    r.B(11) = s->B((base << (SHIFT + 2)) + 5);                  \
1095 664e0f19 bellard
    r.B(12) = d->B((base << (SHIFT + 2)) + 6);                  \
1096 664e0f19 bellard
    r.B(13) = s->B((base << (SHIFT + 2)) + 6);                  \
1097 664e0f19 bellard
    r.B(14) = d->B((base << (SHIFT + 2)) + 7);                  \
1098 664e0f19 bellard
    r.B(15) = s->B((base << (SHIFT + 2)) + 7);                  \
1099 664e0f19 bellard
)                                                               \
1100 664e0f19 bellard
    *d = r;                                                     \
1101 664e0f19 bellard
}                                                               \
1102 664e0f19 bellard
                                                                \
1103 5af45186 bellard
void glue(helper_punpck ## base_name ## wd, SUFFIX) (Reg *d, Reg *s)   \
1104 664e0f19 bellard
{                                                               \
1105 5af45186 bellard
    Reg r;                                              \
1106 664e0f19 bellard
                                                                \
1107 664e0f19 bellard
    r.W(0) = d->W((base << (SHIFT + 1)) + 0);                   \
1108 664e0f19 bellard
    r.W(1) = s->W((base << (SHIFT + 1)) + 0);                   \
1109 664e0f19 bellard
    r.W(2) = d->W((base << (SHIFT + 1)) + 1);                   \
1110 664e0f19 bellard
    r.W(3) = s->W((base << (SHIFT + 1)) + 1);                   \
1111 664e0f19 bellard
XMM_ONLY(                                                       \
1112 664e0f19 bellard
    r.W(4) = d->W((base << (SHIFT + 1)) + 2);                   \
1113 664e0f19 bellard
    r.W(5) = s->W((base << (SHIFT + 1)) + 2);                   \
1114 664e0f19 bellard
    r.W(6) = d->W((base << (SHIFT + 1)) + 3);                   \
1115 664e0f19 bellard
    r.W(7) = s->W((base << (SHIFT + 1)) + 3);                   \
1116 664e0f19 bellard
)                                                               \
1117 664e0f19 bellard
    *d = r;                                                     \
1118 664e0f19 bellard
}                                                               \
1119 664e0f19 bellard
                                                                \
1120 5af45186 bellard
void glue(helper_punpck ## base_name ## dq, SUFFIX) (Reg *d, Reg *s)   \
1121 664e0f19 bellard
{                                                               \
1122 5af45186 bellard
    Reg r;                                              \
1123 664e0f19 bellard
                                                                \
1124 664e0f19 bellard
    r.L(0) = d->L((base << SHIFT) + 0);                         \
1125 664e0f19 bellard
    r.L(1) = s->L((base << SHIFT) + 0);                         \
1126 664e0f19 bellard
XMM_ONLY(                                                       \
1127 664e0f19 bellard
    r.L(2) = d->L((base << SHIFT) + 1);                         \
1128 664e0f19 bellard
    r.L(3) = s->L((base << SHIFT) + 1);                         \
1129 664e0f19 bellard
)                                                               \
1130 664e0f19 bellard
    *d = r;                                                     \
1131 664e0f19 bellard
}                                                               \
1132 664e0f19 bellard
                                                                \
1133 664e0f19 bellard
XMM_ONLY(                                                       \
1134 5af45186 bellard
void glue(helper_punpck ## base_name ## qdq, SUFFIX) (Reg *d, Reg *s)  \
1135 664e0f19 bellard
{                                                               \
1136 5af45186 bellard
    Reg r;                                              \
1137 664e0f19 bellard
                                                                \
1138 664e0f19 bellard
    r.Q(0) = d->Q(base);                                        \
1139 664e0f19 bellard
    r.Q(1) = s->Q(base);                                        \
1140 664e0f19 bellard
    *d = r;                                                     \
1141 664e0f19 bellard
}                                                               \
1142 664e0f19 bellard
)
1143 664e0f19 bellard
1144 664e0f19 bellard
UNPCK_OP(l, 0)
1145 664e0f19 bellard
UNPCK_OP(h, 1)
1146 664e0f19 bellard
1147 a35f3ec7 aurel32
/* 3DNow! float ops */
1148 a35f3ec7 aurel32
#if SHIFT == 0
1149 5af45186 bellard
void helper_pi2fd(MMXReg *d, MMXReg *s)
1150 a35f3ec7 aurel32
{
1151 a35f3ec7 aurel32
    d->MMX_S(0) = int32_to_float32(s->MMX_L(0), &env->mmx_status);
1152 a35f3ec7 aurel32
    d->MMX_S(1) = int32_to_float32(s->MMX_L(1), &env->mmx_status);
1153 a35f3ec7 aurel32
}
1154 a35f3ec7 aurel32
1155 5af45186 bellard
void helper_pi2fw(MMXReg *d, MMXReg *s)
1156 a35f3ec7 aurel32
{
1157 a35f3ec7 aurel32
    d->MMX_S(0) = int32_to_float32((int16_t)s->MMX_W(0), &env->mmx_status);
1158 a35f3ec7 aurel32
    d->MMX_S(1) = int32_to_float32((int16_t)s->MMX_W(2), &env->mmx_status);
1159 a35f3ec7 aurel32
}
1160 a35f3ec7 aurel32
1161 5af45186 bellard
void helper_pf2id(MMXReg *d, MMXReg *s)
1162 a35f3ec7 aurel32
{
1163 a35f3ec7 aurel32
    d->MMX_L(0) = float32_to_int32_round_to_zero(s->MMX_S(0), &env->mmx_status);
1164 a35f3ec7 aurel32
    d->MMX_L(1) = float32_to_int32_round_to_zero(s->MMX_S(1), &env->mmx_status);
1165 a35f3ec7 aurel32
}
1166 a35f3ec7 aurel32
1167 5af45186 bellard
void helper_pf2iw(MMXReg *d, MMXReg *s)
1168 a35f3ec7 aurel32
{
1169 a35f3ec7 aurel32
    d->MMX_L(0) = satsw(float32_to_int32_round_to_zero(s->MMX_S(0), &env->mmx_status));
1170 a35f3ec7 aurel32
    d->MMX_L(1) = satsw(float32_to_int32_round_to_zero(s->MMX_S(1), &env->mmx_status));
1171 a35f3ec7 aurel32
}
1172 a35f3ec7 aurel32
1173 5af45186 bellard
void helper_pfacc(MMXReg *d, MMXReg *s)
1174 a35f3ec7 aurel32
{
1175 a35f3ec7 aurel32
    MMXReg r;
1176 a35f3ec7 aurel32
    r.MMX_S(0) = float32_add(d->MMX_S(0), d->MMX_S(1), &env->mmx_status);
1177 a35f3ec7 aurel32
    r.MMX_S(1) = float32_add(s->MMX_S(0), s->MMX_S(1), &env->mmx_status);
1178 a35f3ec7 aurel32
    *d = r;
1179 a35f3ec7 aurel32
}
1180 a35f3ec7 aurel32
1181 5af45186 bellard
void helper_pfadd(MMXReg *d, MMXReg *s)
1182 a35f3ec7 aurel32
{
1183 a35f3ec7 aurel32
    d->MMX_S(0) = float32_add(d->MMX_S(0), s->MMX_S(0), &env->mmx_status);
1184 a35f3ec7 aurel32
    d->MMX_S(1) = float32_add(d->MMX_S(1), s->MMX_S(1), &env->mmx_status);
1185 a35f3ec7 aurel32
}
1186 a35f3ec7 aurel32
1187 5af45186 bellard
void helper_pfcmpeq(MMXReg *d, MMXReg *s)
1188 a35f3ec7 aurel32
{
1189 a35f3ec7 aurel32
    d->MMX_L(0) = float32_eq(d->MMX_S(0), s->MMX_S(0), &env->mmx_status) ? -1 : 0;
1190 a35f3ec7 aurel32
    d->MMX_L(1) = float32_eq(d->MMX_S(1), s->MMX_S(1), &env->mmx_status) ? -1 : 0;
1191 a35f3ec7 aurel32
}
1192 a35f3ec7 aurel32
1193 5af45186 bellard
void helper_pfcmpge(MMXReg *d, MMXReg *s)
1194 a35f3ec7 aurel32
{
1195 a35f3ec7 aurel32
    d->MMX_L(0) = float32_le(s->MMX_S(0), d->MMX_S(0), &env->mmx_status) ? -1 : 0;
1196 a35f3ec7 aurel32
    d->MMX_L(1) = float32_le(s->MMX_S(1), d->MMX_S(1), &env->mmx_status) ? -1 : 0;
1197 a35f3ec7 aurel32
}
1198 a35f3ec7 aurel32
1199 5af45186 bellard
void helper_pfcmpgt(MMXReg *d, MMXReg *s)
1200 a35f3ec7 aurel32
{
1201 a35f3ec7 aurel32
    d->MMX_L(0) = float32_lt(s->MMX_S(0), d->MMX_S(0), &env->mmx_status) ? -1 : 0;
1202 a35f3ec7 aurel32
    d->MMX_L(1) = float32_lt(s->MMX_S(1), d->MMX_S(1), &env->mmx_status) ? -1 : 0;
1203 a35f3ec7 aurel32
}
1204 a35f3ec7 aurel32
1205 5af45186 bellard
void helper_pfmax(MMXReg *d, MMXReg *s)
1206 a35f3ec7 aurel32
{
1207 a35f3ec7 aurel32
    if (float32_lt(d->MMX_S(0), s->MMX_S(0), &env->mmx_status))
1208 a35f3ec7 aurel32
        d->MMX_S(0) = s->MMX_S(0);
1209 a35f3ec7 aurel32
    if (float32_lt(d->MMX_S(1), s->MMX_S(1), &env->mmx_status))
1210 a35f3ec7 aurel32
        d->MMX_S(1) = s->MMX_S(1);
1211 a35f3ec7 aurel32
}
1212 a35f3ec7 aurel32
1213 5af45186 bellard
void helper_pfmin(MMXReg *d, MMXReg *s)
1214 a35f3ec7 aurel32
{
1215 a35f3ec7 aurel32
    if (float32_lt(s->MMX_S(0), d->MMX_S(0), &env->mmx_status))
1216 a35f3ec7 aurel32
        d->MMX_S(0) = s->MMX_S(0);
1217 a35f3ec7 aurel32
    if (float32_lt(s->MMX_S(1), d->MMX_S(1), &env->mmx_status))
1218 a35f3ec7 aurel32
        d->MMX_S(1) = s->MMX_S(1);
1219 a35f3ec7 aurel32
}
1220 a35f3ec7 aurel32
1221 5af45186 bellard
void helper_pfmul(MMXReg *d, MMXReg *s)
1222 a35f3ec7 aurel32
{
1223 a35f3ec7 aurel32
    d->MMX_S(0) = float32_mul(d->MMX_S(0), s->MMX_S(0), &env->mmx_status);
1224 a35f3ec7 aurel32
    d->MMX_S(1) = float32_mul(d->MMX_S(1), s->MMX_S(1), &env->mmx_status);
1225 a35f3ec7 aurel32
}
1226 a35f3ec7 aurel32
1227 5af45186 bellard
void helper_pfnacc(MMXReg *d, MMXReg *s)
1228 a35f3ec7 aurel32
{
1229 a35f3ec7 aurel32
    MMXReg r;
1230 a35f3ec7 aurel32
    r.MMX_S(0) = float32_sub(d->MMX_S(0), d->MMX_S(1), &env->mmx_status);
1231 a35f3ec7 aurel32
    r.MMX_S(1) = float32_sub(s->MMX_S(0), s->MMX_S(1), &env->mmx_status);
1232 a35f3ec7 aurel32
    *d = r;
1233 a35f3ec7 aurel32
}
1234 a35f3ec7 aurel32
1235 5af45186 bellard
void helper_pfpnacc(MMXReg *d, MMXReg *s)
1236 a35f3ec7 aurel32
{
1237 a35f3ec7 aurel32
    MMXReg r;
1238 a35f3ec7 aurel32
    r.MMX_S(0) = float32_sub(d->MMX_S(0), d->MMX_S(1), &env->mmx_status);
1239 a35f3ec7 aurel32
    r.MMX_S(1) = float32_add(s->MMX_S(0), s->MMX_S(1), &env->mmx_status);
1240 a35f3ec7 aurel32
    *d = r;
1241 a35f3ec7 aurel32
}
1242 a35f3ec7 aurel32
1243 5af45186 bellard
void helper_pfrcp(MMXReg *d, MMXReg *s)
1244 a35f3ec7 aurel32
{
1245 a35f3ec7 aurel32
    d->MMX_S(0) = approx_rcp(s->MMX_S(0));
1246 a35f3ec7 aurel32
    d->MMX_S(1) = d->MMX_S(0);
1247 a35f3ec7 aurel32
}
1248 a35f3ec7 aurel32
1249 5af45186 bellard
void helper_pfrsqrt(MMXReg *d, MMXReg *s)
1250 a35f3ec7 aurel32
{
1251 a35f3ec7 aurel32
    d->MMX_L(1) = s->MMX_L(0) & 0x7fffffff;
1252 a35f3ec7 aurel32
    d->MMX_S(1) = approx_rsqrt(d->MMX_S(1));
1253 a35f3ec7 aurel32
    d->MMX_L(1) |= s->MMX_L(0) & 0x80000000;
1254 a35f3ec7 aurel32
    d->MMX_L(0) = d->MMX_L(1);
1255 a35f3ec7 aurel32
}
1256 a35f3ec7 aurel32
1257 5af45186 bellard
void helper_pfsub(MMXReg *d, MMXReg *s)
1258 a35f3ec7 aurel32
{
1259 a35f3ec7 aurel32
    d->MMX_S(0) = float32_sub(d->MMX_S(0), s->MMX_S(0), &env->mmx_status);
1260 a35f3ec7 aurel32
    d->MMX_S(1) = float32_sub(d->MMX_S(1), s->MMX_S(1), &env->mmx_status);
1261 a35f3ec7 aurel32
}
1262 a35f3ec7 aurel32
1263 5af45186 bellard
void helper_pfsubr(MMXReg *d, MMXReg *s)
1264 a35f3ec7 aurel32
{
1265 a35f3ec7 aurel32
    d->MMX_S(0) = float32_sub(s->MMX_S(0), d->MMX_S(0), &env->mmx_status);
1266 a35f3ec7 aurel32
    d->MMX_S(1) = float32_sub(s->MMX_S(1), d->MMX_S(1), &env->mmx_status);
1267 a35f3ec7 aurel32
}
1268 a35f3ec7 aurel32
1269 5af45186 bellard
void helper_pswapd(MMXReg *d, MMXReg *s)
1270 a35f3ec7 aurel32
{
1271 a35f3ec7 aurel32
    MMXReg r;
1272 a35f3ec7 aurel32
    r.MMX_L(0) = s->MMX_L(1);
1273 a35f3ec7 aurel32
    r.MMX_L(1) = s->MMX_L(0);
1274 a35f3ec7 aurel32
    *d = r;
1275 a35f3ec7 aurel32
}
1276 a35f3ec7 aurel32
#endif
1277 a35f3ec7 aurel32
1278 664e0f19 bellard
#undef SHIFT
1279 664e0f19 bellard
#undef XMM_ONLY
1280 664e0f19 bellard
#undef Reg
1281 664e0f19 bellard
#undef B
1282 664e0f19 bellard
#undef W
1283 664e0f19 bellard
#undef L
1284 664e0f19 bellard
#undef Q
1285 664e0f19 bellard
#undef SUFFIX