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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation helpers for qemu.
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | fdabc366 | bellard | #include <stdarg.h> |
21 | fdabc366 | bellard | #include <stdlib.h> |
22 | fdabc366 | bellard | #include <stdio.h> |
23 | fdabc366 | bellard | #include <string.h> |
24 | fdabc366 | bellard | #include <inttypes.h> |
25 | fdabc366 | bellard | #include <signal.h> |
26 | fdabc366 | bellard | #include <assert.h> |
27 | fdabc366 | bellard | |
28 | fdabc366 | bellard | #include "cpu.h" |
29 | fdabc366 | bellard | #include "exec-all.h" |
30 | 0411a972 | j_mayer | #include "helper_regs.h" |
31 | ca10f867 | aurel32 | #include "qemu-common.h" |
32 | 9a64fbe4 | bellard | |
33 | 9a64fbe4 | bellard | //#define DEBUG_MMU
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34 | 9a64fbe4 | bellard | //#define DEBUG_BATS
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35 | 6b542af7 | j_mayer | //#define DEBUG_SLB
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36 | 76a66253 | j_mayer | //#define DEBUG_SOFTWARE_TLB
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37 | 0411a972 | j_mayer | //#define DUMP_PAGE_TABLES
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38 | 9a64fbe4 | bellard | //#define DEBUG_EXCEPTIONS
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39 | fdabc366 | bellard | //#define FLUSH_ALL_TLBS
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40 | 9a64fbe4 | bellard | |
41 | 9a64fbe4 | bellard | /*****************************************************************************/
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42 | 3fc6c082 | bellard | /* PowerPC MMU emulation */
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43 | a541f297 | bellard | |
44 | d9bce9d9 | j_mayer | #if defined(CONFIG_USER_ONLY)
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45 | e96efcfc | j_mayer | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
46 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
47 | 24741ef3 | bellard | { |
48 | 24741ef3 | bellard | int exception, error_code;
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49 | d9bce9d9 | j_mayer | |
50 | 24741ef3 | bellard | if (rw == 2) { |
51 | e1833e1f | j_mayer | exception = POWERPC_EXCP_ISI; |
52 | 8f793433 | j_mayer | error_code = 0x40000000;
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53 | 24741ef3 | bellard | } else {
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54 | e1833e1f | j_mayer | exception = POWERPC_EXCP_DSI; |
55 | 8f793433 | j_mayer | error_code = 0x40000000;
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56 | 24741ef3 | bellard | if (rw)
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57 | 24741ef3 | bellard | error_code |= 0x02000000;
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58 | 24741ef3 | bellard | env->spr[SPR_DAR] = address; |
59 | 24741ef3 | bellard | env->spr[SPR_DSISR] = error_code; |
60 | 24741ef3 | bellard | } |
61 | 24741ef3 | bellard | env->exception_index = exception; |
62 | 24741ef3 | bellard | env->error_code = error_code; |
63 | 76a66253 | j_mayer | |
64 | 24741ef3 | bellard | return 1; |
65 | 24741ef3 | bellard | } |
66 | 76a66253 | j_mayer | |
67 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
68 | 24741ef3 | bellard | { |
69 | 24741ef3 | bellard | return addr;
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70 | 24741ef3 | bellard | } |
71 | 36081602 | j_mayer | |
72 | 24741ef3 | bellard | #else
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73 | 76a66253 | j_mayer | /* Common routines used by software and hardware TLBs emulation */
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74 | b068d6a7 | j_mayer | static always_inline int pte_is_valid (target_ulong pte0) |
75 | 76a66253 | j_mayer | { |
76 | 76a66253 | j_mayer | return pte0 & 0x80000000 ? 1 : 0; |
77 | 76a66253 | j_mayer | } |
78 | 76a66253 | j_mayer | |
79 | b068d6a7 | j_mayer | static always_inline void pte_invalidate (target_ulong *pte0) |
80 | 76a66253 | j_mayer | { |
81 | 76a66253 | j_mayer | *pte0 &= ~0x80000000;
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82 | 76a66253 | j_mayer | } |
83 | 76a66253 | j_mayer | |
84 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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85 | b068d6a7 | j_mayer | static always_inline int pte64_is_valid (target_ulong pte0) |
86 | caa4039c | j_mayer | { |
87 | caa4039c | j_mayer | return pte0 & 0x0000000000000001ULL ? 1 : 0; |
88 | caa4039c | j_mayer | } |
89 | caa4039c | j_mayer | |
90 | b068d6a7 | j_mayer | static always_inline void pte64_invalidate (target_ulong *pte0) |
91 | caa4039c | j_mayer | { |
92 | caa4039c | j_mayer | *pte0 &= ~0x0000000000000001ULL;
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93 | caa4039c | j_mayer | } |
94 | caa4039c | j_mayer | #endif
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95 | caa4039c | j_mayer | |
96 | 76a66253 | j_mayer | #define PTE_PTEM_MASK 0x7FFFFFBF |
97 | 76a66253 | j_mayer | #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) |
98 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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99 | caa4039c | j_mayer | #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL |
100 | caa4039c | j_mayer | #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F) |
101 | caa4039c | j_mayer | #endif
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102 | 76a66253 | j_mayer | |
103 | b227a8e9 | j_mayer | static always_inline int pp_check (int key, int pp, int nx) |
104 | b227a8e9 | j_mayer | { |
105 | b227a8e9 | j_mayer | int access;
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106 | b227a8e9 | j_mayer | |
107 | b227a8e9 | j_mayer | /* Compute access rights */
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108 | b227a8e9 | j_mayer | /* When pp is 3/7, the result is undefined. Set it to noaccess */
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109 | b227a8e9 | j_mayer | access = 0;
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110 | b227a8e9 | j_mayer | if (key == 0) { |
111 | b227a8e9 | j_mayer | switch (pp) {
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112 | b227a8e9 | j_mayer | case 0x0: |
113 | b227a8e9 | j_mayer | case 0x1: |
114 | b227a8e9 | j_mayer | case 0x2: |
115 | b227a8e9 | j_mayer | access |= PAGE_WRITE; |
116 | b227a8e9 | j_mayer | /* No break here */
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117 | b227a8e9 | j_mayer | case 0x3: |
118 | b227a8e9 | j_mayer | case 0x6: |
119 | b227a8e9 | j_mayer | access |= PAGE_READ; |
120 | b227a8e9 | j_mayer | break;
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121 | b227a8e9 | j_mayer | } |
122 | b227a8e9 | j_mayer | } else {
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123 | b227a8e9 | j_mayer | switch (pp) {
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124 | b227a8e9 | j_mayer | case 0x0: |
125 | b227a8e9 | j_mayer | case 0x6: |
126 | b227a8e9 | j_mayer | access = 0;
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127 | b227a8e9 | j_mayer | break;
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128 | b227a8e9 | j_mayer | case 0x1: |
129 | b227a8e9 | j_mayer | case 0x3: |
130 | b227a8e9 | j_mayer | access = PAGE_READ; |
131 | b227a8e9 | j_mayer | break;
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132 | b227a8e9 | j_mayer | case 0x2: |
133 | b227a8e9 | j_mayer | access = PAGE_READ | PAGE_WRITE; |
134 | b227a8e9 | j_mayer | break;
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135 | b227a8e9 | j_mayer | } |
136 | b227a8e9 | j_mayer | } |
137 | b227a8e9 | j_mayer | if (nx == 0) |
138 | b227a8e9 | j_mayer | access |= PAGE_EXEC; |
139 | b227a8e9 | j_mayer | |
140 | b227a8e9 | j_mayer | return access;
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141 | b227a8e9 | j_mayer | } |
142 | b227a8e9 | j_mayer | |
143 | b227a8e9 | j_mayer | static always_inline int check_prot (int prot, int rw, int access_type) |
144 | b227a8e9 | j_mayer | { |
145 | b227a8e9 | j_mayer | int ret;
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146 | b227a8e9 | j_mayer | |
147 | b227a8e9 | j_mayer | if (access_type == ACCESS_CODE) {
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148 | b227a8e9 | j_mayer | if (prot & PAGE_EXEC)
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149 | b227a8e9 | j_mayer | ret = 0;
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150 | b227a8e9 | j_mayer | else
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151 | b227a8e9 | j_mayer | ret = -2;
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152 | b227a8e9 | j_mayer | } else if (rw) { |
153 | b227a8e9 | j_mayer | if (prot & PAGE_WRITE)
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154 | b227a8e9 | j_mayer | ret = 0;
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155 | b227a8e9 | j_mayer | else
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156 | b227a8e9 | j_mayer | ret = -2;
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157 | b227a8e9 | j_mayer | } else {
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158 | b227a8e9 | j_mayer | if (prot & PAGE_READ)
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159 | b227a8e9 | j_mayer | ret = 0;
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160 | b227a8e9 | j_mayer | else
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161 | b227a8e9 | j_mayer | ret = -2;
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162 | b227a8e9 | j_mayer | } |
163 | b227a8e9 | j_mayer | |
164 | b227a8e9 | j_mayer | return ret;
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165 | b227a8e9 | j_mayer | } |
166 | b227a8e9 | j_mayer | |
167 | b068d6a7 | j_mayer | static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b, |
168 | b068d6a7 | j_mayer | target_ulong pte0, target_ulong pte1, |
169 | b227a8e9 | j_mayer | int h, int rw, int type) |
170 | 76a66253 | j_mayer | { |
171 | caa4039c | j_mayer | target_ulong ptem, mmask; |
172 | b227a8e9 | j_mayer | int access, ret, pteh, ptev, pp;
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173 | 76a66253 | j_mayer | |
174 | 76a66253 | j_mayer | access = 0;
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175 | 76a66253 | j_mayer | ret = -1;
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176 | 76a66253 | j_mayer | /* Check validity and table match */
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177 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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178 | caa4039c | j_mayer | if (is_64b) {
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179 | caa4039c | j_mayer | ptev = pte64_is_valid(pte0); |
180 | caa4039c | j_mayer | pteh = (pte0 >> 1) & 1; |
181 | caa4039c | j_mayer | } else
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182 | caa4039c | j_mayer | #endif
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183 | caa4039c | j_mayer | { |
184 | caa4039c | j_mayer | ptev = pte_is_valid(pte0); |
185 | caa4039c | j_mayer | pteh = (pte0 >> 6) & 1; |
186 | caa4039c | j_mayer | } |
187 | caa4039c | j_mayer | if (ptev && h == pteh) {
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188 | 76a66253 | j_mayer | /* Check vsid & api */
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189 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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190 | caa4039c | j_mayer | if (is_64b) {
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191 | caa4039c | j_mayer | ptem = pte0 & PTE64_PTEM_MASK; |
192 | caa4039c | j_mayer | mmask = PTE64_CHECK_MASK; |
193 | b227a8e9 | j_mayer | pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004); |
194 | b227a8e9 | j_mayer | ctx->nx |= (pte1 >> 2) & 1; /* No execute bit */ |
195 | b227a8e9 | j_mayer | ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */ |
196 | caa4039c | j_mayer | } else
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197 | caa4039c | j_mayer | #endif
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198 | caa4039c | j_mayer | { |
199 | caa4039c | j_mayer | ptem = pte0 & PTE_PTEM_MASK; |
200 | caa4039c | j_mayer | mmask = PTE_CHECK_MASK; |
201 | b227a8e9 | j_mayer | pp = pte1 & 0x00000003;
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202 | caa4039c | j_mayer | } |
203 | caa4039c | j_mayer | if (ptem == ctx->ptem) {
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204 | 6f2d8978 | j_mayer | if (ctx->raddr != (target_phys_addr_t)-1ULL) { |
205 | 76a66253 | j_mayer | /* all matches should have equal RPN, WIMG & PP */
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206 | caa4039c | j_mayer | if ((ctx->raddr & mmask) != (pte1 & mmask)) {
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207 | caa4039c | j_mayer | if (loglevel != 0) |
208 | 76a66253 | j_mayer | fprintf(logfile, "Bad RPN/WIMG/PP\n");
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209 | 76a66253 | j_mayer | return -3; |
210 | 76a66253 | j_mayer | } |
211 | 76a66253 | j_mayer | } |
212 | 76a66253 | j_mayer | /* Compute access rights */
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213 | b227a8e9 | j_mayer | access = pp_check(ctx->key, pp, ctx->nx); |
214 | 76a66253 | j_mayer | /* Keep the matching PTE informations */
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215 | 76a66253 | j_mayer | ctx->raddr = pte1; |
216 | 76a66253 | j_mayer | ctx->prot = access; |
217 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, type); |
218 | b227a8e9 | j_mayer | if (ret == 0) { |
219 | 76a66253 | j_mayer | /* Access granted */
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220 | 76a66253 | j_mayer | #if defined (DEBUG_MMU)
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221 | 4a057712 | j_mayer | if (loglevel != 0) |
222 | 76a66253 | j_mayer | fprintf(logfile, "PTE access granted !\n");
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223 | 76a66253 | j_mayer | #endif
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224 | 76a66253 | j_mayer | } else {
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225 | 76a66253 | j_mayer | /* Access right violation */
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226 | 76a66253 | j_mayer | #if defined (DEBUG_MMU)
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227 | 4a057712 | j_mayer | if (loglevel != 0) |
228 | 76a66253 | j_mayer | fprintf(logfile, "PTE access rejected\n");
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229 | 76a66253 | j_mayer | #endif
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230 | 76a66253 | j_mayer | } |
231 | 76a66253 | j_mayer | } |
232 | 76a66253 | j_mayer | } |
233 | 76a66253 | j_mayer | |
234 | 76a66253 | j_mayer | return ret;
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235 | 76a66253 | j_mayer | } |
236 | 76a66253 | j_mayer | |
237 | a11b8151 | j_mayer | static always_inline int pte32_check (mmu_ctx_t *ctx, |
238 | a11b8151 | j_mayer | target_ulong pte0, target_ulong pte1, |
239 | a11b8151 | j_mayer | int h, int rw, int type) |
240 | caa4039c | j_mayer | { |
241 | b227a8e9 | j_mayer | return _pte_check(ctx, 0, pte0, pte1, h, rw, type); |
242 | caa4039c | j_mayer | } |
243 | caa4039c | j_mayer | |
244 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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245 | a11b8151 | j_mayer | static always_inline int pte64_check (mmu_ctx_t *ctx, |
246 | a11b8151 | j_mayer | target_ulong pte0, target_ulong pte1, |
247 | a11b8151 | j_mayer | int h, int rw, int type) |
248 | caa4039c | j_mayer | { |
249 | b227a8e9 | j_mayer | return _pte_check(ctx, 1, pte0, pte1, h, rw, type); |
250 | caa4039c | j_mayer | } |
251 | caa4039c | j_mayer | #endif
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252 | caa4039c | j_mayer | |
253 | a11b8151 | j_mayer | static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p, |
254 | a11b8151 | j_mayer | int ret, int rw) |
255 | 76a66253 | j_mayer | { |
256 | 76a66253 | j_mayer | int store = 0; |
257 | 76a66253 | j_mayer | |
258 | 76a66253 | j_mayer | /* Update page flags */
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259 | 76a66253 | j_mayer | if (!(*pte1p & 0x00000100)) { |
260 | 76a66253 | j_mayer | /* Update accessed flag */
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261 | 76a66253 | j_mayer | *pte1p |= 0x00000100;
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262 | 76a66253 | j_mayer | store = 1;
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263 | 76a66253 | j_mayer | } |
264 | 76a66253 | j_mayer | if (!(*pte1p & 0x00000080)) { |
265 | 76a66253 | j_mayer | if (rw == 1 && ret == 0) { |
266 | 76a66253 | j_mayer | /* Update changed flag */
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267 | 76a66253 | j_mayer | *pte1p |= 0x00000080;
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268 | 76a66253 | j_mayer | store = 1;
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269 | 76a66253 | j_mayer | } else {
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270 | 76a66253 | j_mayer | /* Force page fault for first write access */
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271 | 76a66253 | j_mayer | ctx->prot &= ~PAGE_WRITE; |
272 | 76a66253 | j_mayer | } |
273 | 76a66253 | j_mayer | } |
274 | 76a66253 | j_mayer | |
275 | 76a66253 | j_mayer | return store;
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276 | 76a66253 | j_mayer | } |
277 | 76a66253 | j_mayer | |
278 | 76a66253 | j_mayer | /* Software driven TLB helpers */
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279 | a11b8151 | j_mayer | static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr, |
280 | a11b8151 | j_mayer | int way, int is_code) |
281 | 76a66253 | j_mayer | { |
282 | 76a66253 | j_mayer | int nr;
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283 | 76a66253 | j_mayer | |
284 | 76a66253 | j_mayer | /* Select TLB num in a way from address */
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285 | 76a66253 | j_mayer | nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
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286 | 76a66253 | j_mayer | /* Select TLB way */
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287 | 76a66253 | j_mayer | nr += env->tlb_per_way * way; |
288 | 76a66253 | j_mayer | /* 6xx have separate TLBs for instructions and data */
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289 | 76a66253 | j_mayer | if (is_code && env->id_tlbs == 1) |
290 | 76a66253 | j_mayer | nr += env->nb_tlb; |
291 | 76a66253 | j_mayer | |
292 | 76a66253 | j_mayer | return nr;
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293 | 76a66253 | j_mayer | } |
294 | 76a66253 | j_mayer | |
295 | a11b8151 | j_mayer | static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env) |
296 | 76a66253 | j_mayer | { |
297 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
298 | 76a66253 | j_mayer | int nr, max;
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299 | 76a66253 | j_mayer | |
300 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB) && 0 |
301 | 76a66253 | j_mayer | if (loglevel != 0) { |
302 | 76a66253 | j_mayer | fprintf(logfile, "Invalidate all TLBs\n");
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303 | 76a66253 | j_mayer | } |
304 | 76a66253 | j_mayer | #endif
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305 | 76a66253 | j_mayer | /* Invalidate all defined software TLB */
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306 | 76a66253 | j_mayer | max = env->nb_tlb; |
307 | 76a66253 | j_mayer | if (env->id_tlbs == 1) |
308 | 76a66253 | j_mayer | max *= 2;
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309 | 76a66253 | j_mayer | for (nr = 0; nr < max; nr++) { |
310 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
311 | 76a66253 | j_mayer | pte_invalidate(&tlb->pte0); |
312 | 76a66253 | j_mayer | } |
313 | 76a66253 | j_mayer | tlb_flush(env, 1);
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314 | 76a66253 | j_mayer | } |
315 | 76a66253 | j_mayer | |
316 | b068d6a7 | j_mayer | static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env, |
317 | b068d6a7 | j_mayer | target_ulong eaddr, |
318 | b068d6a7 | j_mayer | int is_code,
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319 | b068d6a7 | j_mayer | int match_epn)
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320 | 76a66253 | j_mayer | { |
321 | 4a057712 | j_mayer | #if !defined(FLUSH_ALL_TLBS)
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322 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
323 | 76a66253 | j_mayer | int way, nr;
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324 | 76a66253 | j_mayer | |
325 | 76a66253 | j_mayer | /* Invalidate ITLB + DTLB, all ways */
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326 | 76a66253 | j_mayer | for (way = 0; way < env->nb_ways; way++) { |
327 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); |
328 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
329 | 76a66253 | j_mayer | if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { |
330 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
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331 | 76a66253 | j_mayer | if (loglevel != 0) { |
332 | 1b9eb036 | j_mayer | fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n", |
333 | 76a66253 | j_mayer | nr, env->nb_tlb, eaddr); |
334 | 76a66253 | j_mayer | } |
335 | 76a66253 | j_mayer | #endif
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336 | 76a66253 | j_mayer | pte_invalidate(&tlb->pte0); |
337 | 76a66253 | j_mayer | tlb_flush_page(env, tlb->EPN); |
338 | 76a66253 | j_mayer | } |
339 | 76a66253 | j_mayer | } |
340 | 76a66253 | j_mayer | #else
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341 | 76a66253 | j_mayer | /* XXX: PowerPC specification say this is valid as well */
|
342 | 76a66253 | j_mayer | ppc6xx_tlb_invalidate_all(env); |
343 | 76a66253 | j_mayer | #endif
|
344 | 76a66253 | j_mayer | } |
345 | 76a66253 | j_mayer | |
346 | a11b8151 | j_mayer | static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env, |
347 | a11b8151 | j_mayer | target_ulong eaddr, |
348 | a11b8151 | j_mayer | int is_code)
|
349 | 76a66253 | j_mayer | { |
350 | 76a66253 | j_mayer | __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
|
351 | 76a66253 | j_mayer | } |
352 | 76a66253 | j_mayer | |
353 | 76a66253 | j_mayer | void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, |
354 | 76a66253 | j_mayer | target_ulong pte0, target_ulong pte1) |
355 | 76a66253 | j_mayer | { |
356 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
357 | 76a66253 | j_mayer | int nr;
|
358 | 76a66253 | j_mayer | |
359 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); |
360 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
361 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
362 | 76a66253 | j_mayer | if (loglevel != 0) { |
363 | 5fafdf24 | ths | fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX |
364 | 1b9eb036 | j_mayer | " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1); |
365 | 76a66253 | j_mayer | } |
366 | 76a66253 | j_mayer | #endif
|
367 | 76a66253 | j_mayer | /* Invalidate any pending reference in Qemu for this virtual address */
|
368 | 76a66253 | j_mayer | __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
|
369 | 76a66253 | j_mayer | tlb->pte0 = pte0; |
370 | 76a66253 | j_mayer | tlb->pte1 = pte1; |
371 | 76a66253 | j_mayer | tlb->EPN = EPN; |
372 | 76a66253 | j_mayer | /* Store last way for LRU mechanism */
|
373 | 76a66253 | j_mayer | env->last_way = way; |
374 | 76a66253 | j_mayer | } |
375 | 76a66253 | j_mayer | |
376 | a11b8151 | j_mayer | static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx, |
377 | a11b8151 | j_mayer | target_ulong eaddr, int rw,
|
378 | a11b8151 | j_mayer | int access_type)
|
379 | 76a66253 | j_mayer | { |
380 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
381 | 76a66253 | j_mayer | int nr, best, way;
|
382 | 76a66253 | j_mayer | int ret;
|
383 | d9bce9d9 | j_mayer | |
384 | 76a66253 | j_mayer | best = -1;
|
385 | 76a66253 | j_mayer | ret = -1; /* No TLB found */ |
386 | 76a66253 | j_mayer | for (way = 0; way < env->nb_ways; way++) { |
387 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, eaddr, way, |
388 | 76a66253 | j_mayer | access_type == ACCESS_CODE ? 1 : 0); |
389 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
390 | 76a66253 | j_mayer | /* This test "emulates" the PTE index match for hardware TLBs */
|
391 | 76a66253 | j_mayer | if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
|
392 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
393 | 76a66253 | j_mayer | if (loglevel != 0) { |
394 | 1b9eb036 | j_mayer | fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX |
395 | 1b9eb036 | j_mayer | "] <> " ADDRX "\n", |
396 | 76a66253 | j_mayer | nr, env->nb_tlb, |
397 | 76a66253 | j_mayer | pte_is_valid(tlb->pte0) ? "valid" : "inval", |
398 | 76a66253 | j_mayer | tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); |
399 | 76a66253 | j_mayer | } |
400 | 76a66253 | j_mayer | #endif
|
401 | 76a66253 | j_mayer | continue;
|
402 | 76a66253 | j_mayer | } |
403 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
404 | 76a66253 | j_mayer | if (loglevel != 0) { |
405 | 1b9eb036 | j_mayer | fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX |
406 | 1b9eb036 | j_mayer | " %c %c\n",
|
407 | 76a66253 | j_mayer | nr, env->nb_tlb, |
408 | 76a66253 | j_mayer | pte_is_valid(tlb->pte0) ? "valid" : "inval", |
409 | 76a66253 | j_mayer | tlb->EPN, eaddr, tlb->pte1, |
410 | 76a66253 | j_mayer | rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); |
411 | 76a66253 | j_mayer | } |
412 | 76a66253 | j_mayer | #endif
|
413 | b227a8e9 | j_mayer | switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) { |
414 | 76a66253 | j_mayer | case -3: |
415 | 76a66253 | j_mayer | /* TLB inconsistency */
|
416 | 76a66253 | j_mayer | return -1; |
417 | 76a66253 | j_mayer | case -2: |
418 | 76a66253 | j_mayer | /* Access violation */
|
419 | 76a66253 | j_mayer | ret = -2;
|
420 | 76a66253 | j_mayer | best = nr; |
421 | 76a66253 | j_mayer | break;
|
422 | 76a66253 | j_mayer | case -1: |
423 | 76a66253 | j_mayer | default:
|
424 | 76a66253 | j_mayer | /* No match */
|
425 | 76a66253 | j_mayer | break;
|
426 | 76a66253 | j_mayer | case 0: |
427 | 76a66253 | j_mayer | /* access granted */
|
428 | 76a66253 | j_mayer | /* XXX: we should go on looping to check all TLBs consistency
|
429 | 76a66253 | j_mayer | * but we can speed-up the whole thing as the
|
430 | 76a66253 | j_mayer | * result would be undefined if TLBs are not consistent.
|
431 | 76a66253 | j_mayer | */
|
432 | 76a66253 | j_mayer | ret = 0;
|
433 | 76a66253 | j_mayer | best = nr; |
434 | 76a66253 | j_mayer | goto done;
|
435 | 76a66253 | j_mayer | } |
436 | 76a66253 | j_mayer | } |
437 | 76a66253 | j_mayer | if (best != -1) { |
438 | 76a66253 | j_mayer | done:
|
439 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
440 | 4a057712 | j_mayer | if (loglevel != 0) { |
441 | 6b542af7 | j_mayer | fprintf(logfile, "found TLB at addr " PADDRX " prot=%01x ret=%d\n", |
442 | 76a66253 | j_mayer | ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); |
443 | 76a66253 | j_mayer | } |
444 | 76a66253 | j_mayer | #endif
|
445 | 76a66253 | j_mayer | /* Update page flags */
|
446 | 1d0a48fb | j_mayer | pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw); |
447 | 76a66253 | j_mayer | } |
448 | 76a66253 | j_mayer | |
449 | 76a66253 | j_mayer | return ret;
|
450 | 76a66253 | j_mayer | } |
451 | 76a66253 | j_mayer | |
452 | 9a64fbe4 | bellard | /* Perform BAT hit & translation */
|
453 | faadf50e | j_mayer | static always_inline void bat_size_prot (CPUState *env, target_ulong *blp, |
454 | faadf50e | j_mayer | int *validp, int *protp, |
455 | faadf50e | j_mayer | target_ulong *BATu, target_ulong *BATl) |
456 | faadf50e | j_mayer | { |
457 | faadf50e | j_mayer | target_ulong bl; |
458 | faadf50e | j_mayer | int pp, valid, prot;
|
459 | faadf50e | j_mayer | |
460 | faadf50e | j_mayer | bl = (*BATu & 0x00001FFC) << 15; |
461 | faadf50e | j_mayer | valid = 0;
|
462 | faadf50e | j_mayer | prot = 0;
|
463 | faadf50e | j_mayer | if (((msr_pr == 0) && (*BATu & 0x00000002)) || |
464 | faadf50e | j_mayer | ((msr_pr != 0) && (*BATu & 0x00000001))) { |
465 | faadf50e | j_mayer | valid = 1;
|
466 | faadf50e | j_mayer | pp = *BATl & 0x00000003;
|
467 | faadf50e | j_mayer | if (pp != 0) { |
468 | faadf50e | j_mayer | prot = PAGE_READ | PAGE_EXEC; |
469 | faadf50e | j_mayer | if (pp == 0x2) |
470 | faadf50e | j_mayer | prot |= PAGE_WRITE; |
471 | faadf50e | j_mayer | } |
472 | faadf50e | j_mayer | } |
473 | faadf50e | j_mayer | *blp = bl; |
474 | faadf50e | j_mayer | *validp = valid; |
475 | faadf50e | j_mayer | *protp = prot; |
476 | faadf50e | j_mayer | } |
477 | faadf50e | j_mayer | |
478 | faadf50e | j_mayer | static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp, |
479 | faadf50e | j_mayer | int *validp, int *protp, |
480 | faadf50e | j_mayer | target_ulong *BATu, |
481 | faadf50e | j_mayer | target_ulong *BATl) |
482 | faadf50e | j_mayer | { |
483 | faadf50e | j_mayer | target_ulong bl; |
484 | faadf50e | j_mayer | int key, pp, valid, prot;
|
485 | faadf50e | j_mayer | |
486 | faadf50e | j_mayer | bl = (*BATl & 0x0000003F) << 17; |
487 | 056401ea | j_mayer | #if defined (DEBUG_BATS)
|
488 | faadf50e | j_mayer | if (loglevel != 0) { |
489 | 6b542af7 | j_mayer | fprintf(logfile, "b %02x ==> bl " ADDRX " msk " ADDRX "\n", |
490 | 6b542af7 | j_mayer | (uint8_t)(*BATl & 0x0000003F), bl, ~bl);
|
491 | faadf50e | j_mayer | } |
492 | 056401ea | j_mayer | #endif
|
493 | faadf50e | j_mayer | prot = 0;
|
494 | faadf50e | j_mayer | valid = (*BATl >> 6) & 1; |
495 | faadf50e | j_mayer | if (valid) {
|
496 | faadf50e | j_mayer | pp = *BATu & 0x00000003;
|
497 | faadf50e | j_mayer | if (msr_pr == 0) |
498 | faadf50e | j_mayer | key = (*BATu >> 3) & 1; |
499 | faadf50e | j_mayer | else
|
500 | faadf50e | j_mayer | key = (*BATu >> 2) & 1; |
501 | faadf50e | j_mayer | prot = pp_check(key, pp, 0);
|
502 | faadf50e | j_mayer | } |
503 | faadf50e | j_mayer | *blp = bl; |
504 | faadf50e | j_mayer | *validp = valid; |
505 | faadf50e | j_mayer | *protp = prot; |
506 | faadf50e | j_mayer | } |
507 | faadf50e | j_mayer | |
508 | a11b8151 | j_mayer | static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx, |
509 | a11b8151 | j_mayer | target_ulong virtual, int rw, int type) |
510 | 9a64fbe4 | bellard | { |
511 | 76a66253 | j_mayer | target_ulong *BATlt, *BATut, *BATu, *BATl; |
512 | 76a66253 | j_mayer | target_ulong base, BEPIl, BEPIu, bl; |
513 | faadf50e | j_mayer | int i, valid, prot;
|
514 | 9a64fbe4 | bellard | int ret = -1; |
515 | 9a64fbe4 | bellard | |
516 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
517 | 4a057712 | j_mayer | if (loglevel != 0) { |
518 | 6b542af7 | j_mayer | fprintf(logfile, "%s: %cBAT v " ADDRX "\n", __func__, |
519 | 76a66253 | j_mayer | type == ACCESS_CODE ? 'I' : 'D', virtual); |
520 | 9a64fbe4 | bellard | } |
521 | 9a64fbe4 | bellard | #endif
|
522 | 9a64fbe4 | bellard | switch (type) {
|
523 | 9a64fbe4 | bellard | case ACCESS_CODE:
|
524 | 9a64fbe4 | bellard | BATlt = env->IBAT[1];
|
525 | 9a64fbe4 | bellard | BATut = env->IBAT[0];
|
526 | 9a64fbe4 | bellard | break;
|
527 | 9a64fbe4 | bellard | default:
|
528 | 9a64fbe4 | bellard | BATlt = env->DBAT[1];
|
529 | 9a64fbe4 | bellard | BATut = env->DBAT[0];
|
530 | 9a64fbe4 | bellard | break;
|
531 | 9a64fbe4 | bellard | } |
532 | 9a64fbe4 | bellard | base = virtual & 0xFFFC0000;
|
533 | faadf50e | j_mayer | for (i = 0; i < env->nb_BATs; i++) { |
534 | 9a64fbe4 | bellard | BATu = &BATut[i]; |
535 | 9a64fbe4 | bellard | BATl = &BATlt[i]; |
536 | 9a64fbe4 | bellard | BEPIu = *BATu & 0xF0000000;
|
537 | 9a64fbe4 | bellard | BEPIl = *BATu & 0x0FFE0000;
|
538 | faadf50e | j_mayer | if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
|
539 | faadf50e | j_mayer | bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl); |
540 | faadf50e | j_mayer | } else {
|
541 | faadf50e | j_mayer | bat_size_prot(env, &bl, &valid, &prot, BATu, BATl); |
542 | faadf50e | j_mayer | } |
543 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
544 | 4a057712 | j_mayer | if (loglevel != 0) { |
545 | 6b542af7 | j_mayer | fprintf(logfile, "%s: %cBAT%d v " ADDRX " BATu " ADDRX |
546 | 6b542af7 | j_mayer | " BATl " ADDRX "\n", __func__, |
547 | 6b542af7 | j_mayer | type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl); |
548 | 9a64fbe4 | bellard | } |
549 | 9a64fbe4 | bellard | #endif
|
550 | 9a64fbe4 | bellard | if ((virtual & 0xF0000000) == BEPIu && |
551 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
|
552 | 9a64fbe4 | bellard | /* BAT matches */
|
553 | faadf50e | j_mayer | if (valid != 0) { |
554 | 9a64fbe4 | bellard | /* Get physical address */
|
555 | 76a66253 | j_mayer | ctx->raddr = (*BATl & 0xF0000000) |
|
556 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
557 | a541f297 | bellard | (virtual & 0x0001F000);
|
558 | b227a8e9 | j_mayer | /* Compute access rights */
|
559 | faadf50e | j_mayer | ctx->prot = prot; |
560 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, type); |
561 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
562 | b227a8e9 | j_mayer | if (ret == 0 && loglevel != 0) { |
563 | 6b542af7 | j_mayer | fprintf(logfile, "BAT %d match: r " PADDRX " prot=%c%c\n", |
564 | 76a66253 | j_mayer | i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', |
565 | 76a66253 | j_mayer | ctx->prot & PAGE_WRITE ? 'W' : '-'); |
566 | 9a64fbe4 | bellard | } |
567 | 9a64fbe4 | bellard | #endif
|
568 | 9a64fbe4 | bellard | break;
|
569 | 9a64fbe4 | bellard | } |
570 | 9a64fbe4 | bellard | } |
571 | 9a64fbe4 | bellard | } |
572 | 9a64fbe4 | bellard | if (ret < 0) { |
573 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
574 | 4a057712 | j_mayer | if (loglevel != 0) { |
575 | 6b542af7 | j_mayer | fprintf(logfile, "no BAT match for " ADDRX ":\n", virtual); |
576 | 4a057712 | j_mayer | for (i = 0; i < 4; i++) { |
577 | 4a057712 | j_mayer | BATu = &BATut[i]; |
578 | 4a057712 | j_mayer | BATl = &BATlt[i]; |
579 | 4a057712 | j_mayer | BEPIu = *BATu & 0xF0000000;
|
580 | 4a057712 | j_mayer | BEPIl = *BATu & 0x0FFE0000;
|
581 | 4a057712 | j_mayer | bl = (*BATu & 0x00001FFC) << 15; |
582 | 6b542af7 | j_mayer | fprintf(logfile, "%s: %cBAT%d v " ADDRX " BATu " ADDRX |
583 | 6b542af7 | j_mayer | " BATl " ADDRX " \n\t" ADDRX " " ADDRX " " ADDRX "\n", |
584 | 4a057712 | j_mayer | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
585 | 4a057712 | j_mayer | *BATu, *BATl, BEPIu, BEPIl, bl); |
586 | 4a057712 | j_mayer | } |
587 | 9a64fbe4 | bellard | } |
588 | 9a64fbe4 | bellard | #endif
|
589 | 9a64fbe4 | bellard | } |
590 | b227a8e9 | j_mayer | |
591 | 9a64fbe4 | bellard | /* No hit */
|
592 | 9a64fbe4 | bellard | return ret;
|
593 | 9a64fbe4 | bellard | } |
594 | 9a64fbe4 | bellard | |
595 | 9a64fbe4 | bellard | /* PTE table lookup */
|
596 | b227a8e9 | j_mayer | static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, |
597 | b227a8e9 | j_mayer | int rw, int type) |
598 | 9a64fbe4 | bellard | { |
599 | 76a66253 | j_mayer | target_ulong base, pte0, pte1; |
600 | 76a66253 | j_mayer | int i, good = -1; |
601 | caa4039c | j_mayer | int ret, r;
|
602 | 9a64fbe4 | bellard | |
603 | 76a66253 | j_mayer | ret = -1; /* No entry found */ |
604 | 76a66253 | j_mayer | base = ctx->pg_addr[h]; |
605 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) { |
606 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
607 | caa4039c | j_mayer | if (is_64b) {
|
608 | caa4039c | j_mayer | pte0 = ldq_phys(base + (i * 16));
|
609 | caa4039c | j_mayer | pte1 = ldq_phys(base + (i * 16) + 8); |
610 | b227a8e9 | j_mayer | r = pte64_check(ctx, pte0, pte1, h, rw, type); |
611 | 12de9a39 | j_mayer | #if defined (DEBUG_MMU)
|
612 | 12de9a39 | j_mayer | if (loglevel != 0) { |
613 | 6b542af7 | j_mayer | fprintf(logfile, "Load pte from " ADDRX " => " ADDRX " " ADDRX |
614 | 6b542af7 | j_mayer | " %d %d %d " ADDRX "\n", |
615 | 12de9a39 | j_mayer | base + (i * 16), pte0, pte1,
|
616 | 12de9a39 | j_mayer | (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1), |
617 | 12de9a39 | j_mayer | ctx->ptem); |
618 | 12de9a39 | j_mayer | } |
619 | 12de9a39 | j_mayer | #endif
|
620 | caa4039c | j_mayer | } else
|
621 | caa4039c | j_mayer | #endif
|
622 | caa4039c | j_mayer | { |
623 | caa4039c | j_mayer | pte0 = ldl_phys(base + (i * 8));
|
624 | caa4039c | j_mayer | pte1 = ldl_phys(base + (i * 8) + 4); |
625 | b227a8e9 | j_mayer | r = pte32_check(ctx, pte0, pte1, h, rw, type); |
626 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
627 | 12de9a39 | j_mayer | if (loglevel != 0) { |
628 | 6b542af7 | j_mayer | fprintf(logfile, "Load pte from " ADDRX " => " ADDRX " " ADDRX |
629 | 6b542af7 | j_mayer | " %d %d %d " ADDRX "\n", |
630 | 12de9a39 | j_mayer | base + (i * 8), pte0, pte1,
|
631 | 12de9a39 | j_mayer | (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), |
632 | 12de9a39 | j_mayer | ctx->ptem); |
633 | 12de9a39 | j_mayer | } |
634 | 9a64fbe4 | bellard | #endif
|
635 | 12de9a39 | j_mayer | } |
636 | caa4039c | j_mayer | switch (r) {
|
637 | 76a66253 | j_mayer | case -3: |
638 | 76a66253 | j_mayer | /* PTE inconsistency */
|
639 | 76a66253 | j_mayer | return -1; |
640 | 76a66253 | j_mayer | case -2: |
641 | 76a66253 | j_mayer | /* Access violation */
|
642 | 76a66253 | j_mayer | ret = -2;
|
643 | 76a66253 | j_mayer | good = i; |
644 | 76a66253 | j_mayer | break;
|
645 | 76a66253 | j_mayer | case -1: |
646 | 76a66253 | j_mayer | default:
|
647 | 76a66253 | j_mayer | /* No PTE match */
|
648 | 76a66253 | j_mayer | break;
|
649 | 76a66253 | j_mayer | case 0: |
650 | 76a66253 | j_mayer | /* access granted */
|
651 | 76a66253 | j_mayer | /* XXX: we should go on looping to check all PTEs consistency
|
652 | 76a66253 | j_mayer | * but if we can speed-up the whole thing as the
|
653 | 76a66253 | j_mayer | * result would be undefined if PTEs are not consistent.
|
654 | 76a66253 | j_mayer | */
|
655 | 76a66253 | j_mayer | ret = 0;
|
656 | 76a66253 | j_mayer | good = i; |
657 | 76a66253 | j_mayer | goto done;
|
658 | 9a64fbe4 | bellard | } |
659 | 9a64fbe4 | bellard | } |
660 | 9a64fbe4 | bellard | if (good != -1) { |
661 | 76a66253 | j_mayer | done:
|
662 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
663 | 4a057712 | j_mayer | if (loglevel != 0) { |
664 | 6b542af7 | j_mayer | fprintf(logfile, "found PTE at addr " PADDRX " prot=%01x ret=%d\n", |
665 | 76a66253 | j_mayer | ctx->raddr, ctx->prot, ret); |
666 | 76a66253 | j_mayer | } |
667 | 9a64fbe4 | bellard | #endif
|
668 | 9a64fbe4 | bellard | /* Update page flags */
|
669 | 76a66253 | j_mayer | pte1 = ctx->raddr; |
670 | caa4039c | j_mayer | if (pte_update_flags(ctx, &pte1, ret, rw) == 1) { |
671 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
672 | caa4039c | j_mayer | if (is_64b) {
|
673 | caa4039c | j_mayer | stq_phys_notdirty(base + (good * 16) + 8, pte1); |
674 | caa4039c | j_mayer | } else
|
675 | caa4039c | j_mayer | #endif
|
676 | caa4039c | j_mayer | { |
677 | caa4039c | j_mayer | stl_phys_notdirty(base + (good * 8) + 4, pte1); |
678 | caa4039c | j_mayer | } |
679 | caa4039c | j_mayer | } |
680 | 9a64fbe4 | bellard | } |
681 | 9a64fbe4 | bellard | |
682 | 9a64fbe4 | bellard | return ret;
|
683 | 79aceca5 | bellard | } |
684 | 79aceca5 | bellard | |
685 | a11b8151 | j_mayer | static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw, int type) |
686 | caa4039c | j_mayer | { |
687 | b227a8e9 | j_mayer | return _find_pte(ctx, 0, h, rw, type); |
688 | caa4039c | j_mayer | } |
689 | caa4039c | j_mayer | |
690 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
691 | a11b8151 | j_mayer | static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw, int type) |
692 | caa4039c | j_mayer | { |
693 | b227a8e9 | j_mayer | return _find_pte(ctx, 1, h, rw, type); |
694 | caa4039c | j_mayer | } |
695 | caa4039c | j_mayer | #endif
|
696 | caa4039c | j_mayer | |
697 | b068d6a7 | j_mayer | static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx, |
698 | b227a8e9 | j_mayer | int h, int rw, int type) |
699 | caa4039c | j_mayer | { |
700 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
701 | add78955 | j_mayer | if (env->mmu_model & POWERPC_MMU_64)
|
702 | b227a8e9 | j_mayer | return find_pte64(ctx, h, rw, type);
|
703 | caa4039c | j_mayer | #endif
|
704 | caa4039c | j_mayer | |
705 | b227a8e9 | j_mayer | return find_pte32(ctx, h, rw, type);
|
706 | caa4039c | j_mayer | } |
707 | caa4039c | j_mayer | |
708 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
709 | a11b8151 | j_mayer | static always_inline int slb_is_valid (uint64_t slb64) |
710 | eacc3249 | j_mayer | { |
711 | eacc3249 | j_mayer | return slb64 & 0x0000000008000000ULL ? 1 : 0; |
712 | eacc3249 | j_mayer | } |
713 | eacc3249 | j_mayer | |
714 | a11b8151 | j_mayer | static always_inline void slb_invalidate (uint64_t *slb64) |
715 | eacc3249 | j_mayer | { |
716 | eacc3249 | j_mayer | *slb64 &= ~0x0000000008000000ULL;
|
717 | eacc3249 | j_mayer | } |
718 | eacc3249 | j_mayer | |
719 | a11b8151 | j_mayer | static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr, |
720 | a11b8151 | j_mayer | target_ulong *vsid, |
721 | a11b8151 | j_mayer | target_ulong *page_mask, int *attr)
|
722 | caa4039c | j_mayer | { |
723 | caa4039c | j_mayer | target_phys_addr_t sr_base; |
724 | caa4039c | j_mayer | target_ulong mask; |
725 | caa4039c | j_mayer | uint64_t tmp64; |
726 | caa4039c | j_mayer | uint32_t tmp; |
727 | caa4039c | j_mayer | int n, ret;
|
728 | caa4039c | j_mayer | |
729 | caa4039c | j_mayer | ret = -5;
|
730 | caa4039c | j_mayer | sr_base = env->spr[SPR_ASR]; |
731 | 12de9a39 | j_mayer | #if defined(DEBUG_SLB)
|
732 | 12de9a39 | j_mayer | if (loglevel != 0) { |
733 | 12de9a39 | j_mayer | fprintf(logfile, "%s: eaddr " ADDRX " base " PADDRX "\n", |
734 | 12de9a39 | j_mayer | __func__, eaddr, sr_base); |
735 | 12de9a39 | j_mayer | } |
736 | 12de9a39 | j_mayer | #endif
|
737 | caa4039c | j_mayer | mask = 0x0000000000000000ULL; /* Avoid gcc warning */ |
738 | eacc3249 | j_mayer | for (n = 0; n < env->slb_nr; n++) { |
739 | caa4039c | j_mayer | tmp64 = ldq_phys(sr_base); |
740 | 12de9a39 | j_mayer | tmp = ldl_phys(sr_base + 8);
|
741 | 12de9a39 | j_mayer | #if defined(DEBUG_SLB)
|
742 | 12de9a39 | j_mayer | if (loglevel != 0) { |
743 | b33c17e1 | j_mayer | fprintf(logfile, "%s: seg %d " PADDRX " %016" PRIx64 " %08" |
744 | b33c17e1 | j_mayer | PRIx32 "\n", __func__, n, sr_base, tmp64, tmp);
|
745 | 12de9a39 | j_mayer | } |
746 | 12de9a39 | j_mayer | #endif
|
747 | eacc3249 | j_mayer | if (slb_is_valid(tmp64)) {
|
748 | caa4039c | j_mayer | /* SLB entry is valid */
|
749 | caa4039c | j_mayer | switch (tmp64 & 0x0000000006000000ULL) { |
750 | caa4039c | j_mayer | case 0x0000000000000000ULL: |
751 | caa4039c | j_mayer | /* 256 MB segment */
|
752 | caa4039c | j_mayer | mask = 0xFFFFFFFFF0000000ULL;
|
753 | caa4039c | j_mayer | break;
|
754 | caa4039c | j_mayer | case 0x0000000002000000ULL: |
755 | caa4039c | j_mayer | /* 1 TB segment */
|
756 | caa4039c | j_mayer | mask = 0xFFFF000000000000ULL;
|
757 | caa4039c | j_mayer | break;
|
758 | caa4039c | j_mayer | case 0x0000000004000000ULL: |
759 | caa4039c | j_mayer | case 0x0000000006000000ULL: |
760 | caa4039c | j_mayer | /* Reserved => segment is invalid */
|
761 | caa4039c | j_mayer | continue;
|
762 | caa4039c | j_mayer | } |
763 | caa4039c | j_mayer | if ((eaddr & mask) == (tmp64 & mask)) {
|
764 | caa4039c | j_mayer | /* SLB match */
|
765 | caa4039c | j_mayer | *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL; |
766 | caa4039c | j_mayer | *page_mask = ~mask; |
767 | caa4039c | j_mayer | *attr = tmp & 0xFF;
|
768 | eacc3249 | j_mayer | ret = n; |
769 | caa4039c | j_mayer | break;
|
770 | caa4039c | j_mayer | } |
771 | caa4039c | j_mayer | } |
772 | caa4039c | j_mayer | sr_base += 12;
|
773 | caa4039c | j_mayer | } |
774 | caa4039c | j_mayer | |
775 | caa4039c | j_mayer | return ret;
|
776 | 79aceca5 | bellard | } |
777 | 12de9a39 | j_mayer | |
778 | eacc3249 | j_mayer | void ppc_slb_invalidate_all (CPUPPCState *env)
|
779 | eacc3249 | j_mayer | { |
780 | eacc3249 | j_mayer | target_phys_addr_t sr_base; |
781 | eacc3249 | j_mayer | uint64_t tmp64; |
782 | eacc3249 | j_mayer | int n, do_invalidate;
|
783 | eacc3249 | j_mayer | |
784 | eacc3249 | j_mayer | do_invalidate = 0;
|
785 | eacc3249 | j_mayer | sr_base = env->spr[SPR_ASR]; |
786 | 2c1ee068 | j_mayer | /* XXX: Warning: slbia never invalidates the first segment */
|
787 | 2c1ee068 | j_mayer | for (n = 1; n < env->slb_nr; n++) { |
788 | eacc3249 | j_mayer | tmp64 = ldq_phys(sr_base); |
789 | eacc3249 | j_mayer | if (slb_is_valid(tmp64)) {
|
790 | eacc3249 | j_mayer | slb_invalidate(&tmp64); |
791 | eacc3249 | j_mayer | stq_phys(sr_base, tmp64); |
792 | eacc3249 | j_mayer | /* XXX: given the fact that segment size is 256 MB or 1TB,
|
793 | eacc3249 | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask)
|
794 | eacc3249 | j_mayer | * in Qemu, we just invalidate all TLBs
|
795 | eacc3249 | j_mayer | */
|
796 | eacc3249 | j_mayer | do_invalidate = 1;
|
797 | eacc3249 | j_mayer | } |
798 | eacc3249 | j_mayer | sr_base += 12;
|
799 | eacc3249 | j_mayer | } |
800 | eacc3249 | j_mayer | if (do_invalidate)
|
801 | eacc3249 | j_mayer | tlb_flush(env, 1);
|
802 | eacc3249 | j_mayer | } |
803 | eacc3249 | j_mayer | |
804 | eacc3249 | j_mayer | void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
|
805 | eacc3249 | j_mayer | { |
806 | eacc3249 | j_mayer | target_phys_addr_t sr_base; |
807 | eacc3249 | j_mayer | target_ulong vsid, page_mask; |
808 | eacc3249 | j_mayer | uint64_t tmp64; |
809 | eacc3249 | j_mayer | int attr;
|
810 | eacc3249 | j_mayer | int n;
|
811 | eacc3249 | j_mayer | |
812 | eacc3249 | j_mayer | n = slb_lookup(env, T0, &vsid, &page_mask, &attr); |
813 | eacc3249 | j_mayer | if (n >= 0) { |
814 | eacc3249 | j_mayer | sr_base = env->spr[SPR_ASR]; |
815 | eacc3249 | j_mayer | sr_base += 12 * n;
|
816 | eacc3249 | j_mayer | tmp64 = ldq_phys(sr_base); |
817 | eacc3249 | j_mayer | if (slb_is_valid(tmp64)) {
|
818 | eacc3249 | j_mayer | slb_invalidate(&tmp64); |
819 | eacc3249 | j_mayer | stq_phys(sr_base, tmp64); |
820 | eacc3249 | j_mayer | /* XXX: given the fact that segment size is 256 MB or 1TB,
|
821 | eacc3249 | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask)
|
822 | eacc3249 | j_mayer | * in Qemu, we just invalidate all TLBs
|
823 | eacc3249 | j_mayer | */
|
824 | eacc3249 | j_mayer | tlb_flush(env, 1);
|
825 | eacc3249 | j_mayer | } |
826 | eacc3249 | j_mayer | } |
827 | eacc3249 | j_mayer | } |
828 | eacc3249 | j_mayer | |
829 | 12de9a39 | j_mayer | target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
|
830 | 12de9a39 | j_mayer | { |
831 | 12de9a39 | j_mayer | target_phys_addr_t sr_base; |
832 | 12de9a39 | j_mayer | target_ulong rt; |
833 | 12de9a39 | j_mayer | uint64_t tmp64; |
834 | 12de9a39 | j_mayer | uint32_t tmp; |
835 | 12de9a39 | j_mayer | |
836 | 12de9a39 | j_mayer | sr_base = env->spr[SPR_ASR]; |
837 | 12de9a39 | j_mayer | sr_base += 12 * slb_nr;
|
838 | 12de9a39 | j_mayer | tmp64 = ldq_phys(sr_base); |
839 | 12de9a39 | j_mayer | tmp = ldl_phys(sr_base + 8);
|
840 | 12de9a39 | j_mayer | if (tmp64 & 0x0000000008000000ULL) { |
841 | 12de9a39 | j_mayer | /* SLB entry is valid */
|
842 | 12de9a39 | j_mayer | /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
|
843 | 12de9a39 | j_mayer | rt = tmp >> 8; /* 65:88 => 40:63 */ |
844 | 12de9a39 | j_mayer | rt |= (tmp64 & 0x7) << 24; /* 62:64 => 37:39 */ |
845 | 12de9a39 | j_mayer | /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
|
846 | 12de9a39 | j_mayer | rt |= ((tmp >> 4) & 0xF) << 27; |
847 | 12de9a39 | j_mayer | } else {
|
848 | 12de9a39 | j_mayer | rt = 0;
|
849 | 12de9a39 | j_mayer | } |
850 | 12de9a39 | j_mayer | #if defined(DEBUG_SLB)
|
851 | 12de9a39 | j_mayer | if (loglevel != 0) { |
852 | 12de9a39 | j_mayer | fprintf(logfile, "%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d " |
853 | 12de9a39 | j_mayer | ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt);
|
854 | 12de9a39 | j_mayer | } |
855 | 12de9a39 | j_mayer | #endif
|
856 | 12de9a39 | j_mayer | |
857 | 12de9a39 | j_mayer | return rt;
|
858 | 12de9a39 | j_mayer | } |
859 | 12de9a39 | j_mayer | |
860 | 12de9a39 | j_mayer | void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs) |
861 | 12de9a39 | j_mayer | { |
862 | 12de9a39 | j_mayer | target_phys_addr_t sr_base; |
863 | 12de9a39 | j_mayer | uint64_t tmp64; |
864 | 12de9a39 | j_mayer | uint32_t tmp; |
865 | 12de9a39 | j_mayer | |
866 | 12de9a39 | j_mayer | sr_base = env->spr[SPR_ASR]; |
867 | 12de9a39 | j_mayer | sr_base += 12 * slb_nr;
|
868 | 12de9a39 | j_mayer | /* Copy Rs bits 37:63 to SLB 62:88 */
|
869 | 12de9a39 | j_mayer | tmp = rs << 8;
|
870 | 12de9a39 | j_mayer | tmp64 = (rs >> 24) & 0x7; |
871 | 12de9a39 | j_mayer | /* Copy Rs bits 33:36 to SLB 89:92 */
|
872 | 12de9a39 | j_mayer | tmp |= ((rs >> 27) & 0xF) << 4; |
873 | 12de9a39 | j_mayer | /* Set the valid bit */
|
874 | 12de9a39 | j_mayer | tmp64 |= 1 << 27; |
875 | 12de9a39 | j_mayer | /* Set ESID */
|
876 | 12de9a39 | j_mayer | tmp64 |= (uint32_t)slb_nr << 28;
|
877 | 12de9a39 | j_mayer | #if defined(DEBUG_SLB)
|
878 | 12de9a39 | j_mayer | if (loglevel != 0) { |
879 | 6b542af7 | j_mayer | fprintf(logfile, "%s: %d " ADDRX " => " PADDRX " %016" PRIx64 |
880 | 6b542af7 | j_mayer | " %08" PRIx32 "\n", __func__, |
881 | 6b542af7 | j_mayer | slb_nr, rs, sr_base, tmp64, tmp); |
882 | 12de9a39 | j_mayer | } |
883 | 12de9a39 | j_mayer | #endif
|
884 | 12de9a39 | j_mayer | /* Write SLB entry to memory */
|
885 | 12de9a39 | j_mayer | stq_phys(sr_base, tmp64); |
886 | 12de9a39 | j_mayer | stl_phys(sr_base + 8, tmp);
|
887 | 12de9a39 | j_mayer | } |
888 | caa4039c | j_mayer | #endif /* defined(TARGET_PPC64) */ |
889 | 79aceca5 | bellard | |
890 | 9a64fbe4 | bellard | /* Perform segment based translation */
|
891 | b068d6a7 | j_mayer | static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
|
892 | b068d6a7 | j_mayer | int sdr_sh,
|
893 | b068d6a7 | j_mayer | target_phys_addr_t hash, |
894 | b068d6a7 | j_mayer | target_phys_addr_t mask) |
895 | 12de9a39 | j_mayer | { |
896 | 6f2d8978 | j_mayer | return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask); |
897 | 12de9a39 | j_mayer | } |
898 | 12de9a39 | j_mayer | |
899 | a11b8151 | j_mayer | static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx, |
900 | a11b8151 | j_mayer | target_ulong eaddr, int rw, int type) |
901 | 79aceca5 | bellard | { |
902 | 12de9a39 | j_mayer | target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask; |
903 | caa4039c | j_mayer | target_ulong sr, vsid, vsid_mask, pgidx, page_mask; |
904 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
905 | caa4039c | j_mayer | int attr;
|
906 | 9a64fbe4 | bellard | #endif
|
907 | 0411a972 | j_mayer | int ds, vsid_sh, sdr_sh, pr;
|
908 | caa4039c | j_mayer | int ret, ret2;
|
909 | caa4039c | j_mayer | |
910 | 0411a972 | j_mayer | pr = msr_pr; |
911 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
912 | add78955 | j_mayer | if (env->mmu_model & POWERPC_MMU_64) {
|
913 | 12de9a39 | j_mayer | #if defined (DEBUG_MMU)
|
914 | 12de9a39 | j_mayer | if (loglevel != 0) { |
915 | 12de9a39 | j_mayer | fprintf(logfile, "Check SLBs\n");
|
916 | 12de9a39 | j_mayer | } |
917 | 12de9a39 | j_mayer | #endif
|
918 | caa4039c | j_mayer | ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr); |
919 | caa4039c | j_mayer | if (ret < 0) |
920 | caa4039c | j_mayer | return ret;
|
921 | 0411a972 | j_mayer | ctx->key = ((attr & 0x40) && (pr != 0)) || |
922 | 0411a972 | j_mayer | ((attr & 0x80) && (pr == 0)) ? 1 : 0; |
923 | caa4039c | j_mayer | ds = 0;
|
924 | b227a8e9 | j_mayer | ctx->nx = attr & 0x20 ? 1 : 0; |
925 | caa4039c | j_mayer | vsid_mask = 0x00003FFFFFFFFF80ULL;
|
926 | caa4039c | j_mayer | vsid_sh = 7;
|
927 | caa4039c | j_mayer | sdr_sh = 18;
|
928 | caa4039c | j_mayer | sdr_mask = 0x3FF80;
|
929 | caa4039c | j_mayer | } else
|
930 | caa4039c | j_mayer | #endif /* defined(TARGET_PPC64) */ |
931 | caa4039c | j_mayer | { |
932 | caa4039c | j_mayer | sr = env->sr[eaddr >> 28];
|
933 | caa4039c | j_mayer | page_mask = 0x0FFFFFFF;
|
934 | 0411a972 | j_mayer | ctx->key = (((sr & 0x20000000) && (pr != 0)) || |
935 | 0411a972 | j_mayer | ((sr & 0x40000000) && (pr == 0))) ? 1 : 0; |
936 | caa4039c | j_mayer | ds = sr & 0x80000000 ? 1 : 0; |
937 | b227a8e9 | j_mayer | ctx->nx = sr & 0x10000000 ? 1 : 0; |
938 | caa4039c | j_mayer | vsid = sr & 0x00FFFFFF;
|
939 | caa4039c | j_mayer | vsid_mask = 0x01FFFFC0;
|
940 | caa4039c | j_mayer | vsid_sh = 6;
|
941 | caa4039c | j_mayer | sdr_sh = 16;
|
942 | caa4039c | j_mayer | sdr_mask = 0xFFC0;
|
943 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
944 | caa4039c | j_mayer | if (loglevel != 0) { |
945 | 6b542af7 | j_mayer | fprintf(logfile, "Check segment v=" ADDRX " %d " ADDRX |
946 | 6b542af7 | j_mayer | " nip=" ADDRX " lr=" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n", |
947 | caa4039c | j_mayer | eaddr, (int)(eaddr >> 28), sr, env->nip, |
948 | 0411a972 | j_mayer | env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0, |
949 | 0411a972 | j_mayer | rw, type); |
950 | caa4039c | j_mayer | } |
951 | 9a64fbe4 | bellard | #endif
|
952 | caa4039c | j_mayer | } |
953 | 12de9a39 | j_mayer | #if defined (DEBUG_MMU)
|
954 | 12de9a39 | j_mayer | if (loglevel != 0) { |
955 | 12de9a39 | j_mayer | fprintf(logfile, "pte segment: key=%d ds %d nx %d vsid " ADDRX "\n", |
956 | b227a8e9 | j_mayer | ctx->key, ds, ctx->nx, vsid); |
957 | 12de9a39 | j_mayer | } |
958 | 12de9a39 | j_mayer | #endif
|
959 | caa4039c | j_mayer | ret = -1;
|
960 | caa4039c | j_mayer | if (!ds) {
|
961 | 9a64fbe4 | bellard | /* Check if instruction fetch is allowed, if needed */
|
962 | b227a8e9 | j_mayer | if (type != ACCESS_CODE || ctx->nx == 0) { |
963 | 9a64fbe4 | bellard | /* Page address translation */
|
964 | 76a66253 | j_mayer | /* Primary table address */
|
965 | 76a66253 | j_mayer | sdr = env->sdr1; |
966 | 12de9a39 | j_mayer | pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS; |
967 | 12de9a39 | j_mayer | #if defined(TARGET_PPC64)
|
968 | add78955 | j_mayer | if (env->mmu_model & POWERPC_MMU_64) {
|
969 | 12de9a39 | j_mayer | htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F)); |
970 | 12de9a39 | j_mayer | /* XXX: this is false for 1 TB segments */
|
971 | 12de9a39 | j_mayer | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
972 | 12de9a39 | j_mayer | } else
|
973 | 12de9a39 | j_mayer | #endif
|
974 | 12de9a39 | j_mayer | { |
975 | 12de9a39 | j_mayer | htab_mask = sdr & 0x000001FF;
|
976 | 12de9a39 | j_mayer | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
977 | 12de9a39 | j_mayer | } |
978 | 12de9a39 | j_mayer | mask = (htab_mask << sdr_sh) | sdr_mask; |
979 | 12de9a39 | j_mayer | #if defined (DEBUG_MMU)
|
980 | 12de9a39 | j_mayer | if (loglevel != 0) { |
981 | 6b542af7 | j_mayer | fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX |
982 | 6b542af7 | j_mayer | " mask " PADDRX " " ADDRX "\n", |
983 | 6b542af7 | j_mayer | sdr, sdr_sh, hash, mask, page_mask); |
984 | 12de9a39 | j_mayer | } |
985 | 12de9a39 | j_mayer | #endif
|
986 | caa4039c | j_mayer | ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
987 | 76a66253 | j_mayer | /* Secondary table address */
|
988 | caa4039c | j_mayer | hash = (~hash) & vsid_mask; |
989 | 12de9a39 | j_mayer | #if defined (DEBUG_MMU)
|
990 | 12de9a39 | j_mayer | if (loglevel != 0) { |
991 | 6b542af7 | j_mayer | fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX |
992 | 6b542af7 | j_mayer | " mask " PADDRX "\n", |
993 | 6b542af7 | j_mayer | sdr, sdr_sh, hash, mask); |
994 | 12de9a39 | j_mayer | } |
995 | 12de9a39 | j_mayer | #endif
|
996 | caa4039c | j_mayer | ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
997 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
998 | add78955 | j_mayer | if (env->mmu_model & POWERPC_MMU_64) {
|
999 | caa4039c | j_mayer | /* Only 5 bits of the page index are used in the AVPN */
|
1000 | caa4039c | j_mayer | ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80); |
1001 | caa4039c | j_mayer | } else
|
1002 | caa4039c | j_mayer | #endif
|
1003 | caa4039c | j_mayer | { |
1004 | caa4039c | j_mayer | ctx->ptem = (vsid << 7) | (pgidx >> 10); |
1005 | caa4039c | j_mayer | } |
1006 | 76a66253 | j_mayer | /* Initialize real address with an invalid value */
|
1007 | 6f2d8978 | j_mayer | ctx->raddr = (target_phys_addr_t)-1ULL;
|
1008 | 7dbe11ac | j_mayer | if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
|
1009 | 7dbe11ac | j_mayer | env->mmu_model == POWERPC_MMU_SOFT_74xx)) { |
1010 | 76a66253 | j_mayer | /* Software TLB search */
|
1011 | 76a66253 | j_mayer | ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); |
1012 | 76a66253 | j_mayer | } else {
|
1013 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
1014 | 4a057712 | j_mayer | if (loglevel != 0) { |
1015 | 6b542af7 | j_mayer | fprintf(logfile, "0 sdr1=" PADDRX " vsid=" ADDRX " " |
1016 | 6b542af7 | j_mayer | "api=" ADDRX " hash=" PADDRX |
1017 | 6b542af7 | j_mayer | " pg_addr=" PADDRX "\n", |
1018 | 6b542af7 | j_mayer | sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
|
1019 | 76a66253 | j_mayer | } |
1020 | 9a64fbe4 | bellard | #endif
|
1021 | 76a66253 | j_mayer | /* Primary table lookup */
|
1022 | b227a8e9 | j_mayer | ret = find_pte(env, ctx, 0, rw, type);
|
1023 | 76a66253 | j_mayer | if (ret < 0) { |
1024 | 76a66253 | j_mayer | /* Secondary table lookup */
|
1025 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
1026 | 4a057712 | j_mayer | if (eaddr != 0xEFFFFFFF && loglevel != 0) { |
1027 | 6b542af7 | j_mayer | fprintf(logfile, "1 sdr1=" PADDRX " vsid=" ADDRX " " |
1028 | 6b542af7 | j_mayer | "api=" ADDRX " hash=" PADDRX |
1029 | 6b542af7 | j_mayer | " pg_addr=" PADDRX "\n", |
1030 | 6b542af7 | j_mayer | sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
|
1031 | 76a66253 | j_mayer | } |
1032 | 9a64fbe4 | bellard | #endif
|
1033 | b227a8e9 | j_mayer | ret2 = find_pte(env, ctx, 1, rw, type);
|
1034 | 76a66253 | j_mayer | if (ret2 != -1) |
1035 | 76a66253 | j_mayer | ret = ret2; |
1036 | 76a66253 | j_mayer | } |
1037 | 9a64fbe4 | bellard | } |
1038 | 0411a972 | j_mayer | #if defined (DUMP_PAGE_TABLES)
|
1039 | b33c17e1 | j_mayer | if (loglevel != 0) { |
1040 | b33c17e1 | j_mayer | target_phys_addr_t curaddr; |
1041 | b33c17e1 | j_mayer | uint32_t a0, a1, a2, a3; |
1042 | 6b542af7 | j_mayer | fprintf(logfile, "Page table: " PADDRX " len " PADDRX "\n", |
1043 | b33c17e1 | j_mayer | sdr, mask + 0x80);
|
1044 | b33c17e1 | j_mayer | for (curaddr = sdr; curaddr < (sdr + mask + 0x80); |
1045 | b33c17e1 | j_mayer | curaddr += 16) {
|
1046 | b33c17e1 | j_mayer | a0 = ldl_phys(curaddr); |
1047 | b33c17e1 | j_mayer | a1 = ldl_phys(curaddr + 4);
|
1048 | b33c17e1 | j_mayer | a2 = ldl_phys(curaddr + 8);
|
1049 | b33c17e1 | j_mayer | a3 = ldl_phys(curaddr + 12);
|
1050 | b33c17e1 | j_mayer | if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) { |
1051 | 6b542af7 | j_mayer | fprintf(logfile, PADDRX ": %08x %08x %08x %08x\n",
|
1052 | b33c17e1 | j_mayer | curaddr, a0, a1, a2, a3); |
1053 | 12de9a39 | j_mayer | } |
1054 | b33c17e1 | j_mayer | } |
1055 | b33c17e1 | j_mayer | } |
1056 | 12de9a39 | j_mayer | #endif
|
1057 | 9a64fbe4 | bellard | } else {
|
1058 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
1059 | 4a057712 | j_mayer | if (loglevel != 0) |
1060 | 76a66253 | j_mayer | fprintf(logfile, "No access allowed\n");
|
1061 | 9a64fbe4 | bellard | #endif
|
1062 | 76a66253 | j_mayer | ret = -3;
|
1063 | 9a64fbe4 | bellard | } |
1064 | 9a64fbe4 | bellard | } else {
|
1065 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
1066 | 4a057712 | j_mayer | if (loglevel != 0) |
1067 | 76a66253 | j_mayer | fprintf(logfile, "direct store...\n");
|
1068 | 9a64fbe4 | bellard | #endif
|
1069 | 9a64fbe4 | bellard | /* Direct-store segment : absolutely *BUGGY* for now */
|
1070 | 9a64fbe4 | bellard | switch (type) {
|
1071 | 9a64fbe4 | bellard | case ACCESS_INT:
|
1072 | 9a64fbe4 | bellard | /* Integer load/store : only access allowed */
|
1073 | 9a64fbe4 | bellard | break;
|
1074 | 9a64fbe4 | bellard | case ACCESS_CODE:
|
1075 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
1076 | 9a64fbe4 | bellard | return -4; |
1077 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
1078 | 9a64fbe4 | bellard | /* Floating point load/store */
|
1079 | 9a64fbe4 | bellard | return -4; |
1080 | 9a64fbe4 | bellard | case ACCESS_RES:
|
1081 | 9a64fbe4 | bellard | /* lwarx, ldarx or srwcx. */
|
1082 | 9a64fbe4 | bellard | return -4; |
1083 | 9a64fbe4 | bellard | case ACCESS_CACHE:
|
1084 | 9a64fbe4 | bellard | /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
|
1085 | 9a64fbe4 | bellard | /* Should make the instruction do no-op.
|
1086 | 9a64fbe4 | bellard | * As it already do no-op, it's quite easy :-)
|
1087 | 9a64fbe4 | bellard | */
|
1088 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1089 | 9a64fbe4 | bellard | return 0; |
1090 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
1091 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
1092 | 9a64fbe4 | bellard | return -4; |
1093 | 9a64fbe4 | bellard | default:
|
1094 | 9a64fbe4 | bellard | if (logfile) {
|
1095 | 9a64fbe4 | bellard | fprintf(logfile, "ERROR: instruction should not need "
|
1096 | 9a64fbe4 | bellard | "address translation\n");
|
1097 | 9a64fbe4 | bellard | } |
1098 | 9a64fbe4 | bellard | return -4; |
1099 | 9a64fbe4 | bellard | } |
1100 | 76a66253 | j_mayer | if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { |
1101 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1102 | 9a64fbe4 | bellard | ret = 2;
|
1103 | 9a64fbe4 | bellard | } else {
|
1104 | 9a64fbe4 | bellard | ret = -2;
|
1105 | 9a64fbe4 | bellard | } |
1106 | 79aceca5 | bellard | } |
1107 | 9a64fbe4 | bellard | |
1108 | 9a64fbe4 | bellard | return ret;
|
1109 | 79aceca5 | bellard | } |
1110 | 79aceca5 | bellard | |
1111 | c294fc58 | j_mayer | /* Generic TLB check function for embedded PowerPC implementations */
|
1112 | a11b8151 | j_mayer | static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb, |
1113 | a11b8151 | j_mayer | target_phys_addr_t *raddrp, |
1114 | a11b8151 | j_mayer | target_ulong address, |
1115 | a11b8151 | j_mayer | uint32_t pid, int ext, int i) |
1116 | c294fc58 | j_mayer | { |
1117 | c294fc58 | j_mayer | target_ulong mask; |
1118 | c294fc58 | j_mayer | |
1119 | c294fc58 | j_mayer | /* Check valid flag */
|
1120 | c294fc58 | j_mayer | if (!(tlb->prot & PAGE_VALID)) {
|
1121 | c294fc58 | j_mayer | if (loglevel != 0) |
1122 | c294fc58 | j_mayer | fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
|
1123 | c294fc58 | j_mayer | return -1; |
1124 | c294fc58 | j_mayer | } |
1125 | c294fc58 | j_mayer | mask = ~(tlb->size - 1);
|
1126 | daf4f96e | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
1127 | c294fc58 | j_mayer | if (loglevel != 0) { |
1128 | 6b542af7 | j_mayer | fprintf(logfile, "%s: TLB %d address " ADDRX " PID %u <=> " ADDRX |
1129 | 6b542af7 | j_mayer | " " ADDRX " %u\n", |
1130 | 6b542af7 | j_mayer | __func__, i, address, pid, tlb->EPN, mask, (uint32_t)tlb->PID); |
1131 | c294fc58 | j_mayer | } |
1132 | daf4f96e | j_mayer | #endif
|
1133 | c294fc58 | j_mayer | /* Check PID */
|
1134 | 36081602 | j_mayer | if (tlb->PID != 0 && tlb->PID != pid) |
1135 | c294fc58 | j_mayer | return -1; |
1136 | c294fc58 | j_mayer | /* Check effective address */
|
1137 | c294fc58 | j_mayer | if ((address & mask) != tlb->EPN)
|
1138 | c294fc58 | j_mayer | return -1; |
1139 | c294fc58 | j_mayer | *raddrp = (tlb->RPN & mask) | (address & ~mask); |
1140 | 9706285b | j_mayer | #if (TARGET_PHYS_ADDR_BITS >= 36) |
1141 | 36081602 | j_mayer | if (ext) {
|
1142 | 36081602 | j_mayer | /* Extend the physical address to 36 bits */
|
1143 | 36081602 | j_mayer | *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32; |
1144 | 36081602 | j_mayer | } |
1145 | 9706285b | j_mayer | #endif
|
1146 | c294fc58 | j_mayer | |
1147 | c294fc58 | j_mayer | return 0; |
1148 | c294fc58 | j_mayer | } |
1149 | c294fc58 | j_mayer | |
1150 | c294fc58 | j_mayer | /* Generic TLB search function for PowerPC embedded implementations */
|
1151 | 36081602 | j_mayer | int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
|
1152 | c294fc58 | j_mayer | { |
1153 | c294fc58 | j_mayer | ppcemb_tlb_t *tlb; |
1154 | c294fc58 | j_mayer | target_phys_addr_t raddr; |
1155 | c294fc58 | j_mayer | int i, ret;
|
1156 | c294fc58 | j_mayer | |
1157 | c294fc58 | j_mayer | /* Default return value is no match */
|
1158 | c294fc58 | j_mayer | ret = -1;
|
1159 | a750fc0b | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1160 | c294fc58 | j_mayer | tlb = &env->tlb[i].tlbe; |
1161 | 36081602 | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) { |
1162 | c294fc58 | j_mayer | ret = i; |
1163 | c294fc58 | j_mayer | break;
|
1164 | c294fc58 | j_mayer | } |
1165 | c294fc58 | j_mayer | } |
1166 | c294fc58 | j_mayer | |
1167 | c294fc58 | j_mayer | return ret;
|
1168 | c294fc58 | j_mayer | } |
1169 | c294fc58 | j_mayer | |
1170 | daf4f96e | j_mayer | /* Helpers specific to PowerPC 40x implementations */
|
1171 | a11b8151 | j_mayer | static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env) |
1172 | a750fc0b | j_mayer | { |
1173 | a750fc0b | j_mayer | ppcemb_tlb_t *tlb; |
1174 | a750fc0b | j_mayer | int i;
|
1175 | a750fc0b | j_mayer | |
1176 | a750fc0b | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1177 | a750fc0b | j_mayer | tlb = &env->tlb[i].tlbe; |
1178 | daf4f96e | j_mayer | tlb->prot &= ~PAGE_VALID; |
1179 | a750fc0b | j_mayer | } |
1180 | daf4f96e | j_mayer | tlb_flush(env, 1);
|
1181 | a750fc0b | j_mayer | } |
1182 | a750fc0b | j_mayer | |
1183 | a11b8151 | j_mayer | static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env, |
1184 | a11b8151 | j_mayer | target_ulong eaddr, |
1185 | a11b8151 | j_mayer | uint32_t pid) |
1186 | 0a032cbe | j_mayer | { |
1187 | daf4f96e | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1188 | 0a032cbe | j_mayer | ppcemb_tlb_t *tlb; |
1189 | daf4f96e | j_mayer | target_phys_addr_t raddr; |
1190 | daf4f96e | j_mayer | target_ulong page, end; |
1191 | 0a032cbe | j_mayer | int i;
|
1192 | 0a032cbe | j_mayer | |
1193 | 0a032cbe | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1194 | 0a032cbe | j_mayer | tlb = &env->tlb[i].tlbe; |
1195 | daf4f96e | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) { |
1196 | 0a032cbe | j_mayer | end = tlb->EPN + tlb->size; |
1197 | 0a032cbe | j_mayer | for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
|
1198 | 0a032cbe | j_mayer | tlb_flush_page(env, page); |
1199 | 0a032cbe | j_mayer | tlb->prot &= ~PAGE_VALID; |
1200 | daf4f96e | j_mayer | break;
|
1201 | 0a032cbe | j_mayer | } |
1202 | 0a032cbe | j_mayer | } |
1203 | daf4f96e | j_mayer | #else
|
1204 | daf4f96e | j_mayer | ppc4xx_tlb_invalidate_all(env); |
1205 | daf4f96e | j_mayer | #endif
|
1206 | 0a032cbe | j_mayer | } |
1207 | 0a032cbe | j_mayer | |
1208 | 36081602 | j_mayer | int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
|
1209 | e96efcfc | j_mayer | target_ulong address, int rw, int access_type) |
1210 | a8dea12f | j_mayer | { |
1211 | a8dea12f | j_mayer | ppcemb_tlb_t *tlb; |
1212 | a8dea12f | j_mayer | target_phys_addr_t raddr; |
1213 | 0411a972 | j_mayer | int i, ret, zsel, zpr, pr;
|
1214 | 3b46e624 | ths | |
1215 | c55e9aef | j_mayer | ret = -1;
|
1216 | 6f2d8978 | j_mayer | raddr = (target_phys_addr_t)-1ULL;
|
1217 | 0411a972 | j_mayer | pr = msr_pr; |
1218 | a8dea12f | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1219 | a8dea12f | j_mayer | tlb = &env->tlb[i].tlbe; |
1220 | 36081602 | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
1221 | 36081602 | j_mayer | env->spr[SPR_40x_PID], 0, i) < 0) |
1222 | a8dea12f | j_mayer | continue;
|
1223 | a8dea12f | j_mayer | zsel = (tlb->attr >> 4) & 0xF; |
1224 | a8dea12f | j_mayer | zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3; |
1225 | daf4f96e | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
1226 | 4a057712 | j_mayer | if (loglevel != 0) { |
1227 | a8dea12f | j_mayer | fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
|
1228 | a8dea12f | j_mayer | __func__, i, zsel, zpr, rw, tlb->attr); |
1229 | a8dea12f | j_mayer | } |
1230 | daf4f96e | j_mayer | #endif
|
1231 | b227a8e9 | j_mayer | /* Check execute enable bit */
|
1232 | b227a8e9 | j_mayer | switch (zpr) {
|
1233 | b227a8e9 | j_mayer | case 0x2: |
1234 | 0411a972 | j_mayer | if (pr != 0) |
1235 | b227a8e9 | j_mayer | goto check_perms;
|
1236 | b227a8e9 | j_mayer | /* No break here */
|
1237 | b227a8e9 | j_mayer | case 0x3: |
1238 | b227a8e9 | j_mayer | /* All accesses granted */
|
1239 | b227a8e9 | j_mayer | ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
1240 | b227a8e9 | j_mayer | ret = 0;
|
1241 | b227a8e9 | j_mayer | break;
|
1242 | b227a8e9 | j_mayer | case 0x0: |
1243 | 0411a972 | j_mayer | if (pr != 0) { |
1244 | b227a8e9 | j_mayer | ctx->prot = 0;
|
1245 | b227a8e9 | j_mayer | ret = -2;
|
1246 | a8dea12f | j_mayer | break;
|
1247 | a8dea12f | j_mayer | } |
1248 | b227a8e9 | j_mayer | /* No break here */
|
1249 | b227a8e9 | j_mayer | case 0x1: |
1250 | b227a8e9 | j_mayer | check_perms:
|
1251 | b227a8e9 | j_mayer | /* Check from TLB entry */
|
1252 | b227a8e9 | j_mayer | /* XXX: there is a problem here or in the TLB fill code... */
|
1253 | b227a8e9 | j_mayer | ctx->prot = tlb->prot; |
1254 | b227a8e9 | j_mayer | ctx->prot |= PAGE_EXEC; |
1255 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, access_type); |
1256 | b227a8e9 | j_mayer | break;
|
1257 | a8dea12f | j_mayer | } |
1258 | a8dea12f | j_mayer | if (ret >= 0) { |
1259 | a8dea12f | j_mayer | ctx->raddr = raddr; |
1260 | daf4f96e | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
1261 | 4a057712 | j_mayer | if (loglevel != 0) { |
1262 | 6b542af7 | j_mayer | fprintf(logfile, "%s: access granted " ADDRX " => " PADDRX |
1263 | c55e9aef | j_mayer | " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
|
1264 | c55e9aef | j_mayer | ret); |
1265 | a8dea12f | j_mayer | } |
1266 | daf4f96e | j_mayer | #endif
|
1267 | c55e9aef | j_mayer | return 0; |
1268 | a8dea12f | j_mayer | } |
1269 | a8dea12f | j_mayer | } |
1270 | daf4f96e | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
1271 | 4a057712 | j_mayer | if (loglevel != 0) { |
1272 | 6b542af7 | j_mayer | fprintf(logfile, "%s: access refused " ADDRX " => " PADDRX |
1273 | c55e9aef | j_mayer | " %d %d\n", __func__, address, raddr, ctx->prot,
|
1274 | c55e9aef | j_mayer | ret); |
1275 | c55e9aef | j_mayer | } |
1276 | daf4f96e | j_mayer | #endif
|
1277 | 3b46e624 | ths | |
1278 | a8dea12f | j_mayer | return ret;
|
1279 | a8dea12f | j_mayer | } |
1280 | a8dea12f | j_mayer | |
1281 | c294fc58 | j_mayer | void store_40x_sler (CPUPPCState *env, uint32_t val)
|
1282 | c294fc58 | j_mayer | { |
1283 | c294fc58 | j_mayer | /* XXX: TO BE FIXED */
|
1284 | c294fc58 | j_mayer | if (val != 0x00000000) { |
1285 | c294fc58 | j_mayer | cpu_abort(env, "Little-endian regions are not supported by now\n");
|
1286 | c294fc58 | j_mayer | } |
1287 | c294fc58 | j_mayer | env->spr[SPR_405_SLER] = val; |
1288 | c294fc58 | j_mayer | } |
1289 | c294fc58 | j_mayer | |
1290 | 5eb7995e | j_mayer | int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
|
1291 | 5eb7995e | j_mayer | target_ulong address, int rw,
|
1292 | 5eb7995e | j_mayer | int access_type)
|
1293 | 5eb7995e | j_mayer | { |
1294 | 5eb7995e | j_mayer | ppcemb_tlb_t *tlb; |
1295 | 5eb7995e | j_mayer | target_phys_addr_t raddr; |
1296 | 5eb7995e | j_mayer | int i, prot, ret;
|
1297 | 5eb7995e | j_mayer | |
1298 | 5eb7995e | j_mayer | ret = -1;
|
1299 | 6f2d8978 | j_mayer | raddr = (target_phys_addr_t)-1ULL;
|
1300 | 5eb7995e | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1301 | 5eb7995e | j_mayer | tlb = &env->tlb[i].tlbe; |
1302 | 5eb7995e | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
1303 | 5eb7995e | j_mayer | env->spr[SPR_BOOKE_PID], 1, i) < 0) |
1304 | 5eb7995e | j_mayer | continue;
|
1305 | 0411a972 | j_mayer | if (msr_pr != 0) |
1306 | 5eb7995e | j_mayer | prot = tlb->prot & 0xF;
|
1307 | 5eb7995e | j_mayer | else
|
1308 | 5eb7995e | j_mayer | prot = (tlb->prot >> 4) & 0xF; |
1309 | 5eb7995e | j_mayer | /* Check the address space */
|
1310 | 5eb7995e | j_mayer | if (access_type == ACCESS_CODE) {
|
1311 | d26bfc9a | j_mayer | if (msr_ir != (tlb->attr & 1)) |
1312 | 5eb7995e | j_mayer | continue;
|
1313 | 5eb7995e | j_mayer | ctx->prot = prot; |
1314 | 5eb7995e | j_mayer | if (prot & PAGE_EXEC) {
|
1315 | 5eb7995e | j_mayer | ret = 0;
|
1316 | 5eb7995e | j_mayer | break;
|
1317 | 5eb7995e | j_mayer | } |
1318 | 5eb7995e | j_mayer | ret = -3;
|
1319 | 5eb7995e | j_mayer | } else {
|
1320 | d26bfc9a | j_mayer | if (msr_dr != (tlb->attr & 1)) |
1321 | 5eb7995e | j_mayer | continue;
|
1322 | 5eb7995e | j_mayer | ctx->prot = prot; |
1323 | 5eb7995e | j_mayer | if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
|
1324 | 5eb7995e | j_mayer | ret = 0;
|
1325 | 5eb7995e | j_mayer | break;
|
1326 | 5eb7995e | j_mayer | } |
1327 | 5eb7995e | j_mayer | ret = -2;
|
1328 | 5eb7995e | j_mayer | } |
1329 | 5eb7995e | j_mayer | } |
1330 | 5eb7995e | j_mayer | if (ret >= 0) |
1331 | 5eb7995e | j_mayer | ctx->raddr = raddr; |
1332 | 5eb7995e | j_mayer | |
1333 | 5eb7995e | j_mayer | return ret;
|
1334 | 5eb7995e | j_mayer | } |
1335 | 5eb7995e | j_mayer | |
1336 | a11b8151 | j_mayer | static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx, |
1337 | a11b8151 | j_mayer | target_ulong eaddr, int rw)
|
1338 | 76a66253 | j_mayer | { |
1339 | 76a66253 | j_mayer | int in_plb, ret;
|
1340 | 3b46e624 | ths | |
1341 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1342 | b227a8e9 | j_mayer | ctx->prot = PAGE_READ | PAGE_EXEC; |
1343 | 76a66253 | j_mayer | ret = 0;
|
1344 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1345 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1346 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1347 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1348 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1349 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1350 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1351 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1352 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1353 | caa4039c | j_mayer | break;
|
1354 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
1355 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1356 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1357 | caa4039c | j_mayer | /* Real address are 60 bits long */
|
1358 | a750fc0b | j_mayer | ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
|
1359 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1360 | caa4039c | j_mayer | break;
|
1361 | 9706285b | j_mayer | #endif
|
1362 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1363 | caa4039c | j_mayer | if (unlikely(msr_pe != 0)) { |
1364 | caa4039c | j_mayer | /* 403 family add some particular protections,
|
1365 | caa4039c | j_mayer | * using PBL/PBU registers for accesses with no translation.
|
1366 | caa4039c | j_mayer | */
|
1367 | caa4039c | j_mayer | in_plb = |
1368 | caa4039c | j_mayer | /* Check PLB validity */
|
1369 | caa4039c | j_mayer | (env->pb[0] < env->pb[1] && |
1370 | caa4039c | j_mayer | /* and address in plb area */
|
1371 | caa4039c | j_mayer | eaddr >= env->pb[0] && eaddr < env->pb[1]) || |
1372 | caa4039c | j_mayer | (env->pb[2] < env->pb[3] && |
1373 | caa4039c | j_mayer | eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; |
1374 | caa4039c | j_mayer | if (in_plb ^ msr_px) {
|
1375 | caa4039c | j_mayer | /* Access in protected area */
|
1376 | caa4039c | j_mayer | if (rw == 1) { |
1377 | caa4039c | j_mayer | /* Access is not allowed */
|
1378 | caa4039c | j_mayer | ret = -2;
|
1379 | caa4039c | j_mayer | } |
1380 | caa4039c | j_mayer | } else {
|
1381 | caa4039c | j_mayer | /* Read-write access is allowed */
|
1382 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1383 | 76a66253 | j_mayer | } |
1384 | 76a66253 | j_mayer | } |
1385 | e1833e1f | j_mayer | break;
|
1386 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1387 | b4095fed | j_mayer | /* XXX: TODO */
|
1388 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1389 | b4095fed | j_mayer | break;
|
1390 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1391 | caa4039c | j_mayer | /* XXX: TODO */
|
1392 | caa4039c | j_mayer | cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
1393 | caa4039c | j_mayer | break;
|
1394 | caa4039c | j_mayer | default:
|
1395 | caa4039c | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1396 | caa4039c | j_mayer | return -1; |
1397 | 76a66253 | j_mayer | } |
1398 | 76a66253 | j_mayer | |
1399 | 76a66253 | j_mayer | return ret;
|
1400 | 76a66253 | j_mayer | } |
1401 | 76a66253 | j_mayer | |
1402 | 76a66253 | j_mayer | int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
|
1403 | faadf50e | j_mayer | int rw, int access_type) |
1404 | 9a64fbe4 | bellard | { |
1405 | 9a64fbe4 | bellard | int ret;
|
1406 | 0411a972 | j_mayer | |
1407 | 514fb8c1 | bellard | #if 0
|
1408 | 4a057712 | j_mayer | if (loglevel != 0) {
|
1409 | 9a64fbe4 | bellard | fprintf(logfile, "%s\n", __func__);
|
1410 | 9a64fbe4 | bellard | }
|
1411 | d9bce9d9 | j_mayer | #endif
|
1412 | 4b3686fa | bellard | if ((access_type == ACCESS_CODE && msr_ir == 0) || |
1413 | 4b3686fa | bellard | (access_type != ACCESS_CODE && msr_dr == 0)) {
|
1414 | 9a64fbe4 | bellard | /* No address translation */
|
1415 | 76a66253 | j_mayer | ret = check_physical(env, ctx, eaddr, rw); |
1416 | 9a64fbe4 | bellard | } else {
|
1417 | c55e9aef | j_mayer | ret = -1;
|
1418 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1419 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1420 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1421 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1422 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1423 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1424 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1425 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1426 | c55e9aef | j_mayer | #endif
|
1427 | faadf50e | j_mayer | /* Try to find a BAT */
|
1428 | faadf50e | j_mayer | if (env->nb_BATs != 0) |
1429 | faadf50e | j_mayer | ret = get_bat(env, ctx, eaddr, rw, access_type); |
1430 | a8dea12f | j_mayer | if (ret < 0) { |
1431 | c55e9aef | j_mayer | /* We didn't match any BAT entry or don't have BATs */
|
1432 | a8dea12f | j_mayer | ret = get_segment(env, ctx, eaddr, rw, access_type); |
1433 | a8dea12f | j_mayer | } |
1434 | a8dea12f | j_mayer | break;
|
1435 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1436 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1437 | 36081602 | j_mayer | ret = mmu40x_get_physical_address(env, ctx, eaddr, |
1438 | a8dea12f | j_mayer | rw, access_type); |
1439 | a8dea12f | j_mayer | break;
|
1440 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1441 | 5eb7995e | j_mayer | ret = mmubooke_get_physical_address(env, ctx, eaddr, |
1442 | 5eb7995e | j_mayer | rw, access_type); |
1443 | 5eb7995e | j_mayer | break;
|
1444 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1445 | b4095fed | j_mayer | /* XXX: TODO */
|
1446 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1447 | b4095fed | j_mayer | break;
|
1448 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1449 | c55e9aef | j_mayer | /* XXX: TODO */
|
1450 | c55e9aef | j_mayer | cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
1451 | c55e9aef | j_mayer | return -1; |
1452 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1453 | b4095fed | j_mayer | cpu_abort(env, "PowerPC in real mode do not do any translation\n");
|
1454 | 2662a059 | j_mayer | return -1; |
1455 | c55e9aef | j_mayer | default:
|
1456 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1457 | a8dea12f | j_mayer | return -1; |
1458 | 9a64fbe4 | bellard | } |
1459 | 9a64fbe4 | bellard | } |
1460 | 514fb8c1 | bellard | #if 0
|
1461 | 4a057712 | j_mayer | if (loglevel != 0) {
|
1462 | 4a057712 | j_mayer | fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
|
1463 | c55e9aef | j_mayer | __func__, eaddr, ret, ctx->raddr);
|
1464 | a541f297 | bellard | }
|
1465 | 76a66253 | j_mayer | #endif
|
1466 | d9bce9d9 | j_mayer | |
1467 | 9a64fbe4 | bellard | return ret;
|
1468 | 9a64fbe4 | bellard | } |
1469 | 9a64fbe4 | bellard | |
1470 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
1471 | a6b025d3 | bellard | { |
1472 | 76a66253 | j_mayer | mmu_ctx_t ctx; |
1473 | a6b025d3 | bellard | |
1474 | faadf50e | j_mayer | if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0)) |
1475 | a6b025d3 | bellard | return -1; |
1476 | 76a66253 | j_mayer | |
1477 | 76a66253 | j_mayer | return ctx.raddr & TARGET_PAGE_MASK;
|
1478 | a6b025d3 | bellard | } |
1479 | 9a64fbe4 | bellard | |
1480 | 9a64fbe4 | bellard | /* Perform address translation */
|
1481 | e96efcfc | j_mayer | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
1482 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
1483 | 9a64fbe4 | bellard | { |
1484 | 76a66253 | j_mayer | mmu_ctx_t ctx; |
1485 | a541f297 | bellard | int access_type;
|
1486 | 9a64fbe4 | bellard | int ret = 0; |
1487 | d9bce9d9 | j_mayer | |
1488 | b769d8fe | bellard | if (rw == 2) { |
1489 | b769d8fe | bellard | /* code access */
|
1490 | b769d8fe | bellard | rw = 0;
|
1491 | b769d8fe | bellard | access_type = ACCESS_CODE; |
1492 | b769d8fe | bellard | } else {
|
1493 | b769d8fe | bellard | /* data access */
|
1494 | b769d8fe | bellard | /* XXX: put correct access by using cpu_restore_state()
|
1495 | b769d8fe | bellard | correctly */
|
1496 | b769d8fe | bellard | access_type = ACCESS_INT; |
1497 | b769d8fe | bellard | // access_type = env->access_type;
|
1498 | b769d8fe | bellard | } |
1499 | faadf50e | j_mayer | ret = get_physical_address(env, &ctx, address, rw, access_type); |
1500 | 9a64fbe4 | bellard | if (ret == 0) { |
1501 | b227a8e9 | j_mayer | ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK, |
1502 | b227a8e9 | j_mayer | ctx.raddr & TARGET_PAGE_MASK, ctx.prot, |
1503 | b227a8e9 | j_mayer | mmu_idx, is_softmmu); |
1504 | 9a64fbe4 | bellard | } else if (ret < 0) { |
1505 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
1506 | 4a057712 | j_mayer | if (loglevel != 0) |
1507 | 76a66253 | j_mayer | cpu_dump_state(env, logfile, fprintf, 0);
|
1508 | 9a64fbe4 | bellard | #endif
|
1509 | 9a64fbe4 | bellard | if (access_type == ACCESS_CODE) {
|
1510 | 9a64fbe4 | bellard | switch (ret) {
|
1511 | 9a64fbe4 | bellard | case -1: |
1512 | 76a66253 | j_mayer | /* No matches in page tables or TLB */
|
1513 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1514 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1515 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_IFTLB; |
1516 | 8f793433 | j_mayer | env->error_code = 1 << 18; |
1517 | 76a66253 | j_mayer | env->spr[SPR_IMISS] = address; |
1518 | 76a66253 | j_mayer | env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
|
1519 | 76a66253 | j_mayer | goto tlb_miss;
|
1520 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1521 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_IFTLB; |
1522 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
1523 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1524 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1525 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ITLB; |
1526 | 8f793433 | j_mayer | env->error_code = 0;
|
1527 | a8dea12f | j_mayer | env->spr[SPR_40x_DEAR] = address; |
1528 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00000000;
|
1529 | c55e9aef | j_mayer | break;
|
1530 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1531 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1532 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1533 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1534 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1535 | c55e9aef | j_mayer | #endif
|
1536 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1537 | 8f793433 | j_mayer | env->error_code = 0x40000000;
|
1538 | 8f793433 | j_mayer | break;
|
1539 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1540 | c55e9aef | j_mayer | /* XXX: TODO */
|
1541 | b4095fed | j_mayer | cpu_abort(env, "BookE MMU model is not implemented\n");
|
1542 | c55e9aef | j_mayer | return -1; |
1543 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1544 | c55e9aef | j_mayer | /* XXX: TODO */
|
1545 | b4095fed | j_mayer | cpu_abort(env, "BookE FSL MMU model is not implemented\n");
|
1546 | c55e9aef | j_mayer | return -1; |
1547 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1548 | b4095fed | j_mayer | /* XXX: TODO */
|
1549 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1550 | b4095fed | j_mayer | break;
|
1551 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1552 | b4095fed | j_mayer | cpu_abort(env, "PowerPC in real mode should never raise "
|
1553 | b4095fed | j_mayer | "any MMU exceptions\n");
|
1554 | 2662a059 | j_mayer | return -1; |
1555 | c55e9aef | j_mayer | default:
|
1556 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1557 | c55e9aef | j_mayer | return -1; |
1558 | 76a66253 | j_mayer | } |
1559 | 9a64fbe4 | bellard | break;
|
1560 | 9a64fbe4 | bellard | case -2: |
1561 | 9a64fbe4 | bellard | /* Access rights violation */
|
1562 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1563 | 8f793433 | j_mayer | env->error_code = 0x08000000;
|
1564 | 9a64fbe4 | bellard | break;
|
1565 | 9a64fbe4 | bellard | case -3: |
1566 | 76a66253 | j_mayer | /* No execute protection violation */
|
1567 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1568 | 8f793433 | j_mayer | env->error_code = 0x10000000;
|
1569 | 9a64fbe4 | bellard | break;
|
1570 | 9a64fbe4 | bellard | case -4: |
1571 | 9a64fbe4 | bellard | /* Direct store exception */
|
1572 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
1573 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1574 | 8f793433 | j_mayer | env->error_code = 0x10000000;
|
1575 | 2be0071f | bellard | break;
|
1576 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
1577 | 2be0071f | bellard | case -5: |
1578 | 2be0071f | bellard | /* No match in segment table */
|
1579 | add78955 | j_mayer | if (env->mmu_model == POWERPC_MMU_620) {
|
1580 | add78955 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1581 | add78955 | j_mayer | /* XXX: this might be incorrect */
|
1582 | add78955 | j_mayer | env->error_code = 0x40000000;
|
1583 | add78955 | j_mayer | } else {
|
1584 | add78955 | j_mayer | env->exception_index = POWERPC_EXCP_ISEG; |
1585 | add78955 | j_mayer | env->error_code = 0;
|
1586 | add78955 | j_mayer | } |
1587 | 9a64fbe4 | bellard | break;
|
1588 | e1833e1f | j_mayer | #endif
|
1589 | 9a64fbe4 | bellard | } |
1590 | 9a64fbe4 | bellard | } else {
|
1591 | 9a64fbe4 | bellard | switch (ret) {
|
1592 | 9a64fbe4 | bellard | case -1: |
1593 | 76a66253 | j_mayer | /* No matches in page tables or TLB */
|
1594 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1595 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1596 | 76a66253 | j_mayer | if (rw == 1) { |
1597 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSTLB; |
1598 | 8f793433 | j_mayer | env->error_code = 1 << 16; |
1599 | 76a66253 | j_mayer | } else {
|
1600 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DLTLB; |
1601 | 8f793433 | j_mayer | env->error_code = 0;
|
1602 | 76a66253 | j_mayer | } |
1603 | 76a66253 | j_mayer | env->spr[SPR_DMISS] = address; |
1604 | 76a66253 | j_mayer | env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
|
1605 | 76a66253 | j_mayer | tlb_miss:
|
1606 | 8f793433 | j_mayer | env->error_code |= ctx.key << 19;
|
1607 | 76a66253 | j_mayer | env->spr[SPR_HASH1] = ctx.pg_addr[0];
|
1608 | 76a66253 | j_mayer | env->spr[SPR_HASH2] = ctx.pg_addr[1];
|
1609 | 8f793433 | j_mayer | break;
|
1610 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1611 | 7dbe11ac | j_mayer | if (rw == 1) { |
1612 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSTLB; |
1613 | 7dbe11ac | j_mayer | } else {
|
1614 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DLTLB; |
1615 | 7dbe11ac | j_mayer | } |
1616 | 7dbe11ac | j_mayer | tlb_miss_74xx:
|
1617 | 7dbe11ac | j_mayer | /* Implement LRU algorithm */
|
1618 | 8f793433 | j_mayer | env->error_code = ctx.key << 19;
|
1619 | 7dbe11ac | j_mayer | env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
|
1620 | 7dbe11ac | j_mayer | ((env->last_way + 1) & (env->nb_ways - 1)); |
1621 | 7dbe11ac | j_mayer | env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
|
1622 | 7dbe11ac | j_mayer | break;
|
1623 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1624 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1625 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DTLB; |
1626 | 8f793433 | j_mayer | env->error_code = 0;
|
1627 | a8dea12f | j_mayer | env->spr[SPR_40x_DEAR] = address; |
1628 | a8dea12f | j_mayer | if (rw)
|
1629 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00800000;
|
1630 | a8dea12f | j_mayer | else
|
1631 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00000000;
|
1632 | c55e9aef | j_mayer | break;
|
1633 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1634 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1635 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1636 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1637 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1638 | c55e9aef | j_mayer | #endif
|
1639 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1640 | 8f793433 | j_mayer | env->error_code = 0;
|
1641 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1642 | 8f793433 | j_mayer | if (rw == 1) |
1643 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x42000000;
|
1644 | 8f793433 | j_mayer | else
|
1645 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x40000000;
|
1646 | 8f793433 | j_mayer | break;
|
1647 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1648 | b4095fed | j_mayer | /* XXX: TODO */
|
1649 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1650 | b4095fed | j_mayer | break;
|
1651 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1652 | c55e9aef | j_mayer | /* XXX: TODO */
|
1653 | b4095fed | j_mayer | cpu_abort(env, "BookE MMU model is not implemented\n");
|
1654 | c55e9aef | j_mayer | return -1; |
1655 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1656 | c55e9aef | j_mayer | /* XXX: TODO */
|
1657 | b4095fed | j_mayer | cpu_abort(env, "BookE FSL MMU model is not implemented\n");
|
1658 | c55e9aef | j_mayer | return -1; |
1659 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1660 | b4095fed | j_mayer | cpu_abort(env, "PowerPC in real mode should never raise "
|
1661 | b4095fed | j_mayer | "any MMU exceptions\n");
|
1662 | 2662a059 | j_mayer | return -1; |
1663 | c55e9aef | j_mayer | default:
|
1664 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1665 | c55e9aef | j_mayer | return -1; |
1666 | 76a66253 | j_mayer | } |
1667 | 9a64fbe4 | bellard | break;
|
1668 | 9a64fbe4 | bellard | case -2: |
1669 | 9a64fbe4 | bellard | /* Access rights violation */
|
1670 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1671 | 8f793433 | j_mayer | env->error_code = 0;
|
1672 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1673 | 8f793433 | j_mayer | if (rw == 1) |
1674 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x0A000000;
|
1675 | 8f793433 | j_mayer | else
|
1676 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x08000000;
|
1677 | 9a64fbe4 | bellard | break;
|
1678 | 9a64fbe4 | bellard | case -4: |
1679 | 9a64fbe4 | bellard | /* Direct store exception */
|
1680 | 9a64fbe4 | bellard | switch (access_type) {
|
1681 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
1682 | 9a64fbe4 | bellard | /* Floating point load/store */
|
1683 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ALIGN; |
1684 | 8f793433 | j_mayer | env->error_code = POWERPC_EXCP_ALIGN_FP; |
1685 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1686 | 9a64fbe4 | bellard | break;
|
1687 | 9a64fbe4 | bellard | case ACCESS_RES:
|
1688 | 8f793433 | j_mayer | /* lwarx, ldarx or stwcx. */
|
1689 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1690 | 8f793433 | j_mayer | env->error_code = 0;
|
1691 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1692 | 8f793433 | j_mayer | if (rw == 1) |
1693 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x06000000;
|
1694 | 8f793433 | j_mayer | else
|
1695 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x04000000;
|
1696 | 9a64fbe4 | bellard | break;
|
1697 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
1698 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
1699 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1700 | 8f793433 | j_mayer | env->error_code = 0;
|
1701 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1702 | 8f793433 | j_mayer | if (rw == 1) |
1703 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x06100000;
|
1704 | 8f793433 | j_mayer | else
|
1705 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x04100000;
|
1706 | 9a64fbe4 | bellard | break;
|
1707 | 9a64fbe4 | bellard | default:
|
1708 | 76a66253 | j_mayer | printf("DSI: invalid exception (%d)\n", ret);
|
1709 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_PROGRAM; |
1710 | 8f793433 | j_mayer | env->error_code = |
1711 | 8f793433 | j_mayer | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; |
1712 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1713 | 9a64fbe4 | bellard | break;
|
1714 | 9a64fbe4 | bellard | } |
1715 | fdabc366 | bellard | break;
|
1716 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
1717 | 2be0071f | bellard | case -5: |
1718 | 2be0071f | bellard | /* No match in segment table */
|
1719 | add78955 | j_mayer | if (env->mmu_model == POWERPC_MMU_620) {
|
1720 | add78955 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1721 | add78955 | j_mayer | env->error_code = 0;
|
1722 | add78955 | j_mayer | env->spr[SPR_DAR] = address; |
1723 | add78955 | j_mayer | /* XXX: this might be incorrect */
|
1724 | add78955 | j_mayer | if (rw == 1) |
1725 | add78955 | j_mayer | env->spr[SPR_DSISR] = 0x42000000;
|
1726 | add78955 | j_mayer | else
|
1727 | add78955 | j_mayer | env->spr[SPR_DSISR] = 0x40000000;
|
1728 | add78955 | j_mayer | } else {
|
1729 | add78955 | j_mayer | env->exception_index = POWERPC_EXCP_DSEG; |
1730 | add78955 | j_mayer | env->error_code = 0;
|
1731 | add78955 | j_mayer | env->spr[SPR_DAR] = address; |
1732 | add78955 | j_mayer | } |
1733 | 2be0071f | bellard | break;
|
1734 | e1833e1f | j_mayer | #endif
|
1735 | 9a64fbe4 | bellard | } |
1736 | 9a64fbe4 | bellard | } |
1737 | 9a64fbe4 | bellard | #if 0
|
1738 | 8f793433 | j_mayer | printf("%s: set exception to %d %02x\n", __func__,
|
1739 | 8f793433 | j_mayer | env->exception, env->error_code);
|
1740 | 9a64fbe4 | bellard | #endif
|
1741 | 9a64fbe4 | bellard | ret = 1;
|
1742 | 9a64fbe4 | bellard | } |
1743 | 76a66253 | j_mayer | |
1744 | 9a64fbe4 | bellard | return ret;
|
1745 | 9a64fbe4 | bellard | } |
1746 | 9a64fbe4 | bellard | |
1747 | 3fc6c082 | bellard | /*****************************************************************************/
|
1748 | 3fc6c082 | bellard | /* BATs management */
|
1749 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1750 | b068d6a7 | j_mayer | static always_inline void do_invalidate_BAT (CPUPPCState *env, |
1751 | b068d6a7 | j_mayer | target_ulong BATu, |
1752 | b068d6a7 | j_mayer | target_ulong mask) |
1753 | 3fc6c082 | bellard | { |
1754 | 3fc6c082 | bellard | target_ulong base, end, page; |
1755 | 76a66253 | j_mayer | |
1756 | 3fc6c082 | bellard | base = BATu & ~0x0001FFFF;
|
1757 | 3fc6c082 | bellard | end = base + mask + 0x00020000;
|
1758 | 3fc6c082 | bellard | #if defined (DEBUG_BATS)
|
1759 | 76a66253 | j_mayer | if (loglevel != 0) { |
1760 | 1b9eb036 | j_mayer | fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n", |
1761 | 76a66253 | j_mayer | base, end, mask); |
1762 | 76a66253 | j_mayer | } |
1763 | 3fc6c082 | bellard | #endif
|
1764 | 3fc6c082 | bellard | for (page = base; page != end; page += TARGET_PAGE_SIZE)
|
1765 | 3fc6c082 | bellard | tlb_flush_page(env, page); |
1766 | 3fc6c082 | bellard | #if defined (DEBUG_BATS)
|
1767 | 3fc6c082 | bellard | if (loglevel != 0) |
1768 | 3fc6c082 | bellard | fprintf(logfile, "Flush done\n");
|
1769 | 3fc6c082 | bellard | #endif
|
1770 | 3fc6c082 | bellard | } |
1771 | 3fc6c082 | bellard | #endif
|
1772 | 3fc6c082 | bellard | |
1773 | b068d6a7 | j_mayer | static always_inline void dump_store_bat (CPUPPCState *env, char ID, |
1774 | b068d6a7 | j_mayer | int ul, int nr, target_ulong value) |
1775 | 3fc6c082 | bellard | { |
1776 | 3fc6c082 | bellard | #if defined (DEBUG_BATS)
|
1777 | 3fc6c082 | bellard | if (loglevel != 0) { |
1778 | 6b542af7 | j_mayer | fprintf(logfile, "Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n", |
1779 | 1b9eb036 | j_mayer | ID, nr, ul == 0 ? 'u' : 'l', value, env->nip); |
1780 | 3fc6c082 | bellard | } |
1781 | 3fc6c082 | bellard | #endif
|
1782 | 3fc6c082 | bellard | } |
1783 | 3fc6c082 | bellard | |
1784 | 3fc6c082 | bellard | target_ulong do_load_ibatu (CPUPPCState *env, int nr)
|
1785 | 3fc6c082 | bellard | { |
1786 | 3fc6c082 | bellard | return env->IBAT[0][nr]; |
1787 | 3fc6c082 | bellard | } |
1788 | 3fc6c082 | bellard | |
1789 | 3fc6c082 | bellard | target_ulong do_load_ibatl (CPUPPCState *env, int nr)
|
1790 | 3fc6c082 | bellard | { |
1791 | 3fc6c082 | bellard | return env->IBAT[1][nr]; |
1792 | 3fc6c082 | bellard | } |
1793 | 3fc6c082 | bellard | |
1794 | 3fc6c082 | bellard | void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value) |
1795 | 3fc6c082 | bellard | { |
1796 | 3fc6c082 | bellard | target_ulong mask; |
1797 | 3fc6c082 | bellard | |
1798 | 3fc6c082 | bellard | dump_store_bat(env, 'I', 0, nr, value); |
1799 | 3fc6c082 | bellard | if (env->IBAT[0][nr] != value) { |
1800 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1801 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1802 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1803 | 3fc6c082 | bellard | #endif
|
1804 | 3fc6c082 | bellard | /* When storing valid upper BAT, mask BEPI and BRPN
|
1805 | 3fc6c082 | bellard | * and invalidate all TLBs covered by this BAT
|
1806 | 3fc6c082 | bellard | */
|
1807 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1808 | 3fc6c082 | bellard | env->IBAT[0][nr] = (value & 0x00001FFFUL) | |
1809 | 3fc6c082 | bellard | (value & ~0x0001FFFFUL & ~mask);
|
1810 | 3fc6c082 | bellard | env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) | |
1811 | 3fc6c082 | bellard | (env->IBAT[1][nr] & ~0x0001FFFF & ~mask); |
1812 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1813 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1814 | 76a66253 | j_mayer | #else
|
1815 | 3fc6c082 | bellard | tlb_flush(env, 1);
|
1816 | 3fc6c082 | bellard | #endif
|
1817 | 3fc6c082 | bellard | } |
1818 | 3fc6c082 | bellard | } |
1819 | 3fc6c082 | bellard | |
1820 | 3fc6c082 | bellard | void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value) |
1821 | 3fc6c082 | bellard | { |
1822 | 3fc6c082 | bellard | dump_store_bat(env, 'I', 1, nr, value); |
1823 | 3fc6c082 | bellard | env->IBAT[1][nr] = value;
|
1824 | 3fc6c082 | bellard | } |
1825 | 3fc6c082 | bellard | |
1826 | 3fc6c082 | bellard | target_ulong do_load_dbatu (CPUPPCState *env, int nr)
|
1827 | 3fc6c082 | bellard | { |
1828 | 3fc6c082 | bellard | return env->DBAT[0][nr]; |
1829 | 3fc6c082 | bellard | } |
1830 | 3fc6c082 | bellard | |
1831 | 3fc6c082 | bellard | target_ulong do_load_dbatl (CPUPPCState *env, int nr)
|
1832 | 3fc6c082 | bellard | { |
1833 | 3fc6c082 | bellard | return env->DBAT[1][nr]; |
1834 | 3fc6c082 | bellard | } |
1835 | 3fc6c082 | bellard | |
1836 | 3fc6c082 | bellard | void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value) |
1837 | 3fc6c082 | bellard | { |
1838 | 3fc6c082 | bellard | target_ulong mask; |
1839 | 3fc6c082 | bellard | |
1840 | 3fc6c082 | bellard | dump_store_bat(env, 'D', 0, nr, value); |
1841 | 3fc6c082 | bellard | if (env->DBAT[0][nr] != value) { |
1842 | 3fc6c082 | bellard | /* When storing valid upper BAT, mask BEPI and BRPN
|
1843 | 3fc6c082 | bellard | * and invalidate all TLBs covered by this BAT
|
1844 | 3fc6c082 | bellard | */
|
1845 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1846 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1847 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
1848 | 3fc6c082 | bellard | #endif
|
1849 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1850 | 3fc6c082 | bellard | env->DBAT[0][nr] = (value & 0x00001FFFUL) | |
1851 | 3fc6c082 | bellard | (value & ~0x0001FFFFUL & ~mask);
|
1852 | 3fc6c082 | bellard | env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) | |
1853 | 3fc6c082 | bellard | (env->DBAT[1][nr] & ~0x0001FFFF & ~mask); |
1854 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1855 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
1856 | 3fc6c082 | bellard | #else
|
1857 | 3fc6c082 | bellard | tlb_flush(env, 1);
|
1858 | 3fc6c082 | bellard | #endif
|
1859 | 3fc6c082 | bellard | } |
1860 | 3fc6c082 | bellard | } |
1861 | 3fc6c082 | bellard | |
1862 | 3fc6c082 | bellard | void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value) |
1863 | 3fc6c082 | bellard | { |
1864 | 3fc6c082 | bellard | dump_store_bat(env, 'D', 1, nr, value); |
1865 | 3fc6c082 | bellard | env->DBAT[1][nr] = value;
|
1866 | 3fc6c082 | bellard | } |
1867 | 3fc6c082 | bellard | |
1868 | 056401ea | j_mayer | void do_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value) |
1869 | 056401ea | j_mayer | { |
1870 | 056401ea | j_mayer | target_ulong mask; |
1871 | 056401ea | j_mayer | int do_inval;
|
1872 | 056401ea | j_mayer | |
1873 | 056401ea | j_mayer | dump_store_bat(env, 'I', 0, nr, value); |
1874 | 056401ea | j_mayer | if (env->IBAT[0][nr] != value) { |
1875 | 056401ea | j_mayer | do_inval = 0;
|
1876 | 056401ea | j_mayer | mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL; |
1877 | 056401ea | j_mayer | if (env->IBAT[1][nr] & 0x40) { |
1878 | 056401ea | j_mayer | /* Invalidate BAT only if it is valid */
|
1879 | 056401ea | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1880 | 056401ea | j_mayer | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1881 | 056401ea | j_mayer | #else
|
1882 | 056401ea | j_mayer | do_inval = 1;
|
1883 | 056401ea | j_mayer | #endif
|
1884 | 056401ea | j_mayer | } |
1885 | 056401ea | j_mayer | /* When storing valid upper BAT, mask BEPI and BRPN
|
1886 | 056401ea | j_mayer | * and invalidate all TLBs covered by this BAT
|
1887 | 056401ea | j_mayer | */
|
1888 | 056401ea | j_mayer | env->IBAT[0][nr] = (value & 0x00001FFFUL) | |
1889 | 056401ea | j_mayer | (value & ~0x0001FFFFUL & ~mask);
|
1890 | 056401ea | j_mayer | env->DBAT[0][nr] = env->IBAT[0][nr]; |
1891 | 056401ea | j_mayer | if (env->IBAT[1][nr] & 0x40) { |
1892 | 056401ea | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1893 | 056401ea | j_mayer | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1894 | 056401ea | j_mayer | #else
|
1895 | 056401ea | j_mayer | do_inval = 1;
|
1896 | 056401ea | j_mayer | #endif
|
1897 | 056401ea | j_mayer | } |
1898 | 056401ea | j_mayer | #if defined(FLUSH_ALL_TLBS)
|
1899 | 056401ea | j_mayer | if (do_inval)
|
1900 | 056401ea | j_mayer | tlb_flush(env, 1);
|
1901 | 056401ea | j_mayer | #endif
|
1902 | 056401ea | j_mayer | } |
1903 | 056401ea | j_mayer | } |
1904 | 056401ea | j_mayer | |
1905 | 056401ea | j_mayer | void do_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value) |
1906 | 056401ea | j_mayer | { |
1907 | 056401ea | j_mayer | target_ulong mask; |
1908 | 056401ea | j_mayer | int do_inval;
|
1909 | 056401ea | j_mayer | |
1910 | 056401ea | j_mayer | dump_store_bat(env, 'I', 1, nr, value); |
1911 | 056401ea | j_mayer | if (env->IBAT[1][nr] != value) { |
1912 | 056401ea | j_mayer | do_inval = 0;
|
1913 | 056401ea | j_mayer | if (env->IBAT[1][nr] & 0x40) { |
1914 | 056401ea | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1915 | 056401ea | j_mayer | mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL; |
1916 | 056401ea | j_mayer | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1917 | 056401ea | j_mayer | #else
|
1918 | 056401ea | j_mayer | do_inval = 1;
|
1919 | 056401ea | j_mayer | #endif
|
1920 | 056401ea | j_mayer | } |
1921 | 056401ea | j_mayer | if (value & 0x40) { |
1922 | 056401ea | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1923 | 056401ea | j_mayer | mask = (value << 17) & 0x0FFE0000UL; |
1924 | 056401ea | j_mayer | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1925 | 056401ea | j_mayer | #else
|
1926 | 056401ea | j_mayer | do_inval = 1;
|
1927 | 056401ea | j_mayer | #endif
|
1928 | 056401ea | j_mayer | } |
1929 | 056401ea | j_mayer | env->IBAT[1][nr] = value;
|
1930 | 056401ea | j_mayer | env->DBAT[1][nr] = value;
|
1931 | 056401ea | j_mayer | #if defined(FLUSH_ALL_TLBS)
|
1932 | 056401ea | j_mayer | if (do_inval)
|
1933 | 056401ea | j_mayer | tlb_flush(env, 1);
|
1934 | 056401ea | j_mayer | #endif
|
1935 | 056401ea | j_mayer | } |
1936 | 056401ea | j_mayer | } |
1937 | 056401ea | j_mayer | |
1938 | 0a032cbe | j_mayer | /*****************************************************************************/
|
1939 | 0a032cbe | j_mayer | /* TLB management */
|
1940 | 0a032cbe | j_mayer | void ppc_tlb_invalidate_all (CPUPPCState *env)
|
1941 | 0a032cbe | j_mayer | { |
1942 | daf4f96e | j_mayer | switch (env->mmu_model) {
|
1943 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1944 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1945 | 0a032cbe | j_mayer | ppc6xx_tlb_invalidate_all(env); |
1946 | daf4f96e | j_mayer | break;
|
1947 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1948 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1949 | 0a032cbe | j_mayer | ppc4xx_tlb_invalidate_all(env); |
1950 | daf4f96e | j_mayer | break;
|
1951 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1952 | 7dbe11ac | j_mayer | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
|
1953 | 7dbe11ac | j_mayer | break;
|
1954 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
1955 | b4095fed | j_mayer | /* XXX: TODO */
|
1956 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
1957 | b4095fed | j_mayer | break;
|
1958 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1959 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1960 | b4095fed | j_mayer | cpu_abort(env, "BookE MMU model is not implemented\n");
|
1961 | 7dbe11ac | j_mayer | break;
|
1962 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1963 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1964 | b4095fed | j_mayer | cpu_abort(env, "BookE MMU model is not implemented\n");
|
1965 | 7dbe11ac | j_mayer | break;
|
1966 | 7dbe11ac | j_mayer | case POWERPC_MMU_32B:
|
1967 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
1968 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
|
1969 | add78955 | j_mayer | case POWERPC_MMU_620:
|
1970 | 7dbe11ac | j_mayer | case POWERPC_MMU_64B:
|
1971 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
1972 | 0a032cbe | j_mayer | tlb_flush(env, 1);
|
1973 | daf4f96e | j_mayer | break;
|
1974 | 00af685f | j_mayer | default:
|
1975 | 00af685f | j_mayer | /* XXX: TODO */
|
1976 | 12de9a39 | j_mayer | cpu_abort(env, "Unknown MMU model\n");
|
1977 | 00af685f | j_mayer | break;
|
1978 | 0a032cbe | j_mayer | } |
1979 | 0a032cbe | j_mayer | } |
1980 | 0a032cbe | j_mayer | |
1981 | daf4f96e | j_mayer | void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
|
1982 | daf4f96e | j_mayer | { |
1983 | daf4f96e | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1984 | daf4f96e | j_mayer | addr &= TARGET_PAGE_MASK; |
1985 | daf4f96e | j_mayer | switch (env->mmu_model) {
|
1986 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1987 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1988 | daf4f96e | j_mayer | ppc6xx_tlb_invalidate_virt(env, addr, 0);
|
1989 | daf4f96e | j_mayer | if (env->id_tlbs == 1) |
1990 | daf4f96e | j_mayer | ppc6xx_tlb_invalidate_virt(env, addr, 1);
|
1991 | daf4f96e | j_mayer | break;
|
1992 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1993 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1994 | daf4f96e | j_mayer | ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]); |
1995 | daf4f96e | j_mayer | break;
|
1996 | b4095fed | j_mayer | case POWERPC_MMU_REAL:
|
1997 | 7dbe11ac | j_mayer | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
|
1998 | 7dbe11ac | j_mayer | break;
|
1999 | b4095fed | j_mayer | case POWERPC_MMU_MPC8xx:
|
2000 | b4095fed | j_mayer | /* XXX: TODO */
|
2001 | b4095fed | j_mayer | cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
2002 | b4095fed | j_mayer | break;
|
2003 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
2004 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
2005 | b4095fed | j_mayer | cpu_abort(env, "BookE MMU model is not implemented\n");
|
2006 | 7dbe11ac | j_mayer | break;
|
2007 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
2008 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
2009 | b4095fed | j_mayer | cpu_abort(env, "BookE FSL MMU model is not implemented\n");
|
2010 | 7dbe11ac | j_mayer | break;
|
2011 | 7dbe11ac | j_mayer | case POWERPC_MMU_32B:
|
2012 | faadf50e | j_mayer | case POWERPC_MMU_601:
|
2013 | daf4f96e | j_mayer | /* tlbie invalidate TLBs for all segments */
|
2014 | 6f2d8978 | j_mayer | addr &= ~((target_ulong)-1ULL << 28); |
2015 | daf4f96e | j_mayer | /* XXX: this case should be optimized,
|
2016 | daf4f96e | j_mayer | * giving a mask to tlb_flush_page
|
2017 | daf4f96e | j_mayer | */
|
2018 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x0 << 28)); |
2019 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x1 << 28)); |
2020 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x2 << 28)); |
2021 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x3 << 28)); |
2022 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x4 << 28)); |
2023 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x5 << 28)); |
2024 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x6 << 28)); |
2025 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x7 << 28)); |
2026 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x8 << 28)); |
2027 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x9 << 28)); |
2028 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xA << 28)); |
2029 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xB << 28)); |
2030 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xC << 28)); |
2031 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xD << 28)); |
2032 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xE << 28)); |
2033 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xF << 28)); |
2034 | 7dbe11ac | j_mayer | break;
|
2035 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
|
2036 | add78955 | j_mayer | case POWERPC_MMU_620:
|
2037 | 7dbe11ac | j_mayer | case POWERPC_MMU_64B:
|
2038 | 7dbe11ac | j_mayer | /* tlbie invalidate TLBs for all segments */
|
2039 | 7dbe11ac | j_mayer | /* XXX: given the fact that there are too many segments to invalidate,
|
2040 | 00af685f | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
|
2041 | 7dbe11ac | j_mayer | * we just invalidate all TLBs
|
2042 | 7dbe11ac | j_mayer | */
|
2043 | 7dbe11ac | j_mayer | tlb_flush(env, 1);
|
2044 | 7dbe11ac | j_mayer | break;
|
2045 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
2046 | 00af685f | j_mayer | default:
|
2047 | 00af685f | j_mayer | /* XXX: TODO */
|
2048 | 12de9a39 | j_mayer | cpu_abort(env, "Unknown MMU model\n");
|
2049 | 00af685f | j_mayer | break;
|
2050 | daf4f96e | j_mayer | } |
2051 | daf4f96e | j_mayer | #else
|
2052 | daf4f96e | j_mayer | ppc_tlb_invalidate_all(env); |
2053 | daf4f96e | j_mayer | #endif
|
2054 | daf4f96e | j_mayer | } |
2055 | daf4f96e | j_mayer | |
2056 | 3fc6c082 | bellard | /*****************************************************************************/
|
2057 | 3fc6c082 | bellard | /* Special registers manipulation */
|
2058 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2059 | d9bce9d9 | j_mayer | target_ulong ppc_load_asr (CPUPPCState *env) |
2060 | d9bce9d9 | j_mayer | { |
2061 | d9bce9d9 | j_mayer | return env->asr;
|
2062 | d9bce9d9 | j_mayer | } |
2063 | d9bce9d9 | j_mayer | |
2064 | d9bce9d9 | j_mayer | void ppc_store_asr (CPUPPCState *env, target_ulong value)
|
2065 | d9bce9d9 | j_mayer | { |
2066 | d9bce9d9 | j_mayer | if (env->asr != value) {
|
2067 | d9bce9d9 | j_mayer | env->asr = value; |
2068 | d9bce9d9 | j_mayer | tlb_flush(env, 1);
|
2069 | d9bce9d9 | j_mayer | } |
2070 | d9bce9d9 | j_mayer | } |
2071 | d9bce9d9 | j_mayer | #endif
|
2072 | d9bce9d9 | j_mayer | |
2073 | 3fc6c082 | bellard | target_ulong do_load_sdr1 (CPUPPCState *env) |
2074 | 3fc6c082 | bellard | { |
2075 | 3fc6c082 | bellard | return env->sdr1;
|
2076 | 3fc6c082 | bellard | } |
2077 | 3fc6c082 | bellard | |
2078 | 3fc6c082 | bellard | void do_store_sdr1 (CPUPPCState *env, target_ulong value)
|
2079 | 3fc6c082 | bellard | { |
2080 | 3fc6c082 | bellard | #if defined (DEBUG_MMU)
|
2081 | 3fc6c082 | bellard | if (loglevel != 0) { |
2082 | 6b542af7 | j_mayer | fprintf(logfile, "%s: " ADDRX "\n", __func__, value); |
2083 | 3fc6c082 | bellard | } |
2084 | 3fc6c082 | bellard | #endif
|
2085 | 3fc6c082 | bellard | if (env->sdr1 != value) {
|
2086 | 12de9a39 | j_mayer | /* XXX: for PowerPC 64, should check that the HTABSIZE value
|
2087 | 12de9a39 | j_mayer | * is <= 28
|
2088 | 12de9a39 | j_mayer | */
|
2089 | 3fc6c082 | bellard | env->sdr1 = value; |
2090 | 76a66253 | j_mayer | tlb_flush(env, 1);
|
2091 | 3fc6c082 | bellard | } |
2092 | 3fc6c082 | bellard | } |
2093 | 3fc6c082 | bellard | |
2094 | 12de9a39 | j_mayer | #if 0 // Unused
|
2095 | 3fc6c082 | bellard | target_ulong do_load_sr (CPUPPCState *env, int srnum)
|
2096 | 3fc6c082 | bellard | {
|
2097 | 3fc6c082 | bellard | return env->sr[srnum];
|
2098 | 3fc6c082 | bellard | }
|
2099 | 12de9a39 | j_mayer | #endif
|
2100 | 3fc6c082 | bellard | |
2101 | 3fc6c082 | bellard | void do_store_sr (CPUPPCState *env, int srnum, target_ulong value) |
2102 | 3fc6c082 | bellard | { |
2103 | 3fc6c082 | bellard | #if defined (DEBUG_MMU)
|
2104 | 3fc6c082 | bellard | if (loglevel != 0) { |
2105 | 6b542af7 | j_mayer | fprintf(logfile, "%s: reg=%d " ADDRX " " ADDRX "\n", |
2106 | 1b9eb036 | j_mayer | __func__, srnum, value, env->sr[srnum]); |
2107 | 3fc6c082 | bellard | } |
2108 | 3fc6c082 | bellard | #endif
|
2109 | 3fc6c082 | bellard | if (env->sr[srnum] != value) {
|
2110 | 3fc6c082 | bellard | env->sr[srnum] = value; |
2111 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS) && 0 |
2112 | 3fc6c082 | bellard | { |
2113 | 3fc6c082 | bellard | target_ulong page, end; |
2114 | 3fc6c082 | bellard | /* Invalidate 256 MB of virtual memory */
|
2115 | 3fc6c082 | bellard | page = (16 << 20) * srnum; |
2116 | 3fc6c082 | bellard | end = page + (16 << 20); |
2117 | 3fc6c082 | bellard | for (; page != end; page += TARGET_PAGE_SIZE)
|
2118 | 3fc6c082 | bellard | tlb_flush_page(env, page); |
2119 | 3fc6c082 | bellard | } |
2120 | 3fc6c082 | bellard | #else
|
2121 | 76a66253 | j_mayer | tlb_flush(env, 1);
|
2122 | 3fc6c082 | bellard | #endif
|
2123 | 3fc6c082 | bellard | } |
2124 | 3fc6c082 | bellard | } |
2125 | 76a66253 | j_mayer | #endif /* !defined (CONFIG_USER_ONLY) */ |
2126 | 3fc6c082 | bellard | |
2127 | bfa1e5cf | j_mayer | target_ulong ppc_load_xer (CPUPPCState *env) |
2128 | 79aceca5 | bellard | { |
2129 | 0411a972 | j_mayer | return hreg_load_xer(env);
|
2130 | 79aceca5 | bellard | } |
2131 | 79aceca5 | bellard | |
2132 | bfa1e5cf | j_mayer | void ppc_store_xer (CPUPPCState *env, target_ulong value)
|
2133 | 79aceca5 | bellard | { |
2134 | 0411a972 | j_mayer | hreg_store_xer(env, value); |
2135 | 79aceca5 | bellard | } |
2136 | 79aceca5 | bellard | |
2137 | 76a66253 | j_mayer | /* GDBstub can read and write MSR... */
|
2138 | 0411a972 | j_mayer | void ppc_store_msr (CPUPPCState *env, target_ulong value)
|
2139 | 3fc6c082 | bellard | { |
2140 | a4f30719 | j_mayer | hreg_store_msr(env, value, 0);
|
2141 | 3fc6c082 | bellard | } |
2142 | 3fc6c082 | bellard | |
2143 | 3fc6c082 | bellard | /*****************************************************************************/
|
2144 | 3fc6c082 | bellard | /* Exception processing */
|
2145 | 18fba28c | bellard | #if defined (CONFIG_USER_ONLY)
|
2146 | 9a64fbe4 | bellard | void do_interrupt (CPUState *env)
|
2147 | 79aceca5 | bellard | { |
2148 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2149 | e1833e1f | j_mayer | env->error_code = 0;
|
2150 | 18fba28c | bellard | } |
2151 | 47103572 | j_mayer | |
2152 | e9df014c | j_mayer | void ppc_hw_interrupt (CPUState *env)
|
2153 | 47103572 | j_mayer | { |
2154 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2155 | e1833e1f | j_mayer | env->error_code = 0;
|
2156 | 47103572 | j_mayer | } |
2157 | 76a66253 | j_mayer | #else /* defined (CONFIG_USER_ONLY) */ |
2158 | a11b8151 | j_mayer | static always_inline void dump_syscall (CPUState *env) |
2159 | d094807b | bellard | { |
2160 | 6b542af7 | j_mayer | fprintf(logfile, "syscall r0=" REGX " r3=" REGX " r4=" REGX |
2161 | 6b542af7 | j_mayer | " r5=" REGX " r6=" REGX " nip=" ADDRX "\n", |
2162 | 6b542af7 | j_mayer | ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4), |
2163 | 6b542af7 | j_mayer | ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6), env->nip); |
2164 | d094807b | bellard | } |
2165 | d094807b | bellard | |
2166 | e1833e1f | j_mayer | /* Note that this function should be greatly optimized
|
2167 | e1833e1f | j_mayer | * when called with a constant excp, from ppc_hw_interrupt
|
2168 | e1833e1f | j_mayer | */
|
2169 | e1833e1f | j_mayer | static always_inline void powerpc_excp (CPUState *env, |
2170 | e1833e1f | j_mayer | int excp_model, int excp) |
2171 | 18fba28c | bellard | { |
2172 | 0411a972 | j_mayer | target_ulong msr, new_msr, vector; |
2173 | e1833e1f | j_mayer | int srr0, srr1, asrr0, asrr1;
|
2174 | a4f30719 | j_mayer | int lpes0, lpes1, lev;
|
2175 | 79aceca5 | bellard | |
2176 | b172c56a | j_mayer | if (0) { |
2177 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2178 | b172c56a | j_mayer | lpes0 = (env->spr[SPR_LPCR] >> 1) & 1; |
2179 | b172c56a | j_mayer | lpes1 = (env->spr[SPR_LPCR] >> 2) & 1; |
2180 | b172c56a | j_mayer | } else {
|
2181 | b172c56a | j_mayer | /* Those values ensure we won't enter the hypervisor mode */
|
2182 | b172c56a | j_mayer | lpes0 = 0;
|
2183 | b172c56a | j_mayer | lpes1 = 1;
|
2184 | b172c56a | j_mayer | } |
2185 | b172c56a | j_mayer | |
2186 | b769d8fe | bellard | if (loglevel & CPU_LOG_INT) {
|
2187 | 6b542af7 | j_mayer | fprintf(logfile, "Raise exception at " ADDRX " => %08x (%02x)\n", |
2188 | 1b9eb036 | j_mayer | env->nip, excp, env->error_code); |
2189 | b769d8fe | bellard | } |
2190 | 0411a972 | j_mayer | msr = env->msr; |
2191 | 0411a972 | j_mayer | new_msr = msr; |
2192 | e1833e1f | j_mayer | srr0 = SPR_SRR0; |
2193 | e1833e1f | j_mayer | srr1 = SPR_SRR1; |
2194 | e1833e1f | j_mayer | asrr0 = -1;
|
2195 | e1833e1f | j_mayer | asrr1 = -1;
|
2196 | e1833e1f | j_mayer | msr &= ~((target_ulong)0x783F0000);
|
2197 | 9a64fbe4 | bellard | switch (excp) {
|
2198 | e1833e1f | j_mayer | case POWERPC_EXCP_NONE:
|
2199 | e1833e1f | j_mayer | /* Should never happen */
|
2200 | e1833e1f | j_mayer | return;
|
2201 | e1833e1f | j_mayer | case POWERPC_EXCP_CRITICAL: /* Critical input */ |
2202 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2203 | e1833e1f | j_mayer | switch (excp_model) {
|
2204 | a750fc0b | j_mayer | case POWERPC_EXCP_40x:
|
2205 | e1833e1f | j_mayer | srr0 = SPR_40x_SRR2; |
2206 | e1833e1f | j_mayer | srr1 = SPR_40x_SRR3; |
2207 | c62db105 | j_mayer | break;
|
2208 | a750fc0b | j_mayer | case POWERPC_EXCP_BOOKE:
|
2209 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2210 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2211 | c62db105 | j_mayer | break;
|
2212 | e1833e1f | j_mayer | case POWERPC_EXCP_G2:
|
2213 | c62db105 | j_mayer | break;
|
2214 | e1833e1f | j_mayer | default:
|
2215 | e1833e1f | j_mayer | goto excp_invalid;
|
2216 | 2be0071f | bellard | } |
2217 | 9a64fbe4 | bellard | goto store_next;
|
2218 | e1833e1f | j_mayer | case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
2219 | e1833e1f | j_mayer | if (msr_me == 0) { |
2220 | e63ecc6f | j_mayer | /* Machine check exception is not enabled.
|
2221 | e63ecc6f | j_mayer | * Enter checkstop state.
|
2222 | e63ecc6f | j_mayer | */
|
2223 | e63ecc6f | j_mayer | if (loglevel != 0) { |
2224 | e63ecc6f | j_mayer | fprintf(logfile, "Machine check while not allowed. "
|
2225 | e63ecc6f | j_mayer | "Entering checkstop state\n");
|
2226 | e63ecc6f | j_mayer | } else {
|
2227 | e63ecc6f | j_mayer | fprintf(stderr, "Machine check while not allowed. "
|
2228 | e63ecc6f | j_mayer | "Entering checkstop state\n");
|
2229 | e63ecc6f | j_mayer | } |
2230 | e63ecc6f | j_mayer | env->halted = 1;
|
2231 | e63ecc6f | j_mayer | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
2232 | e1833e1f | j_mayer | } |
2233 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2234 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_ME);
|
2235 | b172c56a | j_mayer | if (0) { |
2236 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2237 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2238 | b172c56a | j_mayer | } |
2239 | e1833e1f | j_mayer | /* XXX: should also have something loaded in DAR / DSISR */
|
2240 | e1833e1f | j_mayer | switch (excp_model) {
|
2241 | a750fc0b | j_mayer | case POWERPC_EXCP_40x:
|
2242 | e1833e1f | j_mayer | srr0 = SPR_40x_SRR2; |
2243 | e1833e1f | j_mayer | srr1 = SPR_40x_SRR3; |
2244 | c62db105 | j_mayer | break;
|
2245 | a750fc0b | j_mayer | case POWERPC_EXCP_BOOKE:
|
2246 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_MCSRR0; |
2247 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_MCSRR1; |
2248 | e1833e1f | j_mayer | asrr0 = SPR_BOOKE_CSRR0; |
2249 | e1833e1f | j_mayer | asrr1 = SPR_BOOKE_CSRR1; |
2250 | c62db105 | j_mayer | break;
|
2251 | c62db105 | j_mayer | default:
|
2252 | c62db105 | j_mayer | break;
|
2253 | 2be0071f | bellard | } |
2254 | e1833e1f | j_mayer | goto store_next;
|
2255 | e1833e1f | j_mayer | case POWERPC_EXCP_DSI: /* Data storage exception */ |
2256 | a541f297 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
2257 | 4a057712 | j_mayer | if (loglevel != 0) { |
2258 | 6b542af7 | j_mayer | fprintf(logfile, "DSI exception: DSISR=" ADDRX" DAR=" ADDRX "\n", |
2259 | 6b542af7 | j_mayer | env->spr[SPR_DSISR], env->spr[SPR_DAR]); |
2260 | 76a66253 | j_mayer | } |
2261 | a541f297 | bellard | #endif
|
2262 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2263 | e1833e1f | j_mayer | if (lpes1 == 0) |
2264 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2265 | a541f297 | bellard | goto store_next;
|
2266 | e1833e1f | j_mayer | case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
2267 | a541f297 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
2268 | 76a66253 | j_mayer | if (loglevel != 0) { |
2269 | 6b542af7 | j_mayer | fprintf(logfile, "ISI exception: msr=" ADDRX ", nip=" ADDRX "\n", |
2270 | 6b542af7 | j_mayer | msr, env->nip); |
2271 | 76a66253 | j_mayer | } |
2272 | a541f297 | bellard | #endif
|
2273 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2274 | e1833e1f | j_mayer | if (lpes1 == 0) |
2275 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2276 | e1833e1f | j_mayer | msr |= env->error_code; |
2277 | 9a64fbe4 | bellard | goto store_next;
|
2278 | e1833e1f | j_mayer | case POWERPC_EXCP_EXTERNAL: /* External input */ |
2279 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2280 | e1833e1f | j_mayer | if (lpes0 == 1) |
2281 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2282 | 9a64fbe4 | bellard | goto store_next;
|
2283 | e1833e1f | j_mayer | case POWERPC_EXCP_ALIGN: /* Alignment exception */ |
2284 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2285 | e1833e1f | j_mayer | if (lpes1 == 0) |
2286 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2287 | e1833e1f | j_mayer | /* XXX: this is false */
|
2288 | e1833e1f | j_mayer | /* Get rS/rD and rA from faulting opcode */
|
2289 | e1833e1f | j_mayer | env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; |
2290 | 9a64fbe4 | bellard | goto store_current;
|
2291 | e1833e1f | j_mayer | case POWERPC_EXCP_PROGRAM: /* Program exception */ |
2292 | 9a64fbe4 | bellard | switch (env->error_code & ~0xF) { |
2293 | e1833e1f | j_mayer | case POWERPC_EXCP_FP:
|
2294 | e1833e1f | j_mayer | if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { |
2295 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
2296 | 4a057712 | j_mayer | if (loglevel != 0) { |
2297 | a496775f | j_mayer | fprintf(logfile, "Ignore floating point exception\n");
|
2298 | a496775f | j_mayer | } |
2299 | 9a64fbe4 | bellard | #endif
|
2300 | 7c58044c | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2301 | 7c58044c | j_mayer | env->error_code = 0;
|
2302 | 9a64fbe4 | bellard | return;
|
2303 | 76a66253 | j_mayer | } |
2304 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2305 | e1833e1f | j_mayer | if (lpes1 == 0) |
2306 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2307 | 9a64fbe4 | bellard | msr |= 0x00100000;
|
2308 | 5b52b991 | j_mayer | if (msr_fe0 == msr_fe1)
|
2309 | 5b52b991 | j_mayer | goto store_next;
|
2310 | 5b52b991 | j_mayer | msr |= 0x00010000;
|
2311 | 76a66253 | j_mayer | break;
|
2312 | e1833e1f | j_mayer | case POWERPC_EXCP_INVAL:
|
2313 | a496775f | j_mayer | #if defined (DEBUG_EXCEPTIONS)
|
2314 | 4a057712 | j_mayer | if (loglevel != 0) { |
2315 | 6b542af7 | j_mayer | fprintf(logfile, "Invalid instruction at " ADDRX "\n", |
2316 | a496775f | j_mayer | env->nip); |
2317 | a496775f | j_mayer | } |
2318 | a496775f | j_mayer | #endif
|
2319 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2320 | e1833e1f | j_mayer | if (lpes1 == 0) |
2321 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2322 | 9a64fbe4 | bellard | msr |= 0x00080000;
|
2323 | 76a66253 | j_mayer | break;
|
2324 | e1833e1f | j_mayer | case POWERPC_EXCP_PRIV:
|
2325 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2326 | e1833e1f | j_mayer | if (lpes1 == 0) |
2327 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2328 | 9a64fbe4 | bellard | msr |= 0x00040000;
|
2329 | 76a66253 | j_mayer | break;
|
2330 | e1833e1f | j_mayer | case POWERPC_EXCP_TRAP:
|
2331 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2332 | e1833e1f | j_mayer | if (lpes1 == 0) |
2333 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2334 | 9a64fbe4 | bellard | msr |= 0x00020000;
|
2335 | 9a64fbe4 | bellard | break;
|
2336 | 9a64fbe4 | bellard | default:
|
2337 | 9a64fbe4 | bellard | /* Should never occur */
|
2338 | e1833e1f | j_mayer | cpu_abort(env, "Invalid program exception %d. Aborting\n",
|
2339 | e1833e1f | j_mayer | env->error_code); |
2340 | 76a66253 | j_mayer | break;
|
2341 | 76a66253 | j_mayer | } |
2342 | 5b52b991 | j_mayer | goto store_current;
|
2343 | e1833e1f | j_mayer | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ |
2344 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2345 | e1833e1f | j_mayer | if (lpes1 == 0) |
2346 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2347 | e1833e1f | j_mayer | goto store_current;
|
2348 | e1833e1f | j_mayer | case POWERPC_EXCP_SYSCALL: /* System call exception */ |
2349 | d094807b | bellard | /* NOTE: this is a temporary hack to support graphics OSI
|
2350 | d094807b | bellard | calls from the MOL driver */
|
2351 | e1833e1f | j_mayer | /* XXX: To be removed */
|
2352 | d094807b | bellard | if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b && |
2353 | d094807b | bellard | env->osi_call) { |
2354 | 7c58044c | j_mayer | if (env->osi_call(env) != 0) { |
2355 | 7c58044c | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2356 | 7c58044c | j_mayer | env->error_code = 0;
|
2357 | d094807b | bellard | return;
|
2358 | 7c58044c | j_mayer | } |
2359 | d094807b | bellard | } |
2360 | b769d8fe | bellard | if (loglevel & CPU_LOG_INT) {
|
2361 | d094807b | bellard | dump_syscall(env); |
2362 | b769d8fe | bellard | } |
2363 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2364 | f9fdea6b | j_mayer | lev = env->error_code; |
2365 | e1833e1f | j_mayer | if (lev == 1 || (lpes0 == 0 && lpes1 == 0)) |
2366 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2367 | e1833e1f | j_mayer | goto store_next;
|
2368 | e1833e1f | j_mayer | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ |
2369 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2370 | e1833e1f | j_mayer | goto store_current;
|
2371 | e1833e1f | j_mayer | case POWERPC_EXCP_DECR: /* Decrementer exception */ |
2372 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2373 | e1833e1f | j_mayer | if (lpes1 == 0) |
2374 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2375 | e1833e1f | j_mayer | goto store_next;
|
2376 | e1833e1f | j_mayer | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ |
2377 | e1833e1f | j_mayer | /* FIT on 4xx */
|
2378 | e1833e1f | j_mayer | #if defined (DEBUG_EXCEPTIONS)
|
2379 | e1833e1f | j_mayer | if (loglevel != 0) |
2380 | e1833e1f | j_mayer | fprintf(logfile, "FIT exception\n");
|
2381 | e1833e1f | j_mayer | #endif
|
2382 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2383 | 9a64fbe4 | bellard | goto store_next;
|
2384 | e1833e1f | j_mayer | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ |
2385 | e1833e1f | j_mayer | #if defined (DEBUG_EXCEPTIONS)
|
2386 | e1833e1f | j_mayer | if (loglevel != 0) |
2387 | e1833e1f | j_mayer | fprintf(logfile, "WDT exception\n");
|
2388 | e1833e1f | j_mayer | #endif
|
2389 | e1833e1f | j_mayer | switch (excp_model) {
|
2390 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2391 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2392 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2393 | e1833e1f | j_mayer | break;
|
2394 | e1833e1f | j_mayer | default:
|
2395 | e1833e1f | j_mayer | break;
|
2396 | e1833e1f | j_mayer | } |
2397 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2398 | 2be0071f | bellard | goto store_next;
|
2399 | e1833e1f | j_mayer | case POWERPC_EXCP_DTLB: /* Data TLB error */ |
2400 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2401 | e1833e1f | j_mayer | goto store_next;
|
2402 | e1833e1f | j_mayer | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ |
2403 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2404 | e1833e1f | j_mayer | goto store_next;
|
2405 | e1833e1f | j_mayer | case POWERPC_EXCP_DEBUG: /* Debug interrupt */ |
2406 | e1833e1f | j_mayer | switch (excp_model) {
|
2407 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2408 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_DSRR0; |
2409 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_DSRR1; |
2410 | e1833e1f | j_mayer | asrr0 = SPR_BOOKE_CSRR0; |
2411 | e1833e1f | j_mayer | asrr1 = SPR_BOOKE_CSRR1; |
2412 | e1833e1f | j_mayer | break;
|
2413 | e1833e1f | j_mayer | default:
|
2414 | e1833e1f | j_mayer | break;
|
2415 | e1833e1f | j_mayer | } |
2416 | 2be0071f | bellard | /* XXX: TODO */
|
2417 | e1833e1f | j_mayer | cpu_abort(env, "Debug exception is not implemented yet !\n");
|
2418 | 2be0071f | bellard | goto store_next;
|
2419 | e1833e1f | j_mayer | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ |
2420 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2421 | e1833e1f | j_mayer | goto store_current;
|
2422 | e1833e1f | j_mayer | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ |
2423 | 2be0071f | bellard | /* XXX: TODO */
|
2424 | e1833e1f | j_mayer | cpu_abort(env, "Embedded floating point data exception "
|
2425 | 2be0071f | bellard | "is not implemented yet !\n");
|
2426 | 2be0071f | bellard | goto store_next;
|
2427 | e1833e1f | j_mayer | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ |
2428 | 2be0071f | bellard | /* XXX: TODO */
|
2429 | e1833e1f | j_mayer | cpu_abort(env, "Embedded floating point round exception "
|
2430 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2431 | 9a64fbe4 | bellard | goto store_next;
|
2432 | e1833e1f | j_mayer | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ |
2433 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2434 | 2be0071f | bellard | /* XXX: TODO */
|
2435 | 2be0071f | bellard | cpu_abort(env, |
2436 | e1833e1f | j_mayer | "Performance counter exception is not implemented yet !\n");
|
2437 | 9a64fbe4 | bellard | goto store_next;
|
2438 | e1833e1f | j_mayer | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ |
2439 | 76a66253 | j_mayer | /* XXX: TODO */
|
2440 | e1833e1f | j_mayer | cpu_abort(env, |
2441 | e1833e1f | j_mayer | "Embedded doorbell interrupt is not implemented yet !\n");
|
2442 | 2be0071f | bellard | goto store_next;
|
2443 | e1833e1f | j_mayer | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ |
2444 | e1833e1f | j_mayer | switch (excp_model) {
|
2445 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2446 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2447 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2448 | a750fc0b | j_mayer | break;
|
2449 | 2be0071f | bellard | default:
|
2450 | 2be0071f | bellard | break;
|
2451 | 2be0071f | bellard | } |
2452 | e1833e1f | j_mayer | /* XXX: TODO */
|
2453 | e1833e1f | j_mayer | cpu_abort(env, "Embedded doorbell critical interrupt "
|
2454 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2455 | e1833e1f | j_mayer | goto store_next;
|
2456 | e1833e1f | j_mayer | case POWERPC_EXCP_RESET: /* System reset exception */ |
2457 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2458 | a4f30719 | j_mayer | if (0) { |
2459 | a4f30719 | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2460 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2461 | a4f30719 | j_mayer | } |
2462 | e1833e1f | j_mayer | goto store_next;
|
2463 | e1833e1f | j_mayer | case POWERPC_EXCP_DSEG: /* Data segment exception */ |
2464 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2465 | e1833e1f | j_mayer | if (lpes1 == 0) |
2466 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2467 | e1833e1f | j_mayer | goto store_next;
|
2468 | e1833e1f | j_mayer | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ |
2469 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2470 | e1833e1f | j_mayer | if (lpes1 == 0) |
2471 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2472 | e1833e1f | j_mayer | goto store_next;
|
2473 | e1833e1f | j_mayer | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ |
2474 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2475 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2476 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2477 | b172c56a | j_mayer | goto store_next;
|
2478 | e1833e1f | j_mayer | case POWERPC_EXCP_TRACE: /* Trace exception */ |
2479 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2480 | e1833e1f | j_mayer | if (lpes1 == 0) |
2481 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2482 | e1833e1f | j_mayer | goto store_next;
|
2483 | e1833e1f | j_mayer | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
2484 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2485 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2486 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2487 | e1833e1f | j_mayer | goto store_next;
|
2488 | e1833e1f | j_mayer | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ |
2489 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2490 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2491 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2492 | e1833e1f | j_mayer | goto store_next;
|
2493 | e1833e1f | j_mayer | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ |
2494 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2495 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2496 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2497 | e1833e1f | j_mayer | goto store_next;
|
2498 | e1833e1f | j_mayer | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ |
2499 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2500 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2501 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2502 | e1833e1f | j_mayer | goto store_next;
|
2503 | e1833e1f | j_mayer | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ |
2504 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2505 | e1833e1f | j_mayer | if (lpes1 == 0) |
2506 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2507 | e1833e1f | j_mayer | goto store_current;
|
2508 | e1833e1f | j_mayer | case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ |
2509 | a496775f | j_mayer | #if defined (DEBUG_EXCEPTIONS)
|
2510 | e1833e1f | j_mayer | if (loglevel != 0) |
2511 | e1833e1f | j_mayer | fprintf(logfile, "PIT exception\n");
|
2512 | e1833e1f | j_mayer | #endif
|
2513 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2514 | e1833e1f | j_mayer | goto store_next;
|
2515 | e1833e1f | j_mayer | case POWERPC_EXCP_IO: /* IO error exception */ |
2516 | e1833e1f | j_mayer | /* XXX: TODO */
|
2517 | e1833e1f | j_mayer | cpu_abort(env, "601 IO error exception is not implemented yet !\n");
|
2518 | e1833e1f | j_mayer | goto store_next;
|
2519 | e1833e1f | j_mayer | case POWERPC_EXCP_RUNM: /* Run mode exception */ |
2520 | e1833e1f | j_mayer | /* XXX: TODO */
|
2521 | e1833e1f | j_mayer | cpu_abort(env, "601 run mode exception is not implemented yet !\n");
|
2522 | e1833e1f | j_mayer | goto store_next;
|
2523 | e1833e1f | j_mayer | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ |
2524 | e1833e1f | j_mayer | /* XXX: TODO */
|
2525 | e1833e1f | j_mayer | cpu_abort(env, "602 emulation trap exception "
|
2526 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2527 | e1833e1f | j_mayer | goto store_next;
|
2528 | e1833e1f | j_mayer | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ |
2529 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2530 | a4f30719 | j_mayer | if (lpes1 == 0) /* XXX: check this */ |
2531 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2532 | e1833e1f | j_mayer | switch (excp_model) {
|
2533 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2534 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2535 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2536 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2537 | e1833e1f | j_mayer | goto tlb_miss_tgpr;
|
2538 | a750fc0b | j_mayer | case POWERPC_EXCP_7x5:
|
2539 | 76a66253 | j_mayer | goto tlb_miss;
|
2540 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2541 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
2542 | 2be0071f | bellard | default:
|
2543 | e1833e1f | j_mayer | cpu_abort(env, "Invalid instruction TLB miss exception\n");
|
2544 | 2be0071f | bellard | break;
|
2545 | 2be0071f | bellard | } |
2546 | e1833e1f | j_mayer | break;
|
2547 | e1833e1f | j_mayer | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ |
2548 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2549 | a4f30719 | j_mayer | if (lpes1 == 0) /* XXX: check this */ |
2550 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2551 | e1833e1f | j_mayer | switch (excp_model) {
|
2552 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2553 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2554 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2555 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2556 | e1833e1f | j_mayer | goto tlb_miss_tgpr;
|
2557 | a750fc0b | j_mayer | case POWERPC_EXCP_7x5:
|
2558 | 76a66253 | j_mayer | goto tlb_miss;
|
2559 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2560 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
2561 | 2be0071f | bellard | default:
|
2562 | e1833e1f | j_mayer | cpu_abort(env, "Invalid data load TLB miss exception\n");
|
2563 | 2be0071f | bellard | break;
|
2564 | 2be0071f | bellard | } |
2565 | e1833e1f | j_mayer | break;
|
2566 | e1833e1f | j_mayer | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ |
2567 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2568 | a4f30719 | j_mayer | if (lpes1 == 0) /* XXX: check this */ |
2569 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2570 | e1833e1f | j_mayer | switch (excp_model) {
|
2571 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2572 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2573 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2574 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2575 | e1833e1f | j_mayer | tlb_miss_tgpr:
|
2576 | 76a66253 | j_mayer | /* Swap temporary saved registers with GPRs */
|
2577 | 0411a972 | j_mayer | if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { |
2578 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_TGPR;
|
2579 | 0411a972 | j_mayer | hreg_swap_gpr_tgpr(env); |
2580 | 0411a972 | j_mayer | } |
2581 | e1833e1f | j_mayer | goto tlb_miss;
|
2582 | e1833e1f | j_mayer | case POWERPC_EXCP_7x5:
|
2583 | e1833e1f | j_mayer | tlb_miss:
|
2584 | 2be0071f | bellard | #if defined (DEBUG_SOFTWARE_TLB)
|
2585 | 2be0071f | bellard | if (loglevel != 0) { |
2586 | 76a66253 | j_mayer | const unsigned char *es; |
2587 | 76a66253 | j_mayer | target_ulong *miss, *cmp; |
2588 | 76a66253 | j_mayer | int en;
|
2589 | 1e6784f9 | j_mayer | if (excp == POWERPC_EXCP_IFTLB) {
|
2590 | 76a66253 | j_mayer | es = "I";
|
2591 | 76a66253 | j_mayer | en = 'I';
|
2592 | 76a66253 | j_mayer | miss = &env->spr[SPR_IMISS]; |
2593 | 76a66253 | j_mayer | cmp = &env->spr[SPR_ICMP]; |
2594 | 76a66253 | j_mayer | } else {
|
2595 | 1e6784f9 | j_mayer | if (excp == POWERPC_EXCP_DLTLB)
|
2596 | 76a66253 | j_mayer | es = "DL";
|
2597 | 76a66253 | j_mayer | else
|
2598 | 76a66253 | j_mayer | es = "DS";
|
2599 | 76a66253 | j_mayer | en = 'D';
|
2600 | 76a66253 | j_mayer | miss = &env->spr[SPR_DMISS]; |
2601 | 76a66253 | j_mayer | cmp = &env->spr[SPR_DCMP]; |
2602 | 76a66253 | j_mayer | } |
2603 | 1b9eb036 | j_mayer | fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
2604 | 4a057712 | j_mayer | " H1 " ADDRX " H2 " ADDRX " %08x\n", |
2605 | 1b9eb036 | j_mayer | es, en, *miss, en, *cmp, |
2606 | 76a66253 | j_mayer | env->spr[SPR_HASH1], env->spr[SPR_HASH2], |
2607 | 2be0071f | bellard | env->error_code); |
2608 | 2be0071f | bellard | } |
2609 | 9a64fbe4 | bellard | #endif
|
2610 | 2be0071f | bellard | msr |= env->crf[0] << 28; |
2611 | 2be0071f | bellard | msr |= env->error_code; /* key, D/I, S/L bits */
|
2612 | 2be0071f | bellard | /* Set way using a LRU mechanism */
|
2613 | 76a66253 | j_mayer | msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; |
2614 | c62db105 | j_mayer | break;
|
2615 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2616 | 7dbe11ac | j_mayer | tlb_miss_74xx:
|
2617 | 7dbe11ac | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
2618 | 7dbe11ac | j_mayer | if (loglevel != 0) { |
2619 | 7dbe11ac | j_mayer | const unsigned char *es; |
2620 | 7dbe11ac | j_mayer | target_ulong *miss, *cmp; |
2621 | 7dbe11ac | j_mayer | int en;
|
2622 | 7dbe11ac | j_mayer | if (excp == POWERPC_EXCP_IFTLB) {
|
2623 | 7dbe11ac | j_mayer | es = "I";
|
2624 | 7dbe11ac | j_mayer | en = 'I';
|
2625 | 0411a972 | j_mayer | miss = &env->spr[SPR_TLBMISS]; |
2626 | 0411a972 | j_mayer | cmp = &env->spr[SPR_PTEHI]; |
2627 | 7dbe11ac | j_mayer | } else {
|
2628 | 7dbe11ac | j_mayer | if (excp == POWERPC_EXCP_DLTLB)
|
2629 | 7dbe11ac | j_mayer | es = "DL";
|
2630 | 7dbe11ac | j_mayer | else
|
2631 | 7dbe11ac | j_mayer | es = "DS";
|
2632 | 7dbe11ac | j_mayer | en = 'D';
|
2633 | 7dbe11ac | j_mayer | miss = &env->spr[SPR_TLBMISS]; |
2634 | 7dbe11ac | j_mayer | cmp = &env->spr[SPR_PTEHI]; |
2635 | 7dbe11ac | j_mayer | } |
2636 | 7dbe11ac | j_mayer | fprintf(logfile, "74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
2637 | 7dbe11ac | j_mayer | " %08x\n",
|
2638 | 7dbe11ac | j_mayer | es, en, *miss, en, *cmp, env->error_code); |
2639 | 7dbe11ac | j_mayer | } |
2640 | 7dbe11ac | j_mayer | #endif
|
2641 | 7dbe11ac | j_mayer | msr |= env->error_code; /* key bit */
|
2642 | 7dbe11ac | j_mayer | break;
|
2643 | 2be0071f | bellard | default:
|
2644 | e1833e1f | j_mayer | cpu_abort(env, "Invalid data store TLB miss exception\n");
|
2645 | 2be0071f | bellard | break;
|
2646 | 2be0071f | bellard | } |
2647 | e1833e1f | j_mayer | goto store_next;
|
2648 | e1833e1f | j_mayer | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ |
2649 | e1833e1f | j_mayer | /* XXX: TODO */
|
2650 | e1833e1f | j_mayer | cpu_abort(env, "Floating point assist exception "
|
2651 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2652 | e1833e1f | j_mayer | goto store_next;
|
2653 | b4095fed | j_mayer | case POWERPC_EXCP_DABR: /* Data address breakpoint */ |
2654 | b4095fed | j_mayer | /* XXX: TODO */
|
2655 | b4095fed | j_mayer | cpu_abort(env, "DABR exception is not implemented yet !\n");
|
2656 | b4095fed | j_mayer | goto store_next;
|
2657 | e1833e1f | j_mayer | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ |
2658 | e1833e1f | j_mayer | /* XXX: TODO */
|
2659 | e1833e1f | j_mayer | cpu_abort(env, "IABR exception is not implemented yet !\n");
|
2660 | e1833e1f | j_mayer | goto store_next;
|
2661 | e1833e1f | j_mayer | case POWERPC_EXCP_SMI: /* System management interrupt */ |
2662 | e1833e1f | j_mayer | /* XXX: TODO */
|
2663 | e1833e1f | j_mayer | cpu_abort(env, "SMI exception is not implemented yet !\n");
|
2664 | e1833e1f | j_mayer | goto store_next;
|
2665 | e1833e1f | j_mayer | case POWERPC_EXCP_THERM: /* Thermal interrupt */ |
2666 | e1833e1f | j_mayer | /* XXX: TODO */
|
2667 | e1833e1f | j_mayer | cpu_abort(env, "Thermal management exception "
|
2668 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2669 | e1833e1f | j_mayer | goto store_next;
|
2670 | e1833e1f | j_mayer | case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ |
2671 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2672 | e1833e1f | j_mayer | if (lpes1 == 0) |
2673 | a4f30719 | j_mayer | new_msr |= (target_ulong)MSR_HVB; |
2674 | e1833e1f | j_mayer | /* XXX: TODO */
|
2675 | e1833e1f | j_mayer | cpu_abort(env, |
2676 | e1833e1f | j_mayer | "Performance counter exception is not implemented yet !\n");
|
2677 | e1833e1f | j_mayer | goto store_next;
|
2678 | e1833e1f | j_mayer | case POWERPC_EXCP_VPUA: /* Vector assist exception */ |
2679 | e1833e1f | j_mayer | /* XXX: TODO */
|
2680 | e1833e1f | j_mayer | cpu_abort(env, "VPU assist exception is not implemented yet !\n");
|
2681 | e1833e1f | j_mayer | goto store_next;
|
2682 | e1833e1f | j_mayer | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ |
2683 | e1833e1f | j_mayer | /* XXX: TODO */
|
2684 | e1833e1f | j_mayer | cpu_abort(env, |
2685 | e1833e1f | j_mayer | "970 soft-patch exception is not implemented yet !\n");
|
2686 | e1833e1f | j_mayer | goto store_next;
|
2687 | e1833e1f | j_mayer | case POWERPC_EXCP_MAINT: /* Maintenance exception */ |
2688 | e1833e1f | j_mayer | /* XXX: TODO */
|
2689 | e1833e1f | j_mayer | cpu_abort(env, |
2690 | e1833e1f | j_mayer | "970 maintenance exception is not implemented yet !\n");
|
2691 | e1833e1f | j_mayer | goto store_next;
|
2692 | b4095fed | j_mayer | case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ |
2693 | b4095fed | j_mayer | /* XXX: TODO */
|
2694 | b4095fed | j_mayer | cpu_abort(env, "Maskable external exception "
|
2695 | b4095fed | j_mayer | "is not implemented yet !\n");
|
2696 | b4095fed | j_mayer | goto store_next;
|
2697 | b4095fed | j_mayer | case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ |
2698 | b4095fed | j_mayer | /* XXX: TODO */
|
2699 | b4095fed | j_mayer | cpu_abort(env, "Non maskable external exception "
|
2700 | b4095fed | j_mayer | "is not implemented yet !\n");
|
2701 | b4095fed | j_mayer | goto store_next;
|
2702 | 2be0071f | bellard | default:
|
2703 | e1833e1f | j_mayer | excp_invalid:
|
2704 | e1833e1f | j_mayer | cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
|
2705 | e1833e1f | j_mayer | break;
|
2706 | 9a64fbe4 | bellard | store_current:
|
2707 | 2be0071f | bellard | /* save current instruction location */
|
2708 | e1833e1f | j_mayer | env->spr[srr0] = env->nip - 4;
|
2709 | 9a64fbe4 | bellard | break;
|
2710 | 9a64fbe4 | bellard | store_next:
|
2711 | 2be0071f | bellard | /* save next instruction location */
|
2712 | e1833e1f | j_mayer | env->spr[srr0] = env->nip; |
2713 | 9a64fbe4 | bellard | break;
|
2714 | 9a64fbe4 | bellard | } |
2715 | e1833e1f | j_mayer | /* Save MSR */
|
2716 | e1833e1f | j_mayer | env->spr[srr1] = msr; |
2717 | e1833e1f | j_mayer | /* If any alternate SRR register are defined, duplicate saved values */
|
2718 | e1833e1f | j_mayer | if (asrr0 != -1) |
2719 | e1833e1f | j_mayer | env->spr[asrr0] = env->spr[srr0]; |
2720 | e1833e1f | j_mayer | if (asrr1 != -1) |
2721 | e1833e1f | j_mayer | env->spr[asrr1] = env->spr[srr1]; |
2722 | 2be0071f | bellard | /* If we disactivated any translation, flush TLBs */
|
2723 | 0411a972 | j_mayer | if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR))) |
2724 | 2be0071f | bellard | tlb_flush(env, 1);
|
2725 | 9a64fbe4 | bellard | /* reload MSR with correct bits */
|
2726 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_EE);
|
2727 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_PR);
|
2728 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_FP);
|
2729 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_FE0);
|
2730 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_SE);
|
2731 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_BE);
|
2732 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_FE1);
|
2733 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_IR);
|
2734 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_DR);
|
2735 | e1833e1f | j_mayer | #if 0 /* Fix this: not on all targets */
|
2736 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_PMM);
|
2737 | e1833e1f | j_mayer | #endif
|
2738 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_LE);
|
2739 | 0411a972 | j_mayer | if (msr_ile)
|
2740 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_LE;
|
2741 | 0411a972 | j_mayer | else
|
2742 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_LE);
|
2743 | e1833e1f | j_mayer | /* Jump to handler */
|
2744 | e1833e1f | j_mayer | vector = env->excp_vectors[excp]; |
2745 | 6f2d8978 | j_mayer | if (vector == (target_ulong)-1ULL) { |
2746 | e1833e1f | j_mayer | cpu_abort(env, "Raised an exception without defined vector %d\n",
|
2747 | e1833e1f | j_mayer | excp); |
2748 | e1833e1f | j_mayer | } |
2749 | e1833e1f | j_mayer | vector |= env->excp_prefix; |
2750 | c62db105 | j_mayer | #if defined(TARGET_PPC64)
|
2751 | e1833e1f | j_mayer | if (excp_model == POWERPC_EXCP_BOOKE) {
|
2752 | 0411a972 | j_mayer | if (!msr_icm) {
|
2753 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_CM);
|
2754 | e1833e1f | j_mayer | vector = (uint32_t)vector; |
2755 | 0411a972 | j_mayer | } else {
|
2756 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_CM;
|
2757 | 0411a972 | j_mayer | } |
2758 | c62db105 | j_mayer | } else {
|
2759 | 0411a972 | j_mayer | if (!msr_isf) {
|
2760 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_SF);
|
2761 | e1833e1f | j_mayer | vector = (uint32_t)vector; |
2762 | 0411a972 | j_mayer | } else {
|
2763 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_SF;
|
2764 | 0411a972 | j_mayer | } |
2765 | c62db105 | j_mayer | } |
2766 | e1833e1f | j_mayer | #endif
|
2767 | 0411a972 | j_mayer | /* XXX: we don't use hreg_store_msr here as already have treated
|
2768 | 0411a972 | j_mayer | * any special case that could occur. Just store MSR and update hflags
|
2769 | 0411a972 | j_mayer | */
|
2770 | a4f30719 | j_mayer | env->msr = new_msr & env->msr_mask; |
2771 | 0411a972 | j_mayer | hreg_compute_hflags(env); |
2772 | e1833e1f | j_mayer | env->nip = vector; |
2773 | e1833e1f | j_mayer | /* Reset exception state */
|
2774 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2775 | e1833e1f | j_mayer | env->error_code = 0;
|
2776 | fb0eaffc | bellard | } |
2777 | 47103572 | j_mayer | |
2778 | e1833e1f | j_mayer | void do_interrupt (CPUState *env)
|
2779 | 47103572 | j_mayer | { |
2780 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, env->exception_index); |
2781 | e1833e1f | j_mayer | } |
2782 | 47103572 | j_mayer | |
2783 | e1833e1f | j_mayer | void ppc_hw_interrupt (CPUPPCState *env)
|
2784 | e1833e1f | j_mayer | { |
2785 | f9fdea6b | j_mayer | int hdice;
|
2786 | f9fdea6b | j_mayer | |
2787 | 0411a972 | j_mayer | #if 0
|
2788 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
|
2789 | a496775f | j_mayer | fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
|
2790 | a496775f | j_mayer | __func__, env, env->pending_interrupts,
|
2791 | 0411a972 | j_mayer | env->interrupt_request, (int)msr_me, (int)msr_ee);
|
2792 | a496775f | j_mayer | }
|
2793 | 47103572 | j_mayer | #endif
|
2794 | e1833e1f | j_mayer | /* External reset */
|
2795 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { |
2796 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
|
2797 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET); |
2798 | e1833e1f | j_mayer | return;
|
2799 | e1833e1f | j_mayer | } |
2800 | e1833e1f | j_mayer | /* Machine check exception */
|
2801 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { |
2802 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
|
2803 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK); |
2804 | e1833e1f | j_mayer | return;
|
2805 | 47103572 | j_mayer | } |
2806 | e1833e1f | j_mayer | #if 0 /* TODO */
|
2807 | e1833e1f | j_mayer | /* External debug exception */
|
2808 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
|
2809 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
|
2810 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
|
2811 | e1833e1f | j_mayer | return;
|
2812 | e1833e1f | j_mayer | }
|
2813 | e1833e1f | j_mayer | #endif
|
2814 | b172c56a | j_mayer | if (0) { |
2815 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2816 | b172c56a | j_mayer | hdice = env->spr[SPR_LPCR] & 1;
|
2817 | b172c56a | j_mayer | } else {
|
2818 | b172c56a | j_mayer | hdice = 0;
|
2819 | b172c56a | j_mayer | } |
2820 | f9fdea6b | j_mayer | if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) { |
2821 | 47103572 | j_mayer | /* Hypervisor decrementer exception */
|
2822 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { |
2823 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
|
2824 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR); |
2825 | e1833e1f | j_mayer | return;
|
2826 | e1833e1f | j_mayer | } |
2827 | e1833e1f | j_mayer | } |
2828 | e1833e1f | j_mayer | if (msr_ce != 0) { |
2829 | e1833e1f | j_mayer | /* External critical interrupt */
|
2830 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { |
2831 | e1833e1f | j_mayer | /* Taking a critical external interrupt does not clear the external
|
2832 | e1833e1f | j_mayer | * critical interrupt status
|
2833 | e1833e1f | j_mayer | */
|
2834 | e1833e1f | j_mayer | #if 0
|
2835 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
|
2836 | 47103572 | j_mayer | #endif
|
2837 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL); |
2838 | e1833e1f | j_mayer | return;
|
2839 | e1833e1f | j_mayer | } |
2840 | e1833e1f | j_mayer | } |
2841 | e1833e1f | j_mayer | if (msr_ee != 0) { |
2842 | e1833e1f | j_mayer | /* Watchdog timer on embedded PowerPC */
|
2843 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { |
2844 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
|
2845 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT); |
2846 | e1833e1f | j_mayer | return;
|
2847 | e1833e1f | j_mayer | } |
2848 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { |
2849 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
|
2850 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI); |
2851 | e1833e1f | j_mayer | return;
|
2852 | e1833e1f | j_mayer | } |
2853 | e1833e1f | j_mayer | /* Fixed interval timer on embedded PowerPC */
|
2854 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { |
2855 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
|
2856 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT); |
2857 | e1833e1f | j_mayer | return;
|
2858 | e1833e1f | j_mayer | } |
2859 | e1833e1f | j_mayer | /* Programmable interval timer on embedded PowerPC */
|
2860 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { |
2861 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
|
2862 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT); |
2863 | e1833e1f | j_mayer | return;
|
2864 | e1833e1f | j_mayer | } |
2865 | 47103572 | j_mayer | /* Decrementer exception */
|
2866 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { |
2867 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
|
2868 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR); |
2869 | e1833e1f | j_mayer | return;
|
2870 | e1833e1f | j_mayer | } |
2871 | 47103572 | j_mayer | /* External interrupt */
|
2872 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { |
2873 | e9df014c | j_mayer | /* Taking an external interrupt does not clear the external
|
2874 | e9df014c | j_mayer | * interrupt status
|
2875 | e9df014c | j_mayer | */
|
2876 | e9df014c | j_mayer | #if 0
|
2877 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
|
2878 | e9df014c | j_mayer | #endif
|
2879 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL); |
2880 | e1833e1f | j_mayer | return;
|
2881 | e1833e1f | j_mayer | } |
2882 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { |
2883 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
|
2884 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI); |
2885 | e1833e1f | j_mayer | return;
|
2886 | 47103572 | j_mayer | } |
2887 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { |
2888 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
|
2889 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM); |
2890 | e1833e1f | j_mayer | return;
|
2891 | e1833e1f | j_mayer | } |
2892 | e1833e1f | j_mayer | /* Thermal interrupt */
|
2893 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { |
2894 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
|
2895 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM); |
2896 | e1833e1f | j_mayer | return;
|
2897 | e1833e1f | j_mayer | } |
2898 | 47103572 | j_mayer | } |
2899 | 47103572 | j_mayer | } |
2900 | 18fba28c | bellard | #endif /* !CONFIG_USER_ONLY */ |
2901 | a496775f | j_mayer | |
2902 | a496775f | j_mayer | void cpu_dump_EA (target_ulong EA)
|
2903 | a496775f | j_mayer | { |
2904 | a496775f | j_mayer | FILE *f; |
2905 | a496775f | j_mayer | |
2906 | a496775f | j_mayer | if (logfile) {
|
2907 | a496775f | j_mayer | f = logfile; |
2908 | a496775f | j_mayer | } else {
|
2909 | a496775f | j_mayer | f = stdout; |
2910 | a496775f | j_mayer | return;
|
2911 | a496775f | j_mayer | } |
2912 | 4a057712 | j_mayer | fprintf(f, "Memory access at address " ADDRX "\n", EA); |
2913 | 4a057712 | j_mayer | } |
2914 | 4a057712 | j_mayer | |
2915 | 4a057712 | j_mayer | void cpu_dump_rfi (target_ulong RA, target_ulong msr)
|
2916 | 4a057712 | j_mayer | { |
2917 | 4a057712 | j_mayer | FILE *f; |
2918 | 4a057712 | j_mayer | |
2919 | 4a057712 | j_mayer | if (logfile) {
|
2920 | 4a057712 | j_mayer | f = logfile; |
2921 | 4a057712 | j_mayer | } else {
|
2922 | 4a057712 | j_mayer | f = stdout; |
2923 | 4a057712 | j_mayer | return;
|
2924 | 4a057712 | j_mayer | } |
2925 | 4a057712 | j_mayer | fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n", |
2926 | 4a057712 | j_mayer | RA, msr); |
2927 | a496775f | j_mayer | } |
2928 | a496775f | j_mayer | |
2929 | 0a032cbe | j_mayer | void cpu_ppc_reset (void *opaque) |
2930 | 0a032cbe | j_mayer | { |
2931 | 0a032cbe | j_mayer | CPUPPCState *env; |
2932 | 0411a972 | j_mayer | target_ulong msr; |
2933 | 0a032cbe | j_mayer | |
2934 | 0a032cbe | j_mayer | env = opaque; |
2935 | 0411a972 | j_mayer | msr = (target_ulong)0;
|
2936 | a4f30719 | j_mayer | if (0) { |
2937 | a4f30719 | j_mayer | /* XXX: find a suitable condition to enable the hypervisor mode */
|
2938 | a4f30719 | j_mayer | msr |= (target_ulong)MSR_HVB; |
2939 | a4f30719 | j_mayer | } |
2940 | 0411a972 | j_mayer | msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ |
2941 | 0411a972 | j_mayer | msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ |
2942 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_EP;
|
2943 | 0a032cbe | j_mayer | #if defined (DO_SINGLE_STEP) && 0 |
2944 | 0a032cbe | j_mayer | /* Single step trace mode */
|
2945 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_SE;
|
2946 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_BE;
|
2947 | 0a032cbe | j_mayer | #endif
|
2948 | 0a032cbe | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2949 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ |
2950 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_PR;
|
2951 | 0a032cbe | j_mayer | #else
|
2952 | 1c27f8fb | j_mayer | env->nip = env->hreset_vector | env->excp_prefix; |
2953 | b4095fed | j_mayer | if (env->mmu_model != POWERPC_MMU_REAL)
|
2954 | 141c8ae2 | j_mayer | ppc_tlb_invalidate_all(env); |
2955 | 0a032cbe | j_mayer | #endif
|
2956 | 0411a972 | j_mayer | env->msr = msr; |
2957 | 0411a972 | j_mayer | hreg_compute_hflags(env); |
2958 | 6f2d8978 | j_mayer | env->reserve = (target_ulong)-1ULL;
|
2959 | 5eb7995e | j_mayer | /* Be sure no exception or interrupt is pending */
|
2960 | 5eb7995e | j_mayer | env->pending_interrupts = 0;
|
2961 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2962 | e1833e1f | j_mayer | env->error_code = 0;
|
2963 | 5eb7995e | j_mayer | /* Flush all TLBs */
|
2964 | 5eb7995e | j_mayer | tlb_flush(env, 1);
|
2965 | 0a032cbe | j_mayer | } |
2966 | 0a032cbe | j_mayer | |
2967 | aaed909a | bellard | CPUPPCState *cpu_ppc_init (const char *cpu_model) |
2968 | 0a032cbe | j_mayer | { |
2969 | 0a032cbe | j_mayer | CPUPPCState *env; |
2970 | aaed909a | bellard | const ppc_def_t *def;
|
2971 | aaed909a | bellard | |
2972 | aaed909a | bellard | def = cpu_ppc_find_by_name(cpu_model); |
2973 | aaed909a | bellard | if (!def)
|
2974 | aaed909a | bellard | return NULL; |
2975 | 0a032cbe | j_mayer | |
2976 | 0a032cbe | j_mayer | env = qemu_mallocz(sizeof(CPUPPCState));
|
2977 | 0a032cbe | j_mayer | if (!env)
|
2978 | 0a032cbe | j_mayer | return NULL; |
2979 | 0a032cbe | j_mayer | cpu_exec_init(env); |
2980 | 01ba9816 | ths | env->cpu_model_str = cpu_model; |
2981 | aaed909a | bellard | cpu_ppc_register_internal(env, def); |
2982 | aaed909a | bellard | cpu_ppc_reset(env); |
2983 | 0a032cbe | j_mayer | return env;
|
2984 | 0a032cbe | j_mayer | } |
2985 | 0a032cbe | j_mayer | |
2986 | 0a032cbe | j_mayer | void cpu_ppc_close (CPUPPCState *env)
|
2987 | 0a032cbe | j_mayer | { |
2988 | 0a032cbe | j_mayer | /* Should also remove all opcode tables... */
|
2989 | aaed909a | bellard | qemu_free(env); |
2990 | 0a032cbe | j_mayer | } |