root / target-sh4 / translate.c @ f8ed7070
History | View | Annotate | Download (35.2 kB)
1 | fdf9b3e8 | bellard | /*
|
---|---|---|---|
2 | fdf9b3e8 | bellard | * SH4 translation
|
3 | 5fafdf24 | ths | *
|
4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
|
5 | fdf9b3e8 | bellard | *
|
6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
|
7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
|
9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | fdf9b3e8 | bellard | *
|
11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
|
12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
|
15 | fdf9b3e8 | bellard | *
|
16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | fdf9b3e8 | bellard | * License along with this library; if not, write to the Free Software
|
18 | fdf9b3e8 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 | fdf9b3e8 | bellard | */
|
20 | fdf9b3e8 | bellard | #include <stdarg.h> |
21 | fdf9b3e8 | bellard | #include <stdlib.h> |
22 | fdf9b3e8 | bellard | #include <stdio.h> |
23 | fdf9b3e8 | bellard | #include <string.h> |
24 | fdf9b3e8 | bellard | #include <inttypes.h> |
25 | fdf9b3e8 | bellard | #include <assert.h> |
26 | fdf9b3e8 | bellard | |
27 | fdf9b3e8 | bellard | #define DEBUG_DISAS
|
28 | fdf9b3e8 | bellard | #define SH4_DEBUG_DISAS
|
29 | fdf9b3e8 | bellard | //#define SH4_SINGLE_STEP
|
30 | fdf9b3e8 | bellard | |
31 | fdf9b3e8 | bellard | #include "cpu.h" |
32 | fdf9b3e8 | bellard | #include "exec-all.h" |
33 | fdf9b3e8 | bellard | #include "disas.h" |
34 | 57fec1fe | bellard | #include "tcg-op.h" |
35 | ca10f867 | aurel32 | #include "qemu-common.h" |
36 | fdf9b3e8 | bellard | |
37 | fdf9b3e8 | bellard | typedef struct DisasContext { |
38 | fdf9b3e8 | bellard | struct TranslationBlock *tb;
|
39 | fdf9b3e8 | bellard | target_ulong pc; |
40 | fdf9b3e8 | bellard | uint32_t sr; |
41 | eda9b09b | bellard | uint32_t fpscr; |
42 | fdf9b3e8 | bellard | uint16_t opcode; |
43 | fdf9b3e8 | bellard | uint32_t flags; |
44 | 823029f9 | ths | int bstate;
|
45 | fdf9b3e8 | bellard | int memidx;
|
46 | fdf9b3e8 | bellard | uint32_t delayed_pc; |
47 | fdf9b3e8 | bellard | int singlestep_enabled;
|
48 | fdf9b3e8 | bellard | } DisasContext; |
49 | fdf9b3e8 | bellard | |
50 | 823029f9 | ths | enum {
|
51 | 823029f9 | ths | BS_NONE = 0, /* We go out of the TB without reaching a branch or an |
52 | 823029f9 | ths | * exception condition
|
53 | 823029f9 | ths | */
|
54 | 823029f9 | ths | BS_STOP = 1, /* We want to stop translation for any reason */ |
55 | 823029f9 | ths | BS_BRANCH = 2, /* We reached a branch condition */ |
56 | 823029f9 | ths | BS_EXCP = 3, /* We reached an exception condition */ |
57 | 823029f9 | ths | }; |
58 | 823029f9 | ths | |
59 | fdf9b3e8 | bellard | #ifdef CONFIG_USER_ONLY
|
60 | fdf9b3e8 | bellard | |
61 | eda9b09b | bellard | #define GEN_OP_LD(width, reg) \
|
62 | eda9b09b | bellard | void gen_op_ld##width##_T0_##reg (DisasContext *ctx) { \ |
63 | eda9b09b | bellard | gen_op_ld##width##_T0_##reg##_raw(); \ |
64 | fdf9b3e8 | bellard | } |
65 | eda9b09b | bellard | #define GEN_OP_ST(width, reg) \
|
66 | eda9b09b | bellard | void gen_op_st##width##_##reg##_T1 (DisasContext *ctx) { \ |
67 | eda9b09b | bellard | gen_op_st##width##_##reg##_T1_raw(); \ |
68 | fdf9b3e8 | bellard | } |
69 | fdf9b3e8 | bellard | |
70 | fdf9b3e8 | bellard | #else
|
71 | fdf9b3e8 | bellard | |
72 | eda9b09b | bellard | #define GEN_OP_LD(width, reg) \
|
73 | eda9b09b | bellard | void gen_op_ld##width##_T0_##reg (DisasContext *ctx) { \ |
74 | eda9b09b | bellard | if (ctx->memidx) gen_op_ld##width##_T0_##reg##_kernel(); \ |
75 | eda9b09b | bellard | else gen_op_ld##width##_T0_##reg##_user();\ |
76 | fdf9b3e8 | bellard | } |
77 | eda9b09b | bellard | #define GEN_OP_ST(width, reg) \
|
78 | eda9b09b | bellard | void gen_op_st##width##_##reg##_T1 (DisasContext *ctx) { \ |
79 | eda9b09b | bellard | if (ctx->memidx) gen_op_st##width##_##reg##_T1_kernel(); \ |
80 | eda9b09b | bellard | else gen_op_st##width##_##reg##_T1_user();\ |
81 | fdf9b3e8 | bellard | } |
82 | fdf9b3e8 | bellard | |
83 | fdf9b3e8 | bellard | #endif
|
84 | fdf9b3e8 | bellard | |
85 | eda9b09b | bellard | GEN_OP_LD(ub, T0) |
86 | eda9b09b | bellard | GEN_OP_LD(b, T0) |
87 | eda9b09b | bellard | GEN_OP_ST(b, T0) |
88 | eda9b09b | bellard | GEN_OP_LD(uw, T0) |
89 | eda9b09b | bellard | GEN_OP_LD(w, T0) |
90 | eda9b09b | bellard | GEN_OP_ST(w, T0) |
91 | eda9b09b | bellard | GEN_OP_LD(l, T0) |
92 | eda9b09b | bellard | GEN_OP_ST(l, T0) |
93 | eda9b09b | bellard | GEN_OP_LD(fl, FT0) |
94 | eda9b09b | bellard | GEN_OP_ST(fl, FT0) |
95 | eda9b09b | bellard | GEN_OP_LD(fq, DT0) |
96 | eda9b09b | bellard | GEN_OP_ST(fq, DT0) |
97 | fdf9b3e8 | bellard | |
98 | fdf9b3e8 | bellard | void cpu_dump_state(CPUState * env, FILE * f,
|
99 | fdf9b3e8 | bellard | int (*cpu_fprintf) (FILE * f, const char *fmt, ...), |
100 | fdf9b3e8 | bellard | int flags)
|
101 | fdf9b3e8 | bellard | { |
102 | fdf9b3e8 | bellard | int i;
|
103 | eda9b09b | bellard | cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
|
104 | eda9b09b | bellard | env->pc, env->sr, env->pr, env->fpscr); |
105 | fdf9b3e8 | bellard | for (i = 0; i < 24; i += 4) { |
106 | fdf9b3e8 | bellard | cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
|
107 | fdf9b3e8 | bellard | i, env->gregs[i], i + 1, env->gregs[i + 1], |
108 | fdf9b3e8 | bellard | i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]); |
109 | fdf9b3e8 | bellard | } |
110 | fdf9b3e8 | bellard | if (env->flags & DELAY_SLOT) {
|
111 | fdf9b3e8 | bellard | cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n",
|
112 | fdf9b3e8 | bellard | env->delayed_pc); |
113 | fdf9b3e8 | bellard | } else if (env->flags & DELAY_SLOT_CONDITIONAL) { |
114 | fdf9b3e8 | bellard | cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n",
|
115 | fdf9b3e8 | bellard | env->delayed_pc); |
116 | fdf9b3e8 | bellard | } |
117 | fdf9b3e8 | bellard | } |
118 | fdf9b3e8 | bellard | |
119 | fdf9b3e8 | bellard | void cpu_sh4_reset(CPUSH4State * env)
|
120 | fdf9b3e8 | bellard | { |
121 | 9c2a9ea1 | pbrook | #if defined(CONFIG_USER_ONLY)
|
122 | 4c909d14 | ths | env->sr = SR_FD; /* FD - kernel does lazy fpu context switch */
|
123 | 9c2a9ea1 | pbrook | #else
|
124 | fdf9b3e8 | bellard | env->sr = 0x700000F0; /* MD, RB, BL, I3-I0 */ |
125 | 9c2a9ea1 | pbrook | #endif
|
126 | fdf9b3e8 | bellard | env->vbr = 0;
|
127 | fdf9b3e8 | bellard | env->pc = 0xA0000000;
|
128 | ea6cf6be | ths | #if defined(CONFIG_USER_ONLY)
|
129 | ea6cf6be | ths | env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
|
130 | b0b3de89 | bellard | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
|
131 | ea6cf6be | ths | #else
|
132 | ea6cf6be | ths | env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */ |
133 | b0b3de89 | bellard | set_float_rounding_mode(float_round_to_zero, &env->fp_status); |
134 | ea6cf6be | ths | #endif
|
135 | fdf9b3e8 | bellard | env->mmucr = 0;
|
136 | fdf9b3e8 | bellard | } |
137 | fdf9b3e8 | bellard | |
138 | aaed909a | bellard | CPUSH4State *cpu_sh4_init(const char *cpu_model) |
139 | fdf9b3e8 | bellard | { |
140 | fdf9b3e8 | bellard | CPUSH4State *env; |
141 | fdf9b3e8 | bellard | |
142 | fdf9b3e8 | bellard | env = qemu_mallocz(sizeof(CPUSH4State));
|
143 | fdf9b3e8 | bellard | if (!env)
|
144 | fdf9b3e8 | bellard | return NULL; |
145 | fdf9b3e8 | bellard | cpu_exec_init(env); |
146 | fdf9b3e8 | bellard | cpu_sh4_reset(env); |
147 | fdf9b3e8 | bellard | tlb_flush(env, 1);
|
148 | fdf9b3e8 | bellard | return env;
|
149 | fdf9b3e8 | bellard | } |
150 | fdf9b3e8 | bellard | |
151 | fdf9b3e8 | bellard | static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest) |
152 | fdf9b3e8 | bellard | { |
153 | fdf9b3e8 | bellard | TranslationBlock *tb; |
154 | fdf9b3e8 | bellard | tb = ctx->tb; |
155 | fdf9b3e8 | bellard | |
156 | fdf9b3e8 | bellard | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
|
157 | fdf9b3e8 | bellard | !ctx->singlestep_enabled) { |
158 | fdf9b3e8 | bellard | /* Use a direct jump if in same page and singlestep not enabled */
|
159 | 57fec1fe | bellard | tcg_gen_goto_tb(n); |
160 | 57fec1fe | bellard | gen_op_movl_imm_PC(dest); |
161 | 57fec1fe | bellard | tcg_gen_exit_tb((long) tb + n);
|
162 | fdf9b3e8 | bellard | } else {
|
163 | 57fec1fe | bellard | gen_op_movl_imm_PC(dest); |
164 | 57fec1fe | bellard | if (ctx->singlestep_enabled)
|
165 | 57fec1fe | bellard | gen_op_debug(); |
166 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
167 | fdf9b3e8 | bellard | } |
168 | fdf9b3e8 | bellard | } |
169 | fdf9b3e8 | bellard | |
170 | fdf9b3e8 | bellard | static void gen_jump(DisasContext * ctx) |
171 | fdf9b3e8 | bellard | { |
172 | fdf9b3e8 | bellard | if (ctx->delayed_pc == (uint32_t) - 1) { |
173 | fdf9b3e8 | bellard | /* Target is not statically known, it comes necessarily from a
|
174 | fdf9b3e8 | bellard | delayed jump as immediate jump are conditinal jumps */
|
175 | fdf9b3e8 | bellard | gen_op_movl_delayed_pc_PC(); |
176 | fdf9b3e8 | bellard | if (ctx->singlestep_enabled)
|
177 | fdf9b3e8 | bellard | gen_op_debug(); |
178 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
179 | fdf9b3e8 | bellard | } else {
|
180 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 0, ctx->delayed_pc);
|
181 | fdf9b3e8 | bellard | } |
182 | fdf9b3e8 | bellard | } |
183 | fdf9b3e8 | bellard | |
184 | fdf9b3e8 | bellard | /* Immediate conditional jump (bt or bf) */
|
185 | fdf9b3e8 | bellard | static void gen_conditional_jump(DisasContext * ctx, |
186 | fdf9b3e8 | bellard | target_ulong ift, target_ulong ifnott) |
187 | fdf9b3e8 | bellard | { |
188 | fdf9b3e8 | bellard | int l1;
|
189 | fdf9b3e8 | bellard | |
190 | fdf9b3e8 | bellard | l1 = gen_new_label(); |
191 | fdf9b3e8 | bellard | gen_op_jT(l1); |
192 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 0, ifnott);
|
193 | fdf9b3e8 | bellard | gen_set_label(l1); |
194 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 1, ift);
|
195 | fdf9b3e8 | bellard | } |
196 | fdf9b3e8 | bellard | |
197 | fdf9b3e8 | bellard | /* Delayed conditional jump (bt or bf) */
|
198 | fdf9b3e8 | bellard | static void gen_delayed_conditional_jump(DisasContext * ctx) |
199 | fdf9b3e8 | bellard | { |
200 | fdf9b3e8 | bellard | int l1;
|
201 | fdf9b3e8 | bellard | |
202 | fdf9b3e8 | bellard | l1 = gen_new_label(); |
203 | 9c2a9ea1 | pbrook | gen_op_jdelayed(l1); |
204 | 823029f9 | ths | gen_goto_tb(ctx, 1, ctx->pc + 2); |
205 | fdf9b3e8 | bellard | gen_set_label(l1); |
206 | 9c2a9ea1 | pbrook | gen_jump(ctx); |
207 | fdf9b3e8 | bellard | } |
208 | fdf9b3e8 | bellard | |
209 | fdf9b3e8 | bellard | #define B3_0 (ctx->opcode & 0xf) |
210 | fdf9b3e8 | bellard | #define B6_4 ((ctx->opcode >> 4) & 0x7) |
211 | fdf9b3e8 | bellard | #define B7_4 ((ctx->opcode >> 4) & 0xf) |
212 | fdf9b3e8 | bellard | #define B7_0 (ctx->opcode & 0xff) |
213 | fdf9b3e8 | bellard | #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff)) |
214 | fdf9b3e8 | bellard | #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \ |
215 | fdf9b3e8 | bellard | (ctx->opcode & 0xfff))
|
216 | fdf9b3e8 | bellard | #define B11_8 ((ctx->opcode >> 8) & 0xf) |
217 | fdf9b3e8 | bellard | #define B15_12 ((ctx->opcode >> 12) & 0xf) |
218 | fdf9b3e8 | bellard | |
219 | fdf9b3e8 | bellard | #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \ |
220 | fdf9b3e8 | bellard | (x) + 16 : (x))
|
221 | fdf9b3e8 | bellard | |
222 | fdf9b3e8 | bellard | #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \ |
223 | fdf9b3e8 | bellard | ? (x) + 16 : (x))
|
224 | fdf9b3e8 | bellard | |
225 | eda9b09b | bellard | #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x)) |
226 | f09111e0 | ths | #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) |
227 | eda9b09b | bellard | #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x)) |
228 | ea6cf6be | ths | #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */ |
229 | eda9b09b | bellard | |
230 | fdf9b3e8 | bellard | #define CHECK_NOT_DELAY_SLOT \
|
231 | fdf9b3e8 | bellard | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
|
232 | 823029f9 | ths | {gen_op_raise_slot_illegal_instruction (); ctx->bstate = BS_EXCP; \ |
233 | fdf9b3e8 | bellard | return;}
|
234 | fdf9b3e8 | bellard | |
235 | 823029f9 | ths | void _decode_opc(DisasContext * ctx)
|
236 | fdf9b3e8 | bellard | { |
237 | fdf9b3e8 | bellard | #if 0
|
238 | fdf9b3e8 | bellard | fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
|
239 | fdf9b3e8 | bellard | #endif
|
240 | fdf9b3e8 | bellard | switch (ctx->opcode) {
|
241 | fdf9b3e8 | bellard | case 0x0019: /* div0u */ |
242 | fdf9b3e8 | bellard | gen_op_div0u(); |
243 | fdf9b3e8 | bellard | return;
|
244 | fdf9b3e8 | bellard | case 0x000b: /* rts */ |
245 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT gen_op_rts(); |
246 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
247 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
248 | fdf9b3e8 | bellard | return;
|
249 | fdf9b3e8 | bellard | case 0x0028: /* clrmac */ |
250 | fdf9b3e8 | bellard | gen_op_clrmac(); |
251 | fdf9b3e8 | bellard | return;
|
252 | fdf9b3e8 | bellard | case 0x0048: /* clrs */ |
253 | fdf9b3e8 | bellard | gen_op_clrs(); |
254 | fdf9b3e8 | bellard | return;
|
255 | fdf9b3e8 | bellard | case 0x0008: /* clrt */ |
256 | fdf9b3e8 | bellard | gen_op_clrt(); |
257 | fdf9b3e8 | bellard | return;
|
258 | fdf9b3e8 | bellard | case 0x0038: /* ldtlb */ |
259 | ea2b542a | aurel32 | #if defined(CONFIG_USER_ONLY)
|
260 | fdf9b3e8 | bellard | assert(0); /* XXXXX */ |
261 | ea2b542a | aurel32 | #else
|
262 | ea2b542a | aurel32 | gen_op_ldtlb(); |
263 | ea2b542a | aurel32 | #endif
|
264 | fdf9b3e8 | bellard | return;
|
265 | c5e814b2 | ths | case 0x002b: /* rte */ |
266 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT gen_op_rte(); |
267 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
268 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
269 | fdf9b3e8 | bellard | return;
|
270 | fdf9b3e8 | bellard | case 0x0058: /* sets */ |
271 | fdf9b3e8 | bellard | gen_op_sets(); |
272 | fdf9b3e8 | bellard | return;
|
273 | fdf9b3e8 | bellard | case 0x0018: /* sett */ |
274 | fdf9b3e8 | bellard | gen_op_sett(); |
275 | fdf9b3e8 | bellard | return;
|
276 | 24988dc2 | aurel32 | case 0xfbfd: /* frchg */ |
277 | eda9b09b | bellard | gen_op_frchg(); |
278 | 823029f9 | ths | ctx->bstate = BS_STOP; |
279 | fdf9b3e8 | bellard | return;
|
280 | 24988dc2 | aurel32 | case 0xf3fd: /* fschg */ |
281 | eda9b09b | bellard | gen_op_fschg(); |
282 | 823029f9 | ths | ctx->bstate = BS_STOP; |
283 | fdf9b3e8 | bellard | return;
|
284 | fdf9b3e8 | bellard | case 0x0009: /* nop */ |
285 | fdf9b3e8 | bellard | return;
|
286 | fdf9b3e8 | bellard | case 0x001b: /* sleep */ |
287 | fdf9b3e8 | bellard | assert(0); /* XXXXX */ |
288 | fdf9b3e8 | bellard | return;
|
289 | fdf9b3e8 | bellard | } |
290 | fdf9b3e8 | bellard | |
291 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf000) { |
292 | fdf9b3e8 | bellard | case 0x1000: /* mov.l Rm,@(disp,Rn) */ |
293 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
294 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
295 | fdf9b3e8 | bellard | gen_op_addl_imm_T1(B3_0 * 4);
|
296 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
297 | fdf9b3e8 | bellard | return;
|
298 | fdf9b3e8 | bellard | case 0x5000: /* mov.l @(disp,Rm),Rn */ |
299 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
300 | fdf9b3e8 | bellard | gen_op_addl_imm_T0(B3_0 * 4);
|
301 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
302 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
303 | fdf9b3e8 | bellard | return;
|
304 | 24988dc2 | aurel32 | case 0xe000: /* mov #imm,Rn */ |
305 | fdf9b3e8 | bellard | gen_op_movl_imm_rN(B7_0s, REG(B11_8)); |
306 | fdf9b3e8 | bellard | return;
|
307 | fdf9b3e8 | bellard | case 0x9000: /* mov.w @(disp,PC),Rn */ |
308 | fdf9b3e8 | bellard | gen_op_movl_imm_T0(ctx->pc + 4 + B7_0 * 2); |
309 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
310 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
311 | fdf9b3e8 | bellard | return;
|
312 | fdf9b3e8 | bellard | case 0xd000: /* mov.l @(disp,PC),Rn */ |
313 | fdf9b3e8 | bellard | gen_op_movl_imm_T0((ctx->pc + 4 + B7_0 * 4) & ~3); |
314 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
315 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
316 | fdf9b3e8 | bellard | return;
|
317 | 24988dc2 | aurel32 | case 0x7000: /* add #imm,Rn */ |
318 | fdf9b3e8 | bellard | gen_op_add_imm_rN(B7_0s, REG(B11_8)); |
319 | fdf9b3e8 | bellard | return;
|
320 | fdf9b3e8 | bellard | case 0xa000: /* bra disp */ |
321 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
322 | fdf9b3e8 | bellard | gen_op_bra(ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2); |
323 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
324 | fdf9b3e8 | bellard | return;
|
325 | fdf9b3e8 | bellard | case 0xb000: /* bsr disp */ |
326 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
327 | fdf9b3e8 | bellard | gen_op_bsr(ctx->pc + 4, ctx->delayed_pc =
|
328 | fdf9b3e8 | bellard | ctx->pc + 4 + B11_0s * 2); |
329 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
330 | fdf9b3e8 | bellard | return;
|
331 | fdf9b3e8 | bellard | } |
332 | fdf9b3e8 | bellard | |
333 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf00f) { |
334 | fdf9b3e8 | bellard | case 0x6003: /* mov Rm,Rn */ |
335 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
336 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
337 | fdf9b3e8 | bellard | return;
|
338 | fdf9b3e8 | bellard | case 0x2000: /* mov.b Rm,@Rn */ |
339 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
340 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
341 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
342 | fdf9b3e8 | bellard | return;
|
343 | fdf9b3e8 | bellard | case 0x2001: /* mov.w Rm,@Rn */ |
344 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
345 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
346 | fdf9b3e8 | bellard | gen_op_stw_T0_T1(ctx); |
347 | fdf9b3e8 | bellard | return;
|
348 | fdf9b3e8 | bellard | case 0x2002: /* mov.l Rm,@Rn */ |
349 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
350 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
351 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
352 | fdf9b3e8 | bellard | return;
|
353 | fdf9b3e8 | bellard | case 0x6000: /* mov.b @Rm,Rn */ |
354 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
355 | fdf9b3e8 | bellard | gen_op_ldb_T0_T0(ctx); |
356 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
357 | fdf9b3e8 | bellard | return;
|
358 | fdf9b3e8 | bellard | case 0x6001: /* mov.w @Rm,Rn */ |
359 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
360 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
361 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
362 | fdf9b3e8 | bellard | return;
|
363 | fdf9b3e8 | bellard | case 0x6002: /* mov.l @Rm,Rn */ |
364 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
365 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
366 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
367 | fdf9b3e8 | bellard | return;
|
368 | fdf9b3e8 | bellard | case 0x2004: /* mov.b Rm,@-Rn */ |
369 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
370 | 24988dc2 | aurel32 | gen_op_dec1_rN(REG(B11_8)); |
371 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
372 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
373 | fdf9b3e8 | bellard | return;
|
374 | fdf9b3e8 | bellard | case 0x2005: /* mov.w Rm,@-Rn */ |
375 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
376 | 24988dc2 | aurel32 | gen_op_dec2_rN(REG(B11_8)); |
377 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
378 | fdf9b3e8 | bellard | gen_op_stw_T0_T1(ctx); |
379 | fdf9b3e8 | bellard | return;
|
380 | fdf9b3e8 | bellard | case 0x2006: /* mov.l Rm,@-Rn */ |
381 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
382 | 24988dc2 | aurel32 | gen_op_dec4_rN(REG(B11_8)); |
383 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
384 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
385 | fdf9b3e8 | bellard | return;
|
386 | eda9b09b | bellard | case 0x6004: /* mov.b @Rm+,Rn */ |
387 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
388 | fdf9b3e8 | bellard | gen_op_ldb_T0_T0(ctx); |
389 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
390 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
391 | 24988dc2 | aurel32 | gen_op_inc1_rN(REG(B7_4)); |
392 | fdf9b3e8 | bellard | return;
|
393 | fdf9b3e8 | bellard | case 0x6005: /* mov.w @Rm+,Rn */ |
394 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
395 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
396 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
397 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
398 | 24988dc2 | aurel32 | gen_op_inc2_rN(REG(B7_4)); |
399 | fdf9b3e8 | bellard | return;
|
400 | fdf9b3e8 | bellard | case 0x6006: /* mov.l @Rm+,Rn */ |
401 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
402 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
403 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
404 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
405 | 24988dc2 | aurel32 | gen_op_inc4_rN(REG(B7_4)); |
406 | fdf9b3e8 | bellard | return;
|
407 | fdf9b3e8 | bellard | case 0x0004: /* mov.b Rm,@(R0,Rn) */ |
408 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
409 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
410 | fdf9b3e8 | bellard | gen_op_add_rN_T1(REG(0));
|
411 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
412 | fdf9b3e8 | bellard | return;
|
413 | fdf9b3e8 | bellard | case 0x0005: /* mov.w Rm,@(R0,Rn) */ |
414 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
415 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
416 | fdf9b3e8 | bellard | gen_op_add_rN_T1(REG(0));
|
417 | fdf9b3e8 | bellard | gen_op_stw_T0_T1(ctx); |
418 | fdf9b3e8 | bellard | return;
|
419 | fdf9b3e8 | bellard | case 0x0006: /* mov.l Rm,@(R0,Rn) */ |
420 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
421 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
422 | fdf9b3e8 | bellard | gen_op_add_rN_T1(REG(0));
|
423 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
424 | fdf9b3e8 | bellard | return;
|
425 | fdf9b3e8 | bellard | case 0x000c: /* mov.b @(R0,Rm),Rn */ |
426 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
427 | fdf9b3e8 | bellard | gen_op_add_rN_T0(REG(0));
|
428 | fdf9b3e8 | bellard | gen_op_ldb_T0_T0(ctx); |
429 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
430 | fdf9b3e8 | bellard | return;
|
431 | fdf9b3e8 | bellard | case 0x000d: /* mov.w @(R0,Rm),Rn */ |
432 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
433 | fdf9b3e8 | bellard | gen_op_add_rN_T0(REG(0));
|
434 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
435 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
436 | fdf9b3e8 | bellard | return;
|
437 | fdf9b3e8 | bellard | case 0x000e: /* mov.l @(R0,Rm),Rn */ |
438 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
439 | fdf9b3e8 | bellard | gen_op_add_rN_T0(REG(0));
|
440 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
441 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
442 | fdf9b3e8 | bellard | return;
|
443 | fdf9b3e8 | bellard | case 0x6008: /* swap.b Rm,Rn */ |
444 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
445 | fdf9b3e8 | bellard | gen_op_swapb_T0(); |
446 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
447 | fdf9b3e8 | bellard | return;
|
448 | fdf9b3e8 | bellard | case 0x6009: /* swap.w Rm,Rn */ |
449 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
450 | fdf9b3e8 | bellard | gen_op_swapw_T0(); |
451 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
452 | fdf9b3e8 | bellard | return;
|
453 | fdf9b3e8 | bellard | case 0x200d: /* xtrct Rm,Rn */ |
454 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
455 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
456 | fdf9b3e8 | bellard | gen_op_xtrct_T0_T1(); |
457 | fdf9b3e8 | bellard | gen_op_movl_T1_rN(REG(B11_8)); |
458 | fdf9b3e8 | bellard | return;
|
459 | fdf9b3e8 | bellard | case 0x300c: /* add Rm,Rn */ |
460 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
461 | fdf9b3e8 | bellard | gen_op_add_T0_rN(REG(B11_8)); |
462 | fdf9b3e8 | bellard | return;
|
463 | fdf9b3e8 | bellard | case 0x300e: /* addc Rm,Rn */ |
464 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
465 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
466 | fdf9b3e8 | bellard | gen_op_addc_T0_T1(); |
467 | fdf9b3e8 | bellard | gen_op_movl_T1_rN(REG(B11_8)); |
468 | fdf9b3e8 | bellard | return;
|
469 | fdf9b3e8 | bellard | case 0x300f: /* addv Rm,Rn */ |
470 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
471 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
472 | fdf9b3e8 | bellard | gen_op_addv_T0_T1(); |
473 | fdf9b3e8 | bellard | gen_op_movl_T1_rN(REG(B11_8)); |
474 | fdf9b3e8 | bellard | return;
|
475 | fdf9b3e8 | bellard | case 0x2009: /* and Rm,Rn */ |
476 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
477 | fdf9b3e8 | bellard | gen_op_and_T0_rN(REG(B11_8)); |
478 | fdf9b3e8 | bellard | return;
|
479 | fdf9b3e8 | bellard | case 0x3000: /* cmp/eq Rm,Rn */ |
480 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
481 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
482 | fdf9b3e8 | bellard | gen_op_cmp_eq_T0_T1(); |
483 | fdf9b3e8 | bellard | return;
|
484 | fdf9b3e8 | bellard | case 0x3003: /* cmp/ge Rm,Rn */ |
485 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
486 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
487 | fdf9b3e8 | bellard | gen_op_cmp_ge_T0_T1(); |
488 | fdf9b3e8 | bellard | return;
|
489 | fdf9b3e8 | bellard | case 0x3007: /* cmp/gt Rm,Rn */ |
490 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
491 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
492 | fdf9b3e8 | bellard | gen_op_cmp_gt_T0_T1(); |
493 | fdf9b3e8 | bellard | return;
|
494 | fdf9b3e8 | bellard | case 0x3006: /* cmp/hi Rm,Rn */ |
495 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
496 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
497 | fdf9b3e8 | bellard | gen_op_cmp_hi_T0_T1(); |
498 | fdf9b3e8 | bellard | return;
|
499 | fdf9b3e8 | bellard | case 0x3002: /* cmp/hs Rm,Rn */ |
500 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
501 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
502 | fdf9b3e8 | bellard | gen_op_cmp_hs_T0_T1(); |
503 | fdf9b3e8 | bellard | return;
|
504 | fdf9b3e8 | bellard | case 0x200c: /* cmp/str Rm,Rn */ |
505 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
506 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
507 | fdf9b3e8 | bellard | gen_op_cmp_str_T0_T1(); |
508 | fdf9b3e8 | bellard | return;
|
509 | fdf9b3e8 | bellard | case 0x2007: /* div0s Rm,Rn */ |
510 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
511 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
512 | fdf9b3e8 | bellard | gen_op_div0s_T0_T1(); |
513 | fdf9b3e8 | bellard | return;
|
514 | fdf9b3e8 | bellard | case 0x3004: /* div1 Rm,Rn */ |
515 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
516 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
517 | fdf9b3e8 | bellard | gen_op_div1_T0_T1(); |
518 | fdf9b3e8 | bellard | gen_op_movl_T1_rN(REG(B11_8)); |
519 | fdf9b3e8 | bellard | return;
|
520 | fdf9b3e8 | bellard | case 0x300d: /* dmuls.l Rm,Rn */ |
521 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
522 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
523 | fdf9b3e8 | bellard | gen_op_dmulsl_T0_T1(); |
524 | fdf9b3e8 | bellard | return;
|
525 | fdf9b3e8 | bellard | case 0x3005: /* dmulu.l Rm,Rn */ |
526 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
527 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
528 | fdf9b3e8 | bellard | gen_op_dmulul_T0_T1(); |
529 | fdf9b3e8 | bellard | return;
|
530 | fdf9b3e8 | bellard | case 0x600e: /* exts.b Rm,Rn */ |
531 | fdf9b3e8 | bellard | gen_op_movb_rN_T0(REG(B7_4)); |
532 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
533 | fdf9b3e8 | bellard | return;
|
534 | fdf9b3e8 | bellard | case 0x600f: /* exts.w Rm,Rn */ |
535 | fdf9b3e8 | bellard | gen_op_movw_rN_T0(REG(B7_4)); |
536 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
537 | fdf9b3e8 | bellard | return;
|
538 | fdf9b3e8 | bellard | case 0x600c: /* extu.b Rm,Rn */ |
539 | fdf9b3e8 | bellard | gen_op_movub_rN_T0(REG(B7_4)); |
540 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
541 | fdf9b3e8 | bellard | return;
|
542 | fdf9b3e8 | bellard | case 0x600d: /* extu.w Rm,Rn */ |
543 | fdf9b3e8 | bellard | gen_op_movuw_rN_T0(REG(B7_4)); |
544 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
545 | fdf9b3e8 | bellard | return;
|
546 | 24988dc2 | aurel32 | case 0x000f: /* mac.l @Rm+,@Rn+ */ |
547 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B11_8)); |
548 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
549 | fdf9b3e8 | bellard | gen_op_movl_T0_T1(); |
550 | 24988dc2 | aurel32 | gen_op_inc4_rN(REG(B11_8)); |
551 | 24988dc2 | aurel32 | gen_op_movl_rN_T0(REG(B7_4)); |
552 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
553 | fdf9b3e8 | bellard | gen_op_macl_T0_T1(); |
554 | fdf9b3e8 | bellard | gen_op_inc4_rN(REG(B7_4)); |
555 | fdf9b3e8 | bellard | return;
|
556 | fdf9b3e8 | bellard | case 0x400f: /* mac.w @Rm+,@Rn+ */ |
557 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B11_8)); |
558 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
559 | fdf9b3e8 | bellard | gen_op_movl_T0_T1(); |
560 | 24988dc2 | aurel32 | gen_op_inc2_rN(REG(B11_8)); |
561 | 24988dc2 | aurel32 | gen_op_movl_rN_T0(REG(B7_4)); |
562 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
563 | fdf9b3e8 | bellard | gen_op_macw_T0_T1(); |
564 | fdf9b3e8 | bellard | gen_op_inc2_rN(REG(B7_4)); |
565 | fdf9b3e8 | bellard | return;
|
566 | fdf9b3e8 | bellard | case 0x0007: /* mul.l Rm,Rn */ |
567 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
568 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
569 | fdf9b3e8 | bellard | gen_op_mull_T0_T1(); |
570 | fdf9b3e8 | bellard | return;
|
571 | fdf9b3e8 | bellard | case 0x200f: /* muls.w Rm,Rn */ |
572 | fdf9b3e8 | bellard | gen_op_movw_rN_T0(REG(B7_4)); |
573 | fdf9b3e8 | bellard | gen_op_movw_rN_T1(REG(B11_8)); |
574 | fdf9b3e8 | bellard | gen_op_mulsw_T0_T1(); |
575 | fdf9b3e8 | bellard | return;
|
576 | fdf9b3e8 | bellard | case 0x200e: /* mulu.w Rm,Rn */ |
577 | fdf9b3e8 | bellard | gen_op_movuw_rN_T0(REG(B7_4)); |
578 | fdf9b3e8 | bellard | gen_op_movuw_rN_T1(REG(B11_8)); |
579 | fdf9b3e8 | bellard | gen_op_muluw_T0_T1(); |
580 | fdf9b3e8 | bellard | return;
|
581 | fdf9b3e8 | bellard | case 0x600b: /* neg Rm,Rn */ |
582 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
583 | fdf9b3e8 | bellard | gen_op_neg_T0(); |
584 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
585 | fdf9b3e8 | bellard | return;
|
586 | fdf9b3e8 | bellard | case 0x600a: /* negc Rm,Rn */ |
587 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
588 | fdf9b3e8 | bellard | gen_op_negc_T0(); |
589 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
590 | fdf9b3e8 | bellard | return;
|
591 | fdf9b3e8 | bellard | case 0x6007: /* not Rm,Rn */ |
592 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
593 | fdf9b3e8 | bellard | gen_op_not_T0(); |
594 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
595 | fdf9b3e8 | bellard | return;
|
596 | fdf9b3e8 | bellard | case 0x200b: /* or Rm,Rn */ |
597 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
598 | fdf9b3e8 | bellard | gen_op_or_T0_rN(REG(B11_8)); |
599 | fdf9b3e8 | bellard | return;
|
600 | fdf9b3e8 | bellard | case 0x400c: /* shad Rm,Rn */ |
601 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
602 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
603 | fdf9b3e8 | bellard | gen_op_shad_T0_T1(); |
604 | fdf9b3e8 | bellard | gen_op_movl_T1_rN(REG(B11_8)); |
605 | fdf9b3e8 | bellard | return;
|
606 | fdf9b3e8 | bellard | case 0x400d: /* shld Rm,Rn */ |
607 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
608 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
609 | fdf9b3e8 | bellard | gen_op_shld_T0_T1(); |
610 | fdf9b3e8 | bellard | gen_op_movl_T1_rN(REG(B11_8)); |
611 | fdf9b3e8 | bellard | return;
|
612 | fdf9b3e8 | bellard | case 0x3008: /* sub Rm,Rn */ |
613 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
614 | fdf9b3e8 | bellard | gen_op_sub_T0_rN(REG(B11_8)); |
615 | fdf9b3e8 | bellard | return;
|
616 | fdf9b3e8 | bellard | case 0x300a: /* subc Rm,Rn */ |
617 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
618 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
619 | fdf9b3e8 | bellard | gen_op_subc_T0_T1(); |
620 | fdf9b3e8 | bellard | gen_op_movl_T1_rN(REG(B11_8)); |
621 | fdf9b3e8 | bellard | return;
|
622 | fdf9b3e8 | bellard | case 0x300b: /* subv Rm,Rn */ |
623 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
624 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
625 | fdf9b3e8 | bellard | gen_op_subv_T0_T1(); |
626 | fdf9b3e8 | bellard | gen_op_movl_T1_rN(REG(B11_8)); |
627 | fdf9b3e8 | bellard | return;
|
628 | fdf9b3e8 | bellard | case 0x2008: /* tst Rm,Rn */ |
629 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
630 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
631 | fdf9b3e8 | bellard | gen_op_tst_T0_T1(); |
632 | fdf9b3e8 | bellard | return;
|
633 | fdf9b3e8 | bellard | case 0x200a: /* xor Rm,Rn */ |
634 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
635 | fdf9b3e8 | bellard | gen_op_xor_T0_rN(REG(B11_8)); |
636 | fdf9b3e8 | bellard | return;
|
637 | e67888a7 | ths | case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ |
638 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
639 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(XREG(B7_4)); |
640 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(XREG(B11_8)); |
641 | eda9b09b | bellard | } else {
|
642 | eda9b09b | bellard | gen_op_fmov_frN_FT0(FREG(B7_4)); |
643 | eda9b09b | bellard | gen_op_fmov_FT0_frN(FREG(B11_8)); |
644 | eda9b09b | bellard | } |
645 | eda9b09b | bellard | return;
|
646 | e67888a7 | ths | case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ |
647 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
648 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(XREG(B7_4)); |
649 | eda9b09b | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
650 | eda9b09b | bellard | gen_op_stfq_DT0_T1(ctx); |
651 | eda9b09b | bellard | } else {
|
652 | eda9b09b | bellard | gen_op_fmov_frN_FT0(FREG(B7_4)); |
653 | eda9b09b | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
654 | eda9b09b | bellard | gen_op_stfl_FT0_T1(ctx); |
655 | eda9b09b | bellard | } |
656 | eda9b09b | bellard | return;
|
657 | e67888a7 | ths | case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ |
658 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
659 | eda9b09b | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
660 | eda9b09b | bellard | gen_op_ldfq_T0_DT0(ctx); |
661 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(XREG(B11_8)); |
662 | eda9b09b | bellard | } else {
|
663 | eda9b09b | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
664 | eda9b09b | bellard | gen_op_ldfl_T0_FT0(ctx); |
665 | f09111e0 | ths | gen_op_fmov_FT0_frN(FREG(B11_8)); |
666 | eda9b09b | bellard | } |
667 | eda9b09b | bellard | return;
|
668 | e67888a7 | ths | case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ |
669 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
670 | eda9b09b | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
671 | eda9b09b | bellard | gen_op_ldfq_T0_DT0(ctx); |
672 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(XREG(B11_8)); |
673 | eda9b09b | bellard | gen_op_inc8_rN(REG(B7_4)); |
674 | eda9b09b | bellard | } else {
|
675 | eda9b09b | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
676 | eda9b09b | bellard | gen_op_ldfl_T0_FT0(ctx); |
677 | f09111e0 | ths | gen_op_fmov_FT0_frN(FREG(B11_8)); |
678 | eda9b09b | bellard | gen_op_inc4_rN(REG(B7_4)); |
679 | eda9b09b | bellard | } |
680 | eda9b09b | bellard | return;
|
681 | e67888a7 | ths | case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ |
682 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
683 | eda9b09b | bellard | gen_op_dec8_rN(REG(B11_8)); |
684 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(XREG(B7_4)); |
685 | eda9b09b | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
686 | eda9b09b | bellard | gen_op_stfq_DT0_T1(ctx); |
687 | eda9b09b | bellard | } else {
|
688 | eda9b09b | bellard | gen_op_dec4_rN(REG(B11_8)); |
689 | eda9b09b | bellard | gen_op_fmov_frN_FT0(FREG(B7_4)); |
690 | eda9b09b | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
691 | eda9b09b | bellard | gen_op_stfl_FT0_T1(ctx); |
692 | eda9b09b | bellard | } |
693 | eda9b09b | bellard | return;
|
694 | e67888a7 | ths | case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ |
695 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
696 | eda9b09b | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
697 | eda9b09b | bellard | gen_op_add_rN_T0(REG(0));
|
698 | eda9b09b | bellard | gen_op_ldfq_T0_DT0(ctx); |
699 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(XREG(B11_8)); |
700 | eda9b09b | bellard | } else {
|
701 | eda9b09b | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
702 | eda9b09b | bellard | gen_op_add_rN_T0(REG(0));
|
703 | eda9b09b | bellard | gen_op_ldfl_T0_FT0(ctx); |
704 | f09111e0 | ths | gen_op_fmov_FT0_frN(FREG(B11_8)); |
705 | eda9b09b | bellard | } |
706 | eda9b09b | bellard | return;
|
707 | e67888a7 | ths | case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ |
708 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
709 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(XREG(B7_4)); |
710 | eda9b09b | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
711 | eda9b09b | bellard | gen_op_add_rN_T1(REG(0));
|
712 | eda9b09b | bellard | gen_op_stfq_DT0_T1(ctx); |
713 | eda9b09b | bellard | } else {
|
714 | eda9b09b | bellard | gen_op_fmov_frN_FT0(FREG(B7_4)); |
715 | eda9b09b | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
716 | eda9b09b | bellard | gen_op_add_rN_T1(REG(0));
|
717 | eda9b09b | bellard | gen_op_stfl_FT0_T1(ctx); |
718 | eda9b09b | bellard | } |
719 | eda9b09b | bellard | return;
|
720 | e67888a7 | ths | case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
721 | e67888a7 | ths | case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
722 | e67888a7 | ths | case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
723 | e67888a7 | ths | case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
724 | e67888a7 | ths | case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
725 | e67888a7 | ths | case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
726 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
727 | ea6cf6be | ths | if (ctx->opcode & 0x0110) |
728 | ea6cf6be | ths | break; /* illegal instruction */ |
729 | ea6cf6be | ths | gen_op_fmov_drN_DT1(DREG(B7_4)); |
730 | ea6cf6be | ths | gen_op_fmov_drN_DT0(DREG(B11_8)); |
731 | ea6cf6be | ths | } |
732 | ea6cf6be | ths | else {
|
733 | ea6cf6be | ths | gen_op_fmov_frN_FT1(FREG(B7_4)); |
734 | ea6cf6be | ths | gen_op_fmov_frN_FT0(FREG(B11_8)); |
735 | ea6cf6be | ths | } |
736 | ea6cf6be | ths | |
737 | ea6cf6be | ths | switch (ctx->opcode & 0xf00f) { |
738 | ea6cf6be | ths | case 0xf000: /* fadd Rm,Rn */ |
739 | ea6cf6be | ths | ctx->fpscr & FPSCR_PR ? gen_op_fadd_DT() : gen_op_fadd_FT(); |
740 | ea6cf6be | ths | break;
|
741 | ea6cf6be | ths | case 0xf001: /* fsub Rm,Rn */ |
742 | ea6cf6be | ths | ctx->fpscr & FPSCR_PR ? gen_op_fsub_DT() : gen_op_fsub_FT(); |
743 | ea6cf6be | ths | break;
|
744 | ea6cf6be | ths | case 0xf002: /* fmul Rm,Rn */ |
745 | ea6cf6be | ths | ctx->fpscr & FPSCR_PR ? gen_op_fmul_DT() : gen_op_fmul_FT(); |
746 | ea6cf6be | ths | break;
|
747 | ea6cf6be | ths | case 0xf003: /* fdiv Rm,Rn */ |
748 | ea6cf6be | ths | ctx->fpscr & FPSCR_PR ? gen_op_fdiv_DT() : gen_op_fdiv_FT(); |
749 | ea6cf6be | ths | break;
|
750 | ea6cf6be | ths | case 0xf004: /* fcmp/eq Rm,Rn */ |
751 | 24988dc2 | aurel32 | ctx->fpscr & FPSCR_PR ? gen_op_fcmp_eq_DT() : gen_op_fcmp_eq_FT(); |
752 | ea6cf6be | ths | return;
|
753 | ea6cf6be | ths | case 0xf005: /* fcmp/gt Rm,Rn */ |
754 | 24988dc2 | aurel32 | ctx->fpscr & FPSCR_PR ? gen_op_fcmp_gt_DT() : gen_op_fcmp_gt_FT(); |
755 | ea6cf6be | ths | return;
|
756 | ea6cf6be | ths | } |
757 | ea6cf6be | ths | |
758 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
759 | ea6cf6be | ths | gen_op_fmov_DT0_drN(DREG(B11_8)); |
760 | ea6cf6be | ths | } |
761 | ea6cf6be | ths | else {
|
762 | ea6cf6be | ths | gen_op_fmov_FT0_frN(FREG(B11_8)); |
763 | ea6cf6be | ths | } |
764 | ea6cf6be | ths | return;
|
765 | fdf9b3e8 | bellard | } |
766 | fdf9b3e8 | bellard | |
767 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xff00) { |
768 | fdf9b3e8 | bellard | case 0xc900: /* and #imm,R0 */ |
769 | fdf9b3e8 | bellard | gen_op_and_imm_rN(B7_0, REG(0));
|
770 | fdf9b3e8 | bellard | return;
|
771 | 24988dc2 | aurel32 | case 0xcd00: /* and.b #imm,@(R0,GBR) */ |
772 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
773 | fdf9b3e8 | bellard | gen_op_addl_GBR_T0(); |
774 | fdf9b3e8 | bellard | gen_op_movl_T0_T1(); |
775 | 24988dc2 | aurel32 | gen_op_ldub_T0_T0(ctx); |
776 | fdf9b3e8 | bellard | gen_op_and_imm_T0(B7_0); |
777 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
778 | fdf9b3e8 | bellard | return;
|
779 | fdf9b3e8 | bellard | case 0x8b00: /* bf label */ |
780 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
781 | fdf9b3e8 | bellard | gen_conditional_jump(ctx, ctx->pc + 2,
|
782 | fdf9b3e8 | bellard | ctx->pc + 4 + B7_0s * 2); |
783 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
784 | fdf9b3e8 | bellard | return;
|
785 | fdf9b3e8 | bellard | case 0x8f00: /* bf/s label */ |
786 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
787 | fdf9b3e8 | bellard | gen_op_bf_s(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2); |
788 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
789 | fdf9b3e8 | bellard | return;
|
790 | fdf9b3e8 | bellard | case 0x8900: /* bt label */ |
791 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
792 | fdf9b3e8 | bellard | gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, |
793 | fdf9b3e8 | bellard | ctx->pc + 2);
|
794 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
795 | fdf9b3e8 | bellard | return;
|
796 | fdf9b3e8 | bellard | case 0x8d00: /* bt/s label */ |
797 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
798 | fdf9b3e8 | bellard | gen_op_bt_s(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2); |
799 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
800 | fdf9b3e8 | bellard | return;
|
801 | fdf9b3e8 | bellard | case 0x8800: /* cmp/eq #imm,R0 */ |
802 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
803 | fdf9b3e8 | bellard | gen_op_cmp_eq_imm_T0(B7_0s); |
804 | fdf9b3e8 | bellard | return;
|
805 | fdf9b3e8 | bellard | case 0xc400: /* mov.b @(disp,GBR),R0 */ |
806 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
807 | fdf9b3e8 | bellard | gen_op_addl_imm_T0(B7_0); |
808 | fdf9b3e8 | bellard | gen_op_ldb_T0_T0(ctx); |
809 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(0));
|
810 | fdf9b3e8 | bellard | return;
|
811 | fdf9b3e8 | bellard | case 0xc500: /* mov.w @(disp,GBR),R0 */ |
812 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
813 | 24988dc2 | aurel32 | gen_op_addl_imm_T0(B7_0 * 2);
|
814 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
815 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(0));
|
816 | fdf9b3e8 | bellard | return;
|
817 | fdf9b3e8 | bellard | case 0xc600: /* mov.l @(disp,GBR),R0 */ |
818 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
819 | 24988dc2 | aurel32 | gen_op_addl_imm_T0(B7_0 * 4);
|
820 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
821 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(0));
|
822 | fdf9b3e8 | bellard | return;
|
823 | fdf9b3e8 | bellard | case 0xc000: /* mov.b R0,@(disp,GBR) */ |
824 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
825 | fdf9b3e8 | bellard | gen_op_addl_imm_T0(B7_0); |
826 | fdf9b3e8 | bellard | gen_op_movl_T0_T1(); |
827 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
828 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
829 | fdf9b3e8 | bellard | return;
|
830 | fdf9b3e8 | bellard | case 0xc100: /* mov.w R0,@(disp,GBR) */ |
831 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
832 | 24988dc2 | aurel32 | gen_op_addl_imm_T0(B7_0 * 2);
|
833 | fdf9b3e8 | bellard | gen_op_movl_T0_T1(); |
834 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
835 | fdf9b3e8 | bellard | gen_op_stw_T0_T1(ctx); |
836 | fdf9b3e8 | bellard | return;
|
837 | fdf9b3e8 | bellard | case 0xc200: /* mov.l R0,@(disp,GBR) */ |
838 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
839 | 24988dc2 | aurel32 | gen_op_addl_imm_T0(B7_0 * 4);
|
840 | fdf9b3e8 | bellard | gen_op_movl_T0_T1(); |
841 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
842 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
843 | fdf9b3e8 | bellard | return;
|
844 | fdf9b3e8 | bellard | case 0x8000: /* mov.b R0,@(disp,Rn) */ |
845 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
846 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B7_4)); |
847 | fdf9b3e8 | bellard | gen_op_addl_imm_T1(B3_0); |
848 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
849 | fdf9b3e8 | bellard | return;
|
850 | fdf9b3e8 | bellard | case 0x8100: /* mov.w R0,@(disp,Rn) */ |
851 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
852 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B7_4)); |
853 | fdf9b3e8 | bellard | gen_op_addl_imm_T1(B3_0 * 2);
|
854 | fdf9b3e8 | bellard | gen_op_stw_T0_T1(ctx); |
855 | fdf9b3e8 | bellard | return;
|
856 | fdf9b3e8 | bellard | case 0x8400: /* mov.b @(disp,Rn),R0 */ |
857 | 8c2cc7ce | ths | gen_op_movl_rN_T0(REG(B7_4)); |
858 | 8c2cc7ce | ths | gen_op_addl_imm_T0(B3_0); |
859 | 8c2cc7ce | ths | gen_op_ldb_T0_T0(ctx); |
860 | 8c2cc7ce | ths | gen_op_movl_T0_rN(REG(0));
|
861 | fdf9b3e8 | bellard | return;
|
862 | fdf9b3e8 | bellard | case 0x8500: /* mov.w @(disp,Rn),R0 */ |
863 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
864 | fdf9b3e8 | bellard | gen_op_addl_imm_T0(B3_0 * 2);
|
865 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
866 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(0));
|
867 | fdf9b3e8 | bellard | return;
|
868 | fdf9b3e8 | bellard | case 0xc700: /* mova @(disp,PC),R0 */ |
869 | fdf9b3e8 | bellard | gen_op_movl_imm_rN(((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3, |
870 | fdf9b3e8 | bellard | REG(0));
|
871 | fdf9b3e8 | bellard | return;
|
872 | fdf9b3e8 | bellard | case 0xcb00: /* or #imm,R0 */ |
873 | fdf9b3e8 | bellard | gen_op_or_imm_rN(B7_0, REG(0));
|
874 | fdf9b3e8 | bellard | return;
|
875 | 24988dc2 | aurel32 | case 0xcf00: /* or.b #imm,@(R0,GBR) */ |
876 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
877 | fdf9b3e8 | bellard | gen_op_addl_GBR_T0(); |
878 | fdf9b3e8 | bellard | gen_op_movl_T0_T1(); |
879 | 24988dc2 | aurel32 | gen_op_ldub_T0_T0(ctx); |
880 | fdf9b3e8 | bellard | gen_op_or_imm_T0(B7_0); |
881 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
882 | fdf9b3e8 | bellard | return;
|
883 | fdf9b3e8 | bellard | case 0xc300: /* trapa #imm */ |
884 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT gen_op_movl_imm_PC(ctx->pc); |
885 | fdf9b3e8 | bellard | gen_op_trapa(B7_0); |
886 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
887 | fdf9b3e8 | bellard | return;
|
888 | fdf9b3e8 | bellard | case 0xc800: /* tst #imm,R0 */ |
889 | fdf9b3e8 | bellard | gen_op_tst_imm_rN(B7_0, REG(0));
|
890 | fdf9b3e8 | bellard | return;
|
891 | 24988dc2 | aurel32 | case 0xcc00: /* tst.b #imm,@(R0,GBR) */ |
892 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
893 | fdf9b3e8 | bellard | gen_op_addl_GBR_T0(); |
894 | 24988dc2 | aurel32 | gen_op_ldub_T0_T0(ctx); |
895 | fdf9b3e8 | bellard | gen_op_tst_imm_T0(B7_0); |
896 | fdf9b3e8 | bellard | return;
|
897 | fdf9b3e8 | bellard | case 0xca00: /* xor #imm,R0 */ |
898 | fdf9b3e8 | bellard | gen_op_xor_imm_rN(B7_0, REG(0));
|
899 | fdf9b3e8 | bellard | return;
|
900 | 24988dc2 | aurel32 | case 0xce00: /* xor.b #imm,@(R0,GBR) */ |
901 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
902 | fdf9b3e8 | bellard | gen_op_addl_GBR_T0(); |
903 | fdf9b3e8 | bellard | gen_op_movl_T0_T1(); |
904 | 24988dc2 | aurel32 | gen_op_ldub_T0_T0(ctx); |
905 | fdf9b3e8 | bellard | gen_op_xor_imm_T0(B7_0); |
906 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
907 | fdf9b3e8 | bellard | return;
|
908 | fdf9b3e8 | bellard | } |
909 | fdf9b3e8 | bellard | |
910 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf08f) { |
911 | fdf9b3e8 | bellard | case 0x408e: /* ldc Rm,Rn_BANK */ |
912 | fdf9b3e8 | bellard | gen_op_movl_rN_rN(REG(B11_8), ALTREG(B6_4)); |
913 | fdf9b3e8 | bellard | return;
|
914 | fdf9b3e8 | bellard | case 0x4087: /* ldc.l @Rm+,Rn_BANK */ |
915 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B11_8)); |
916 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
917 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(ALTREG(B6_4)); |
918 | fdf9b3e8 | bellard | gen_op_inc4_rN(REG(B11_8)); |
919 | fdf9b3e8 | bellard | return;
|
920 | fdf9b3e8 | bellard | case 0x0082: /* stc Rm_BANK,Rn */ |
921 | fdf9b3e8 | bellard | gen_op_movl_rN_rN(ALTREG(B6_4), REG(B11_8)); |
922 | fdf9b3e8 | bellard | return;
|
923 | fdf9b3e8 | bellard | case 0x4083: /* stc.l Rm_BANK,@-Rn */ |
924 | fdf9b3e8 | bellard | gen_op_dec4_rN(REG(B11_8)); |
925 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
926 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(ALTREG(B6_4)); |
927 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
928 | fdf9b3e8 | bellard | return;
|
929 | fdf9b3e8 | bellard | } |
930 | fdf9b3e8 | bellard | |
931 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf0ff) { |
932 | fdf9b3e8 | bellard | case 0x0023: /* braf Rn */ |
933 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8)); |
934 | fdf9b3e8 | bellard | gen_op_braf_T0(ctx->pc + 4);
|
935 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
936 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
937 | fdf9b3e8 | bellard | return;
|
938 | fdf9b3e8 | bellard | case 0x0003: /* bsrf Rn */ |
939 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8)); |
940 | fdf9b3e8 | bellard | gen_op_bsrf_T0(ctx->pc + 4);
|
941 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
942 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
943 | fdf9b3e8 | bellard | return;
|
944 | fdf9b3e8 | bellard | case 0x4015: /* cmp/pl Rn */ |
945 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B11_8)); |
946 | fdf9b3e8 | bellard | gen_op_cmp_pl_T0(); |
947 | fdf9b3e8 | bellard | return;
|
948 | fdf9b3e8 | bellard | case 0x4011: /* cmp/pz Rn */ |
949 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B11_8)); |
950 | fdf9b3e8 | bellard | gen_op_cmp_pz_T0(); |
951 | fdf9b3e8 | bellard | return;
|
952 | fdf9b3e8 | bellard | case 0x4010: /* dt Rn */ |
953 | fdf9b3e8 | bellard | gen_op_dt_rN(REG(B11_8)); |
954 | fdf9b3e8 | bellard | return;
|
955 | fdf9b3e8 | bellard | case 0x402b: /* jmp @Rn */ |
956 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8)); |
957 | fdf9b3e8 | bellard | gen_op_jmp_T0(); |
958 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
959 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
960 | fdf9b3e8 | bellard | return;
|
961 | fdf9b3e8 | bellard | case 0x400b: /* jsr @Rn */ |
962 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8)); |
963 | fdf9b3e8 | bellard | gen_op_jsr_T0(ctx->pc + 4);
|
964 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
965 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
966 | fdf9b3e8 | bellard | return;
|
967 | fdf9b3e8 | bellard | #define LDST(reg,ldnum,ldpnum,ldop,stnum,stpnum,stop,extrald) \
|
968 | fdf9b3e8 | bellard | case ldnum: \
|
969 | fdf9b3e8 | bellard | gen_op_movl_rN_T0 (REG(B11_8)); \ |
970 | fdf9b3e8 | bellard | gen_op_##ldop##_T0_##reg (); \ |
971 | fdf9b3e8 | bellard | extrald \ |
972 | fdf9b3e8 | bellard | return; \
|
973 | fdf9b3e8 | bellard | case ldpnum: \
|
974 | fdf9b3e8 | bellard | gen_op_movl_rN_T0 (REG(B11_8)); \ |
975 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0 (ctx); \ |
976 | fdf9b3e8 | bellard | gen_op_inc4_rN (REG(B11_8)); \ |
977 | fdf9b3e8 | bellard | gen_op_##ldop##_T0_##reg (); \ |
978 | fdf9b3e8 | bellard | extrald \ |
979 | fdf9b3e8 | bellard | return; \
|
980 | fdf9b3e8 | bellard | case stnum: \
|
981 | fdf9b3e8 | bellard | gen_op_##stop##_##reg##_T0 (); \ |
982 | fdf9b3e8 | bellard | gen_op_movl_T0_rN (REG(B11_8)); \ |
983 | fdf9b3e8 | bellard | return; \
|
984 | fdf9b3e8 | bellard | case stpnum: \
|
985 | fdf9b3e8 | bellard | gen_op_##stop##_##reg##_T0 (); \ |
986 | fdf9b3e8 | bellard | gen_op_dec4_rN (REG(B11_8)); \ |
987 | fdf9b3e8 | bellard | gen_op_movl_rN_T1 (REG(B11_8)); \ |
988 | fdf9b3e8 | bellard | gen_op_stl_T0_T1 (ctx); \ |
989 | fdf9b3e8 | bellard | return;
|
990 | 823029f9 | ths | LDST(sr, 0x400e, 0x4007, ldc, 0x0002, 0x4003, stc, ctx->bstate = |
991 | 823029f9 | ths | BS_STOP;) |
992 | eda9b09b | bellard | LDST(gbr, 0x401e, 0x4017, ldc, 0x0012, 0x4013, stc,) |
993 | eda9b09b | bellard | LDST(vbr, 0x402e, 0x4027, ldc, 0x0022, 0x4023, stc,) |
994 | eda9b09b | bellard | LDST(ssr, 0x403e, 0x4037, ldc, 0x0032, 0x4033, stc,) |
995 | eda9b09b | bellard | LDST(spc, 0x404e, 0x4047, ldc, 0x0042, 0x4043, stc,) |
996 | eda9b09b | bellard | LDST(dbr, 0x40fa, 0x40f6, ldc, 0x00fa, 0x40f2, stc,) |
997 | eda9b09b | bellard | LDST(mach, 0x400a, 0x4006, lds, 0x000a, 0x4002, sts,) |
998 | eda9b09b | bellard | LDST(macl, 0x401a, 0x4016, lds, 0x001a, 0x4012, sts,) |
999 | eda9b09b | bellard | LDST(pr, 0x402a, 0x4026, lds, 0x002a, 0x4022, sts,) |
1000 | 8bf5a804 | ths | LDST(fpul, 0x405a, 0x4056, lds, 0x005a, 0x4052, sts,) |
1001 | 823029f9 | ths | LDST(fpscr, 0x406a, 0x4066, lds, 0x006a, 0x4062, sts, ctx->bstate = |
1002 | 823029f9 | ths | BS_STOP;) |
1003 | fdf9b3e8 | bellard | case 0x00c3: /* movca.l R0,@Rm */ |
1004 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
1005 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
1006 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
1007 | fdf9b3e8 | bellard | return;
|
1008 | fdf9b3e8 | bellard | case 0x0029: /* movt Rn */ |
1009 | fdf9b3e8 | bellard | gen_op_movt_rN(REG(B11_8)); |
1010 | fdf9b3e8 | bellard | return;
|
1011 | fdf9b3e8 | bellard | case 0x0093: /* ocbi @Rn */ |
1012 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B11_8)); |
1013 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
1014 | fdf9b3e8 | bellard | return;
|
1015 | 24988dc2 | aurel32 | case 0x00a3: /* ocbp @Rn */ |
1016 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B11_8)); |
1017 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
1018 | fdf9b3e8 | bellard | return;
|
1019 | fdf9b3e8 | bellard | case 0x00b3: /* ocbwb @Rn */ |
1020 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B11_8)); |
1021 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
1022 | fdf9b3e8 | bellard | return;
|
1023 | fdf9b3e8 | bellard | case 0x0083: /* pref @Rn */ |
1024 | fdf9b3e8 | bellard | return;
|
1025 | fdf9b3e8 | bellard | case 0x4024: /* rotcl Rn */ |
1026 | fdf9b3e8 | bellard | gen_op_rotcl_Rn(REG(B11_8)); |
1027 | fdf9b3e8 | bellard | return;
|
1028 | fdf9b3e8 | bellard | case 0x4025: /* rotcr Rn */ |
1029 | fdf9b3e8 | bellard | gen_op_rotcr_Rn(REG(B11_8)); |
1030 | fdf9b3e8 | bellard | return;
|
1031 | fdf9b3e8 | bellard | case 0x4004: /* rotl Rn */ |
1032 | fdf9b3e8 | bellard | gen_op_rotl_Rn(REG(B11_8)); |
1033 | fdf9b3e8 | bellard | return;
|
1034 | fdf9b3e8 | bellard | case 0x4005: /* rotr Rn */ |
1035 | fdf9b3e8 | bellard | gen_op_rotr_Rn(REG(B11_8)); |
1036 | fdf9b3e8 | bellard | return;
|
1037 | fdf9b3e8 | bellard | case 0x4000: /* shll Rn */ |
1038 | fdf9b3e8 | bellard | case 0x4020: /* shal Rn */ |
1039 | fdf9b3e8 | bellard | gen_op_shal_Rn(REG(B11_8)); |
1040 | fdf9b3e8 | bellard | return;
|
1041 | fdf9b3e8 | bellard | case 0x4021: /* shar Rn */ |
1042 | fdf9b3e8 | bellard | gen_op_shar_Rn(REG(B11_8)); |
1043 | fdf9b3e8 | bellard | return;
|
1044 | fdf9b3e8 | bellard | case 0x4001: /* shlr Rn */ |
1045 | fdf9b3e8 | bellard | gen_op_shlr_Rn(REG(B11_8)); |
1046 | fdf9b3e8 | bellard | return;
|
1047 | fdf9b3e8 | bellard | case 0x4008: /* shll2 Rn */ |
1048 | fdf9b3e8 | bellard | gen_op_shll2_Rn(REG(B11_8)); |
1049 | fdf9b3e8 | bellard | return;
|
1050 | fdf9b3e8 | bellard | case 0x4018: /* shll8 Rn */ |
1051 | fdf9b3e8 | bellard | gen_op_shll8_Rn(REG(B11_8)); |
1052 | fdf9b3e8 | bellard | return;
|
1053 | fdf9b3e8 | bellard | case 0x4028: /* shll16 Rn */ |
1054 | fdf9b3e8 | bellard | gen_op_shll16_Rn(REG(B11_8)); |
1055 | fdf9b3e8 | bellard | return;
|
1056 | fdf9b3e8 | bellard | case 0x4009: /* shlr2 Rn */ |
1057 | fdf9b3e8 | bellard | gen_op_shlr2_Rn(REG(B11_8)); |
1058 | fdf9b3e8 | bellard | return;
|
1059 | fdf9b3e8 | bellard | case 0x4019: /* shlr8 Rn */ |
1060 | fdf9b3e8 | bellard | gen_op_shlr8_Rn(REG(B11_8)); |
1061 | fdf9b3e8 | bellard | return;
|
1062 | fdf9b3e8 | bellard | case 0x4029: /* shlr16 Rn */ |
1063 | fdf9b3e8 | bellard | gen_op_shlr16_Rn(REG(B11_8)); |
1064 | fdf9b3e8 | bellard | return;
|
1065 | fdf9b3e8 | bellard | case 0x401b: /* tas.b @Rn */ |
1066 | fdf9b3e8 | bellard | gen_op_tasb_rN(REG(B11_8)); |
1067 | fdf9b3e8 | bellard | return;
|
1068 | e67888a7 | ths | case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ |
1069 | eda9b09b | bellard | gen_op_movl_fpul_FT0(); |
1070 | eda9b09b | bellard | gen_op_fmov_FT0_frN(FREG(B11_8)); |
1071 | eda9b09b | bellard | return;
|
1072 | e67888a7 | ths | case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ |
1073 | eda9b09b | bellard | gen_op_fmov_frN_FT0(FREG(B11_8)); |
1074 | eda9b09b | bellard | gen_op_movl_FT0_fpul(); |
1075 | eda9b09b | bellard | return;
|
1076 | e67888a7 | ths | case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */ |
1077 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
1078 | ea6cf6be | ths | if (ctx->opcode & 0x0100) |
1079 | ea6cf6be | ths | break; /* illegal instruction */ |
1080 | ea6cf6be | ths | gen_op_float_DT(); |
1081 | ea6cf6be | ths | gen_op_fmov_DT0_drN(DREG(B11_8)); |
1082 | ea6cf6be | ths | } |
1083 | ea6cf6be | ths | else {
|
1084 | ea6cf6be | ths | gen_op_float_FT(); |
1085 | ea6cf6be | ths | gen_op_fmov_FT0_frN(FREG(B11_8)); |
1086 | ea6cf6be | ths | } |
1087 | ea6cf6be | ths | return;
|
1088 | e67888a7 | ths | case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
1089 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
1090 | ea6cf6be | ths | if (ctx->opcode & 0x0100) |
1091 | ea6cf6be | ths | break; /* illegal instruction */ |
1092 | ea6cf6be | ths | gen_op_fmov_drN_DT0(DREG(B11_8)); |
1093 | ea6cf6be | ths | gen_op_ftrc_DT(); |
1094 | ea6cf6be | ths | } |
1095 | ea6cf6be | ths | else {
|
1096 | ea6cf6be | ths | gen_op_fmov_frN_FT0(FREG(B11_8)); |
1097 | ea6cf6be | ths | gen_op_ftrc_FT(); |
1098 | ea6cf6be | ths | } |
1099 | ea6cf6be | ths | return;
|
1100 | 24988dc2 | aurel32 | case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ |
1101 | 24988dc2 | aurel32 | gen_op_fneg_frN(FREG(B11_8)); |
1102 | 24988dc2 | aurel32 | return;
|
1103 | 24988dc2 | aurel32 | case 0xf05d: /* fabs FRn/DRn */ |
1104 | 24988dc2 | aurel32 | if (ctx->fpscr & FPSCR_PR) {
|
1105 | 24988dc2 | aurel32 | if (ctx->opcode & 0x0100) |
1106 | 24988dc2 | aurel32 | break; /* illegal instruction */ |
1107 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(DREG(B11_8)); |
1108 | 24988dc2 | aurel32 | gen_op_fabs_DT(); |
1109 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(DREG(B11_8)); |
1110 | 24988dc2 | aurel32 | } else {
|
1111 | 24988dc2 | aurel32 | gen_op_fmov_frN_FT0(FREG(B11_8)); |
1112 | 24988dc2 | aurel32 | gen_op_fabs_FT(); |
1113 | 24988dc2 | aurel32 | gen_op_fmov_FT0_frN(FREG(B11_8)); |
1114 | 24988dc2 | aurel32 | } |
1115 | 24988dc2 | aurel32 | return;
|
1116 | 24988dc2 | aurel32 | case 0xf06d: /* fsqrt FRn */ |
1117 | 24988dc2 | aurel32 | if (ctx->fpscr & FPSCR_PR) {
|
1118 | 24988dc2 | aurel32 | if (ctx->opcode & 0x0100) |
1119 | 24988dc2 | aurel32 | break; /* illegal instruction */ |
1120 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(FREG(B11_8)); |
1121 | 24988dc2 | aurel32 | gen_op_fsqrt_DT(); |
1122 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(FREG(B11_8)); |
1123 | 24988dc2 | aurel32 | } else {
|
1124 | 24988dc2 | aurel32 | gen_op_fmov_frN_FT0(FREG(B11_8)); |
1125 | 24988dc2 | aurel32 | gen_op_fsqrt_FT(); |
1126 | 24988dc2 | aurel32 | gen_op_fmov_FT0_frN(FREG(B11_8)); |
1127 | 24988dc2 | aurel32 | } |
1128 | 24988dc2 | aurel32 | return;
|
1129 | 24988dc2 | aurel32 | case 0xf07d: /* fsrra FRn */ |
1130 | 24988dc2 | aurel32 | break;
|
1131 | e67888a7 | ths | case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ |
1132 | ea6cf6be | ths | if (!(ctx->fpscr & FPSCR_PR)) {
|
1133 | ea6cf6be | ths | gen_op_movl_imm_T0(0);
|
1134 | ea6cf6be | ths | gen_op_fmov_T0_frN(FREG(B11_8)); |
1135 | ea6cf6be | ths | return;
|
1136 | ea6cf6be | ths | } |
1137 | ea6cf6be | ths | break;
|
1138 | e67888a7 | ths | case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ |
1139 | ea6cf6be | ths | if (!(ctx->fpscr & FPSCR_PR)) {
|
1140 | ea6cf6be | ths | gen_op_movl_imm_T0(0x3f800000);
|
1141 | ea6cf6be | ths | gen_op_fmov_T0_frN(FREG(B11_8)); |
1142 | ea6cf6be | ths | return;
|
1143 | ea6cf6be | ths | } |
1144 | ea6cf6be | ths | break;
|
1145 | 24988dc2 | aurel32 | case 0xf0ad: /* fcnvsd FPUL,DRn */ |
1146 | 24988dc2 | aurel32 | gen_op_movl_fpul_FT0(); |
1147 | 24988dc2 | aurel32 | gen_op_fcnvsd_FT_DT(); |
1148 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(DREG(B11_8)); |
1149 | 24988dc2 | aurel32 | return;
|
1150 | 24988dc2 | aurel32 | case 0xf0bd: /* fcnvds DRn,FPUL */ |
1151 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(DREG(B11_8)); |
1152 | 24988dc2 | aurel32 | gen_op_fcnvds_DT_FT(); |
1153 | 24988dc2 | aurel32 | gen_op_movl_FT0_fpul(); |
1154 | 24988dc2 | aurel32 | return;
|
1155 | fdf9b3e8 | bellard | } |
1156 | fdf9b3e8 | bellard | |
1157 | fdf9b3e8 | bellard | fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
|
1158 | fdf9b3e8 | bellard | ctx->opcode, ctx->pc); |
1159 | fdf9b3e8 | bellard | gen_op_raise_illegal_instruction(); |
1160 | 823029f9 | ths | ctx->bstate = BS_EXCP; |
1161 | 823029f9 | ths | } |
1162 | 823029f9 | ths | |
1163 | 823029f9 | ths | void decode_opc(DisasContext * ctx)
|
1164 | 823029f9 | ths | { |
1165 | 823029f9 | ths | uint32_t old_flags = ctx->flags; |
1166 | 823029f9 | ths | |
1167 | 823029f9 | ths | _decode_opc(ctx); |
1168 | 823029f9 | ths | |
1169 | 823029f9 | ths | if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
|
1170 | 823029f9 | ths | if (ctx->flags & DELAY_SLOT_CLEARME) {
|
1171 | 823029f9 | ths | gen_op_store_flags(0);
|
1172 | 823029f9 | ths | } |
1173 | 823029f9 | ths | ctx->flags = 0;
|
1174 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
1175 | 823029f9 | ths | if (old_flags & DELAY_SLOT_CONDITIONAL) {
|
1176 | 823029f9 | ths | gen_delayed_conditional_jump(ctx); |
1177 | 823029f9 | ths | } else if (old_flags & DELAY_SLOT) { |
1178 | 823029f9 | ths | gen_jump(ctx); |
1179 | 823029f9 | ths | } |
1180 | 823029f9 | ths | |
1181 | 823029f9 | ths | } |
1182 | fdf9b3e8 | bellard | } |
1183 | fdf9b3e8 | bellard | |
1184 | 820e00f2 | ths | static inline int |
1185 | 820e00f2 | ths | gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, |
1186 | 820e00f2 | ths | int search_pc)
|
1187 | fdf9b3e8 | bellard | { |
1188 | fdf9b3e8 | bellard | DisasContext ctx; |
1189 | fdf9b3e8 | bellard | target_ulong pc_start; |
1190 | fdf9b3e8 | bellard | static uint16_t *gen_opc_end;
|
1191 | 355fb23d | pbrook | int i, ii;
|
1192 | fdf9b3e8 | bellard | |
1193 | fdf9b3e8 | bellard | pc_start = tb->pc; |
1194 | fdf9b3e8 | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
1195 | fdf9b3e8 | bellard | ctx.pc = pc_start; |
1196 | 823029f9 | ths | ctx.flags = (uint32_t)tb->flags; |
1197 | 823029f9 | ths | ctx.bstate = BS_NONE; |
1198 | fdf9b3e8 | bellard | ctx.sr = env->sr; |
1199 | eda9b09b | bellard | ctx.fpscr = env->fpscr; |
1200 | fdf9b3e8 | bellard | ctx.memidx = (env->sr & SR_MD) ? 1 : 0; |
1201 | 9854bc46 | pbrook | /* We don't know if the delayed pc came from a dynamic or static branch,
|
1202 | 9854bc46 | pbrook | so assume it is a dynamic branch. */
|
1203 | 823029f9 | ths | ctx.delayed_pc = -1; /* use delayed pc from env pointer */ |
1204 | fdf9b3e8 | bellard | ctx.tb = tb; |
1205 | fdf9b3e8 | bellard | ctx.singlestep_enabled = env->singlestep_enabled; |
1206 | fdf9b3e8 | bellard | |
1207 | fdf9b3e8 | bellard | #ifdef DEBUG_DISAS
|
1208 | fdf9b3e8 | bellard | if (loglevel & CPU_LOG_TB_CPU) {
|
1209 | fdf9b3e8 | bellard | fprintf(logfile, |
1210 | fdf9b3e8 | bellard | "------------------------------------------------\n");
|
1211 | fdf9b3e8 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
1212 | fdf9b3e8 | bellard | } |
1213 | fdf9b3e8 | bellard | #endif
|
1214 | fdf9b3e8 | bellard | |
1215 | 355fb23d | pbrook | ii = -1;
|
1216 | 823029f9 | ths | while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
|
1217 | fdf9b3e8 | bellard | if (env->nb_breakpoints > 0) { |
1218 | fdf9b3e8 | bellard | for (i = 0; i < env->nb_breakpoints; i++) { |
1219 | fdf9b3e8 | bellard | if (ctx.pc == env->breakpoints[i]) {
|
1220 | fdf9b3e8 | bellard | /* We have hit a breakpoint - make sure PC is up-to-date */
|
1221 | fdf9b3e8 | bellard | gen_op_movl_imm_PC(ctx.pc); |
1222 | fdf9b3e8 | bellard | gen_op_debug(); |
1223 | 823029f9 | ths | ctx.bstate = BS_EXCP; |
1224 | fdf9b3e8 | bellard | break;
|
1225 | fdf9b3e8 | bellard | } |
1226 | fdf9b3e8 | bellard | } |
1227 | fdf9b3e8 | bellard | } |
1228 | 355fb23d | pbrook | if (search_pc) {
|
1229 | 355fb23d | pbrook | i = gen_opc_ptr - gen_opc_buf; |
1230 | 355fb23d | pbrook | if (ii < i) {
|
1231 | 355fb23d | pbrook | ii++; |
1232 | 355fb23d | pbrook | while (ii < i)
|
1233 | 355fb23d | pbrook | gen_opc_instr_start[ii++] = 0;
|
1234 | 355fb23d | pbrook | } |
1235 | 355fb23d | pbrook | gen_opc_pc[ii] = ctx.pc; |
1236 | 823029f9 | ths | gen_opc_hflags[ii] = ctx.flags; |
1237 | 355fb23d | pbrook | gen_opc_instr_start[ii] = 1;
|
1238 | 355fb23d | pbrook | } |
1239 | fdf9b3e8 | bellard | #if 0
|
1240 | fdf9b3e8 | bellard | fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
|
1241 | fdf9b3e8 | bellard | fflush(stderr);
|
1242 | fdf9b3e8 | bellard | #endif
|
1243 | fdf9b3e8 | bellard | ctx.opcode = lduw_code(ctx.pc); |
1244 | fdf9b3e8 | bellard | decode_opc(&ctx); |
1245 | fdf9b3e8 | bellard | ctx.pc += 2;
|
1246 | fdf9b3e8 | bellard | if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) |
1247 | fdf9b3e8 | bellard | break;
|
1248 | fdf9b3e8 | bellard | if (env->singlestep_enabled)
|
1249 | fdf9b3e8 | bellard | break;
|
1250 | fdf9b3e8 | bellard | #ifdef SH4_SINGLE_STEP
|
1251 | fdf9b3e8 | bellard | break;
|
1252 | fdf9b3e8 | bellard | #endif
|
1253 | fdf9b3e8 | bellard | } |
1254 | fdf9b3e8 | bellard | if (env->singlestep_enabled) {
|
1255 | 823029f9 | ths | gen_op_debug(); |
1256 | 823029f9 | ths | } else {
|
1257 | 823029f9 | ths | switch (ctx.bstate) {
|
1258 | 823029f9 | ths | case BS_STOP:
|
1259 | 823029f9 | ths | /* gen_op_interrupt_restart(); */
|
1260 | 823029f9 | ths | /* fall through */
|
1261 | 823029f9 | ths | case BS_NONE:
|
1262 | 823029f9 | ths | if (ctx.flags) {
|
1263 | 823029f9 | ths | gen_op_store_flags(ctx.flags | DELAY_SLOT_CLEARME); |
1264 | 823029f9 | ths | } |
1265 | 823029f9 | ths | gen_goto_tb(&ctx, 0, ctx.pc);
|
1266 | 823029f9 | ths | break;
|
1267 | 823029f9 | ths | case BS_EXCP:
|
1268 | 823029f9 | ths | /* gen_op_interrupt_restart(); */
|
1269 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
1270 | 823029f9 | ths | break;
|
1271 | 823029f9 | ths | case BS_BRANCH:
|
1272 | 823029f9 | ths | default:
|
1273 | 823029f9 | ths | break;
|
1274 | 823029f9 | ths | } |
1275 | fdf9b3e8 | bellard | } |
1276 | 823029f9 | ths | |
1277 | fdf9b3e8 | bellard | *gen_opc_ptr = INDEX_op_end; |
1278 | 355fb23d | pbrook | if (search_pc) {
|
1279 | 355fb23d | pbrook | i = gen_opc_ptr - gen_opc_buf; |
1280 | 355fb23d | pbrook | ii++; |
1281 | 355fb23d | pbrook | while (ii <= i)
|
1282 | 355fb23d | pbrook | gen_opc_instr_start[ii++] = 0;
|
1283 | 355fb23d | pbrook | } else {
|
1284 | 355fb23d | pbrook | tb->size = ctx.pc - pc_start; |
1285 | 355fb23d | pbrook | } |
1286 | fdf9b3e8 | bellard | |
1287 | fdf9b3e8 | bellard | #ifdef DEBUG_DISAS
|
1288 | fdf9b3e8 | bellard | #ifdef SH4_DEBUG_DISAS
|
1289 | fdf9b3e8 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM)
|
1290 | fdf9b3e8 | bellard | fprintf(logfile, "\n");
|
1291 | fdf9b3e8 | bellard | #endif
|
1292 | fdf9b3e8 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
1293 | fdf9b3e8 | bellard | fprintf(logfile, "IN:\n"); /* , lookup_symbol(pc_start)); */ |
1294 | fdf9b3e8 | bellard | target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
|
1295 | fdf9b3e8 | bellard | fprintf(logfile, "\n");
|
1296 | fdf9b3e8 | bellard | } |
1297 | fdf9b3e8 | bellard | #endif
|
1298 | fdf9b3e8 | bellard | return 0; |
1299 | fdf9b3e8 | bellard | } |
1300 | fdf9b3e8 | bellard | |
1301 | fdf9b3e8 | bellard | int gen_intermediate_code(CPUState * env, struct TranslationBlock *tb) |
1302 | fdf9b3e8 | bellard | { |
1303 | fdf9b3e8 | bellard | return gen_intermediate_code_internal(env, tb, 0); |
1304 | fdf9b3e8 | bellard | } |
1305 | fdf9b3e8 | bellard | |
1306 | fdf9b3e8 | bellard | int gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb) |
1307 | fdf9b3e8 | bellard | { |
1308 | fdf9b3e8 | bellard | return gen_intermediate_code_internal(env, tb, 1); |
1309 | fdf9b3e8 | bellard | } |
1310 | d2856f1a | aurel32 | |
1311 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
1312 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
1313 | d2856f1a | aurel32 | { |
1314 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
1315 | d2856f1a | aurel32 | env->flags = gen_opc_hflags[pc_pos]; |
1316 | d2856f1a | aurel32 | } |