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/*
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 * i386 virtual CPU header
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#ifndef CPU_I386_H
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#define CPU_I386_H
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#include "config.h"
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#ifdef TARGET_X86_64
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#define TARGET_LONG_BITS 64
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#else
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#define TARGET_LONG_BITS 32
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#endif
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/* target supports implicit self modifying code */
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#define TARGET_HAS_SMC
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/* support for self modifying code even if the modified instruction is
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   close to the modifying instruction */
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#define TARGET_HAS_PRECISE_SMC
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#define TARGET_HAS_ICE 1
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#ifdef TARGET_X86_64
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#define ELF_MACHINE        EM_X86_64
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#else
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#define ELF_MACHINE        EM_386
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#endif
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#include "cpu-defs.h"
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#include "softfloat.h"
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#define R_EAX 0
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#define R_ECX 1
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#define R_EDX 2
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#define R_EBX 3
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#define R_ESP 4
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#define R_EBP 5
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#define R_ESI 6
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#define R_EDI 7
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#define R_AL 0
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#define R_CL 1
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#define R_DL 2
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#define R_BL 3
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#define R_AH 4
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#define R_CH 5
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#define R_DH 6
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#define R_BH 7
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#define R_ES 0
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#define R_CS 1
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#define R_SS 2
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#define R_DS 3
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#define R_FS 4
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#define R_GS 5
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/* segment descriptor fields */
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#define DESC_G_MASK     (1 << 23)
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#define DESC_B_SHIFT    22
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#define DESC_B_MASK     (1 << DESC_B_SHIFT)
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#define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
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#define DESC_L_MASK     (1 << DESC_L_SHIFT)
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#define DESC_AVL_MASK   (1 << 20)
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#define DESC_P_MASK     (1 << 15)
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#define DESC_DPL_SHIFT  13
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#define DESC_DPL_MASK   (1 << DESC_DPL_SHIFT)
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#define DESC_S_MASK     (1 << 12)
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#define DESC_TYPE_SHIFT 8
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#define DESC_A_MASK     (1 << 8)
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#define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
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#define DESC_C_MASK     (1 << 10) /* code: conforming */
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#define DESC_R_MASK     (1 << 9)  /* code: readable */
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#define DESC_E_MASK     (1 << 10) /* data: expansion direction */
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#define DESC_W_MASK     (1 << 9)  /* data: writable */
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#define DESC_TSS_BUSY_MASK (1 << 9)
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/* eflags masks */
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#define CC_C           0x0001
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#define CC_P         0x0004
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#define CC_A        0x0010
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#define CC_Z        0x0040
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#define CC_S    0x0080
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#define CC_O    0x0800
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#define TF_SHIFT   8
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#define IOPL_SHIFT 12
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#define VM_SHIFT   17
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#define TF_MASK                 0x00000100
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#define IF_MASK                 0x00000200
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#define DF_MASK                 0x00000400
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#define IOPL_MASK                0x00003000
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#define NT_MASK                         0x00004000
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#define RF_MASK                        0x00010000
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#define VM_MASK                        0x00020000
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#define AC_MASK                        0x00040000
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#define VIF_MASK                0x00080000
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#define VIP_MASK                0x00100000
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#define ID_MASK                 0x00200000
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/* hidden flags - used internally by qemu to represent additional cpu
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   states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
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   using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
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   with eflags. */
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/* current cpl */
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#define HF_CPL_SHIFT         0
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/* true if soft mmu is being used */
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#define HF_SOFTMMU_SHIFT     2
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/* true if hardware interrupts must be disabled for next instruction */
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#define HF_INHIBIT_IRQ_SHIFT 3
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/* 16 or 32 segments */
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#define HF_CS32_SHIFT        4
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#define HF_SS32_SHIFT        5
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/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
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#define HF_ADDSEG_SHIFT      6
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/* copy of CR0.PE (protected mode) */
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#define HF_PE_SHIFT          7
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#define HF_TF_SHIFT          8 /* must be same as eflags */
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#define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
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#define HF_EM_SHIFT         10
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#define HF_TS_SHIFT         11
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#define HF_IOPL_SHIFT       12 /* must be same as eflags */
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#define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
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#define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
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#define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
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#define HF_VM_SHIFT         17 /* must be same as eflags */
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#define HF_SMM_SHIFT        19 /* CPU in SMM mode */
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#define HF_GIF_SHIFT        20 /* if set CPU takes interrupts */
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#define HF_HIF_SHIFT        21 /* shadow copy of IF_MASK when in SVM */
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#define HF_NMI_SHIFT        22 /* CPU serving NMI */
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#define HF_SVME_SHIFT       23 /* SVME enabled (copy of EFER.SVME */
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#define HF_SVMI_SHIFT       24 /* SVM intercepts are active */
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#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
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#define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
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#define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
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#define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
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#define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
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#define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
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#define HF_PE_MASK           (1 << HF_PE_SHIFT)
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#define HF_TF_MASK           (1 << HF_TF_SHIFT)
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#define HF_MP_MASK           (1 << HF_MP_SHIFT)
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#define HF_EM_MASK           (1 << HF_EM_SHIFT)
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#define HF_TS_MASK           (1 << HF_TS_SHIFT)
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#define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
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#define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
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#define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
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#define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
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#define HF_GIF_MASK          (1 << HF_GIF_SHIFT)
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#define HF_HIF_MASK          (1 << HF_HIF_SHIFT)
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#define HF_NMI_MASK          (1 << HF_NMI_SHIFT)
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#define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
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#define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
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#define CR0_PE_MASK  (1 << 0)
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#define CR0_MP_MASK  (1 << 1)
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#define CR0_EM_MASK  (1 << 2)
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#define CR0_TS_MASK  (1 << 3)
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#define CR0_ET_MASK  (1 << 4)
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#define CR0_NE_MASK  (1 << 5)
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#define CR0_WP_MASK  (1 << 16)
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#define CR0_AM_MASK  (1 << 18)
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#define CR0_PG_MASK  (1 << 31)
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#define CR4_VME_MASK  (1 << 0)
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#define CR4_PVI_MASK  (1 << 1)
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#define CR4_TSD_MASK  (1 << 2)
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#define CR4_DE_MASK   (1 << 3)
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#define CR4_PSE_MASK  (1 << 4)
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#define CR4_PAE_MASK  (1 << 5)
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#define CR4_PGE_MASK  (1 << 7)
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#define CR4_PCE_MASK  (1 << 8)
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#define CR4_OSFXSR_MASK (1 << 9)
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#define CR4_OSXMMEXCPT_MASK  (1 << 10)
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#define PG_PRESENT_BIT        0
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#define PG_RW_BIT        1
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#define PG_USER_BIT        2
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#define PG_PWT_BIT        3
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#define PG_PCD_BIT        4
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#define PG_ACCESSED_BIT        5
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#define PG_DIRTY_BIT        6
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#define PG_PSE_BIT        7
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#define PG_GLOBAL_BIT        8
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#define PG_NX_BIT        63
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#define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
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#define PG_RW_MASK         (1 << PG_RW_BIT)
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#define PG_USER_MASK         (1 << PG_USER_BIT)
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#define PG_PWT_MASK         (1 << PG_PWT_BIT)
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#define PG_PCD_MASK         (1 << PG_PCD_BIT)
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#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
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#define PG_DIRTY_MASK         (1 << PG_DIRTY_BIT)
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#define PG_PSE_MASK         (1 << PG_PSE_BIT)
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#define PG_GLOBAL_MASK         (1 << PG_GLOBAL_BIT)
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#define PG_NX_MASK         (1LL << PG_NX_BIT)
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#define PG_ERROR_W_BIT     1
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#define PG_ERROR_P_MASK    0x01
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#define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
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#define PG_ERROR_U_MASK    0x04
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#define PG_ERROR_RSVD_MASK 0x08
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#define PG_ERROR_I_D_MASK  0x10
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#define MSR_IA32_APICBASE               0x1b
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#define MSR_IA32_APICBASE_BSP           (1<<8)
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#define MSR_IA32_APICBASE_ENABLE        (1<<11)
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#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
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#define MSR_IA32_SYSENTER_CS            0x174
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#define MSR_IA32_SYSENTER_ESP           0x175
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#define MSR_IA32_SYSENTER_EIP           0x176
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#define MSR_MCG_CAP                     0x179
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#define MSR_MCG_STATUS                  0x17a
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#define MSR_MCG_CTL                     0x17b
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#define MSR_PAT                         0x277
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#define MSR_EFER                        0xc0000080
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#define MSR_EFER_SCE   (1 << 0)
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#define MSR_EFER_LME   (1 << 8)
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#define MSR_EFER_LMA   (1 << 10)
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#define MSR_EFER_NXE   (1 << 11)
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#define MSR_EFER_SVME  (1 << 12)
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#define MSR_EFER_FFXSR (1 << 14)
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#define MSR_STAR                        0xc0000081
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#define MSR_LSTAR                       0xc0000082
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#define MSR_CSTAR                       0xc0000083
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#define MSR_FMASK                       0xc0000084
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#define MSR_FSBASE                      0xc0000100
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#define MSR_GSBASE                      0xc0000101
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#define MSR_KERNELGSBASE                0xc0000102
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#define MSR_VM_HSAVE_PA                 0xc0010117
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/* cpuid_features bits */
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#define CPUID_FP87 (1 << 0)
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#define CPUID_VME  (1 << 1)
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#define CPUID_DE   (1 << 2)
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#define CPUID_PSE  (1 << 3)
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#define CPUID_TSC  (1 << 4)
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#define CPUID_MSR  (1 << 5)
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#define CPUID_PAE  (1 << 6)
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#define CPUID_MCE  (1 << 7)
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#define CPUID_CX8  (1 << 8)
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#define CPUID_APIC (1 << 9)
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#define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
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#define CPUID_MTRR (1 << 12)
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#define CPUID_PGE  (1 << 13)
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#define CPUID_MCA  (1 << 14)
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#define CPUID_CMOV (1 << 15)
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#define CPUID_PAT  (1 << 16)
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#define CPUID_PSE36   (1 << 17)
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#define CPUID_PN   (1 << 18)
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#define CPUID_CLFLUSH (1 << 19)
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#define CPUID_DTS (1 << 21)
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#define CPUID_ACPI (1 << 22)
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#define CPUID_MMX  (1 << 23)
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#define CPUID_FXSR (1 << 24)
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#define CPUID_SSE  (1 << 25)
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#define CPUID_SSE2 (1 << 26)
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#define CPUID_SS (1 << 27)
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#define CPUID_HT (1 << 28)
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#define CPUID_TM (1 << 29)
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#define CPUID_IA64 (1 << 30)
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#define CPUID_PBE (1 << 31)
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#define CPUID_EXT_SSE3     (1 << 0)
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#define CPUID_EXT_MONITOR  (1 << 3)
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#define CPUID_EXT_DSCPL    (1 << 4)
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#define CPUID_EXT_VMX      (1 << 5)
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#define CPUID_EXT_SMX      (1 << 6)
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#define CPUID_EXT_EST      (1 << 7)
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#define CPUID_EXT_TM2      (1 << 8)
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#define CPUID_EXT_SSSE3    (1 << 9)
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#define CPUID_EXT_CID      (1 << 10)
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#define CPUID_EXT_CX16     (1 << 13)
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#define CPUID_EXT_XTPR     (1 << 14)
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#define CPUID_EXT_DCA      (1 << 17)
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#define CPUID_EXT_POPCNT   (1 << 22)
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#define CPUID_EXT2_SYSCALL (1 << 11)
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#define CPUID_EXT2_MP      (1 << 19)
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#define CPUID_EXT2_NX      (1 << 20)
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#define CPUID_EXT2_MMXEXT  (1 << 22)
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#define CPUID_EXT2_FFXSR   (1 << 25)
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#define CPUID_EXT2_PDPE1GB (1 << 26)
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#define CPUID_EXT2_RDTSCP  (1 << 27)
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#define CPUID_EXT2_LM      (1 << 29)
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#define CPUID_EXT2_3DNOWEXT (1 << 30)
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#define CPUID_EXT2_3DNOW   (1 << 31)
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#define CPUID_EXT3_LAHF_LM (1 << 0)
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#define CPUID_EXT3_CMP_LEG (1 << 1)
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#define CPUID_EXT3_SVM     (1 << 2)
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#define CPUID_EXT3_EXTAPIC (1 << 3)
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#define CPUID_EXT3_CR8LEG  (1 << 4)
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#define CPUID_EXT3_ABM     (1 << 5)
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#define CPUID_EXT3_SSE4A   (1 << 6)
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#define CPUID_EXT3_MISALIGNSSE (1 << 7)
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#define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
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#define CPUID_EXT3_OSVW    (1 << 9)
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#define CPUID_EXT3_IBS     (1 << 10)
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#define CPUID_EXT3_SKINIT  (1 << 12)
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#define EXCP00_DIVZ        0
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#define EXCP01_SSTP        1
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#define EXCP02_NMI        2
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#define EXCP03_INT3        3
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#define EXCP04_INTO        4
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#define EXCP05_BOUND        5
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#define EXCP06_ILLOP        6
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#define EXCP07_PREX        7
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#define EXCP08_DBLE        8
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#define EXCP09_XERR        9
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#define EXCP0A_TSS        10
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#define EXCP0B_NOSEG        11
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#define EXCP0C_STACK        12
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#define EXCP0D_GPF        13
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#define EXCP0E_PAGE        14
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#define EXCP10_COPR        16
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#define EXCP11_ALGN        17
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#define EXCP12_MCHK        18
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#define EXCP_SYSCALL    0x100 /* only happens in user only emulation
350
                                 for syscall instruction */
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enum {
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    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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    CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */
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    CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
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    CC_OP_MULW,
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    CC_OP_MULL,
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    CC_OP_MULQ,
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    CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_ADDW,
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    CC_OP_ADDL,
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    CC_OP_ADDQ,
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    CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_ADCW,
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    CC_OP_ADCL,
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    CC_OP_ADCQ,
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    CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_SUBW,
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    CC_OP_SUBL,
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    CC_OP_SUBQ,
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    CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_SBBW,
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    CC_OP_SBBL,
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    CC_OP_SBBQ,
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    CC_OP_LOGICB, /* modify all flags, CC_DST = res */
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    CC_OP_LOGICW,
383
    CC_OP_LOGICL,
384
    CC_OP_LOGICQ,
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    CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
387
    CC_OP_INCW,
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    CC_OP_INCL,
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    CC_OP_INCQ,
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    CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
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    CC_OP_DECW,
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    CC_OP_DECL,
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    CC_OP_DECQ,
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    CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
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    CC_OP_SHLW,
398
    CC_OP_SHLL,
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    CC_OP_SHLQ,
400

    
401
    CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
402
    CC_OP_SARW,
403
    CC_OP_SARL,
404
    CC_OP_SARQ,
405

    
406
    CC_OP_NB,
407
};
408

    
409
#ifdef FLOATX80
410
#define USE_X86LDOUBLE
411
#endif
412

    
413
#ifdef USE_X86LDOUBLE
414
typedef floatx80 CPU86_LDouble;
415
#else
416
typedef float64 CPU86_LDouble;
417
#endif
418

    
419
typedef struct SegmentCache {
420
    uint32_t selector;
421
    target_ulong base;
422
    uint32_t limit;
423
    uint32_t flags;
424
} SegmentCache;
425

    
426
typedef union {
427
    uint8_t _b[16];
428
    uint16_t _w[8];
429
    uint32_t _l[4];
430
    uint64_t _q[2];
431
    float32 _s[4];
432
    float64 _d[2];
433
} XMMReg;
434

    
435
typedef union {
436
    uint8_t _b[8];
437
    uint16_t _w[4];
438
    uint32_t _l[2];
439
    float32 _s[2];
440
    uint64_t q;
441
} MMXReg;
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#ifdef WORDS_BIGENDIAN
444
#define XMM_B(n) _b[15 - (n)]
445
#define XMM_W(n) _w[7 - (n)]
446
#define XMM_L(n) _l[3 - (n)]
447
#define XMM_S(n) _s[3 - (n)]
448
#define XMM_Q(n) _q[1 - (n)]
449
#define XMM_D(n) _d[1 - (n)]
450

    
451
#define MMX_B(n) _b[7 - (n)]
452
#define MMX_W(n) _w[3 - (n)]
453
#define MMX_L(n) _l[1 - (n)]
454
#define MMX_S(n) _s[1 - (n)]
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#else
456
#define XMM_B(n) _b[n]
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#define XMM_W(n) _w[n]
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#define XMM_L(n) _l[n]
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#define XMM_S(n) _s[n]
460
#define XMM_Q(n) _q[n]
461
#define XMM_D(n) _d[n]
462

    
463
#define MMX_B(n) _b[n]
464
#define MMX_W(n) _w[n]
465
#define MMX_L(n) _l[n]
466
#define MMX_S(n) _s[n]
467
#endif
468
#define MMX_Q(n) q
469

    
470
#ifdef TARGET_X86_64
471
#define CPU_NB_REGS 16
472
#else
473
#define CPU_NB_REGS 8
474
#endif
475

    
476
#define NB_MMU_MODES 2
477

    
478
typedef struct CPUX86State {
479
    /* standard registers */
480
    target_ulong regs[CPU_NB_REGS];
481
    target_ulong eip;
482
    target_ulong eflags; /* eflags register. During CPU emulation, CC
483
                        flags and DF are set to zero because they are
484
                        stored elsewhere */
485

    
486
    /* emulator internal eflags handling */
487
    target_ulong cc_src;
488
    target_ulong cc_dst;
489
    uint32_t cc_op;
490
    int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
491
    uint32_t hflags; /* hidden flags, see HF_xxx constants */
492

    
493
    /* segments */
494
    SegmentCache segs[6]; /* selector values */
495
    SegmentCache ldt;
496
    SegmentCache tr;
497
    SegmentCache gdt; /* only base and limit are used */
498
    SegmentCache idt; /* only base and limit are used */
499

    
500
    target_ulong cr[9]; /* NOTE: cr1, cr5-7 are unused */
501
    uint64_t a20_mask;
502

    
503
    /* FPU state */
504
    unsigned int fpstt; /* top of stack index */
505
    unsigned int fpus;
506
    unsigned int fpuc;
507
    uint8_t fptags[8];   /* 0 = valid, 1 = empty */
508
    union {
509
#ifdef USE_X86LDOUBLE
510
        CPU86_LDouble d __attribute__((aligned(16)));
511
#else
512
        CPU86_LDouble d;
513
#endif
514
        MMXReg mmx;
515
    } fpregs[8];
516

    
517
    /* emulator internal variables */
518
    float_status fp_status;
519
    CPU86_LDouble ft0;
520

    
521
    float_status mmx_status; /* for 3DNow! float ops */
522
    float_status sse_status;
523
    uint32_t mxcsr;
524
    XMMReg xmm_regs[CPU_NB_REGS];
525
    XMMReg xmm_t0;
526
    MMXReg mmx_t0;
527
    target_ulong cc_tmp; /* temporary for rcr/rcl */
528

    
529
    /* sysenter registers */
530
    uint32_t sysenter_cs;
531
    uint32_t sysenter_esp;
532
    uint32_t sysenter_eip;
533
    uint64_t efer;
534
    uint64_t star;
535

    
536
    target_phys_addr_t vm_hsave;
537
    target_phys_addr_t vm_vmcb;
538
    uint64_t intercept;
539
    uint16_t intercept_cr_read;
540
    uint16_t intercept_cr_write;
541
    uint16_t intercept_dr_read;
542
    uint16_t intercept_dr_write;
543
    uint32_t intercept_exceptions;
544

    
545
#ifdef TARGET_X86_64
546
    target_ulong lstar;
547
    target_ulong cstar;
548
    target_ulong fmask;
549
    target_ulong kernelgsbase;
550
#endif
551

    
552
    uint64_t pat;
553

    
554
    /* exception/interrupt handling */
555
    int error_code;
556
    int exception_is_int;
557
    target_ulong exception_next_eip;
558
    target_ulong dr[8]; /* debug registers */
559
    uint32_t smbase;
560
    int interrupt_request;
561
    int user_mode_only; /* user mode only simulation */
562
    int old_exception;  /* exception in flight */
563

    
564
    CPU_COMMON
565

    
566
    /* processor features (e.g. for CPUID insn) */
567
    uint32_t cpuid_level;
568
    uint32_t cpuid_vendor1;
569
    uint32_t cpuid_vendor2;
570
    uint32_t cpuid_vendor3;
571
    uint32_t cpuid_version;
572
    uint32_t cpuid_features;
573
    uint32_t cpuid_ext_features;
574
    uint32_t cpuid_xlevel;
575
    uint32_t cpuid_model[12];
576
    uint32_t cpuid_ext2_features;
577
    uint32_t cpuid_ext3_features;
578
    uint32_t cpuid_apic_id;
579

    
580
#ifdef USE_KQEMU
581
    int kqemu_enabled;
582
    int last_io_time;
583
#endif
584
    /* in order to simplify APIC support, we leave this pointer to the
585
       user */
586
    struct APICState *apic_state;
587
} CPUX86State;
588

    
589
CPUX86State *cpu_x86_init(const char *cpu_model);
590
int cpu_x86_exec(CPUX86State *s);
591
void cpu_x86_close(CPUX86State *s);
592
void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
593
                                                 ...));
594
int cpu_get_pic_interrupt(CPUX86State *s);
595
/* MSDOS compatibility mode FPU exception support */
596
void cpu_set_ferr(CPUX86State *s);
597

    
598
/* this function must always be used to load data in the segment
599
   cache: it synchronizes the hflags with the segment cache values */
600
static inline void cpu_x86_load_seg_cache(CPUX86State *env,
601
                                          int seg_reg, unsigned int selector,
602
                                          target_ulong base,
603
                                          unsigned int limit,
604
                                          unsigned int flags)
605
{
606
    SegmentCache *sc;
607
    unsigned int new_hflags;
608

    
609
    sc = &env->segs[seg_reg];
610
    sc->selector = selector;
611
    sc->base = base;
612
    sc->limit = limit;
613
    sc->flags = flags;
614

    
615
    /* update the hidden flags */
616
    {
617
        if (seg_reg == R_CS) {
618
#ifdef TARGET_X86_64
619
            if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
620
                /* long mode */
621
                env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
622
                env->hflags &= ~(HF_ADDSEG_MASK);
623
            } else
624
#endif
625
            {
626
                /* legacy / compatibility case */
627
                new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
628
                    >> (DESC_B_SHIFT - HF_CS32_SHIFT);
629
                env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
630
                    new_hflags;
631
            }
632
        }
633
        new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
634
            >> (DESC_B_SHIFT - HF_SS32_SHIFT);
635
        if (env->hflags & HF_CS64_MASK) {
636
            /* zero base assumed for DS, ES and SS in long mode */
637
        } else if (!(env->cr[0] & CR0_PE_MASK) ||
638
                   (env->eflags & VM_MASK) ||
639
                   !(env->hflags & HF_CS32_MASK)) {
640
            /* XXX: try to avoid this test. The problem comes from the
641
               fact that is real mode or vm86 mode we only modify the
642
               'base' and 'selector' fields of the segment cache to go
643
               faster. A solution may be to force addseg to one in
644
               translate-i386.c. */
645
            new_hflags |= HF_ADDSEG_MASK;
646
        } else {
647
            new_hflags |= ((env->segs[R_DS].base |
648
                            env->segs[R_ES].base |
649
                            env->segs[R_SS].base) != 0) <<
650
                HF_ADDSEG_SHIFT;
651
        }
652
        env->hflags = (env->hflags &
653
                       ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
654
    }
655
}
656

    
657
/* wrapper, just in case memory mappings must be changed */
658
static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
659
{
660
#if HF_CPL_MASK == 3
661
    s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
662
#else
663
#error HF_CPL_MASK is hardcoded
664
#endif
665
}
666

    
667
/* used for debug or cpu save/restore */
668
void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
669
CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
670

    
671
/* the following helpers are only usable in user mode simulation as
672
   they can trigger unexpected exceptions */
673
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
674
void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
675
void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
676

    
677
/* you can call this signal handler from your SIGBUS and SIGSEGV
678
   signal handlers to inform the virtual CPU of exceptions. non zero
679
   is returned if the signal was handled by the virtual CPU.  */
680
int cpu_x86_signal_handler(int host_signum, void *pinfo,
681
                           void *puc);
682
void cpu_x86_set_a20(CPUX86State *env, int a20_state);
683

    
684
uint64_t cpu_get_tsc(CPUX86State *env);
685

    
686
void cpu_set_apic_base(CPUX86State *env, uint64_t val);
687
uint64_t cpu_get_apic_base(CPUX86State *env);
688
void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
689
#ifndef NO_CPU_IO_DEFS
690
uint8_t cpu_get_apic_tpr(CPUX86State *env);
691
#endif
692
void cpu_smm_update(CPUX86State *env);
693

    
694
/* will be suppressed */
695
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
696

    
697
/* used to debug */
698
#define X86_DUMP_FPU  0x0001 /* dump FPU state too */
699
#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
700

    
701
#ifdef USE_KQEMU
702
static inline int cpu_get_time_fast(void)
703
{
704
    int low, high;
705
    asm volatile("rdtsc" : "=a" (low), "=d" (high));
706
    return low;
707
}
708
#endif
709

    
710
#define TARGET_PAGE_BITS 12
711

    
712
#define CPUState CPUX86State
713
#define cpu_init cpu_x86_init
714
#define cpu_exec cpu_x86_exec
715
#define cpu_gen_code cpu_x86_gen_code
716
#define cpu_signal_handler cpu_x86_signal_handler
717
#define cpu_list x86_cpu_list
718

    
719
/* MMU modes definitions */
720
#define MMU_MODE0_SUFFIX _kernel
721
#define MMU_MODE1_SUFFIX _user
722
#define MMU_USER_IDX 1
723
static inline int cpu_mmu_index (CPUState *env)
724
{
725
    return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
726
}
727

    
728
void optimize_flags_init(void);
729

    
730
typedef struct CCTable {
731
    int (*compute_all)(void); /* return all the flags */
732
    int (*compute_c)(void);  /* return the C flag */
733
} CCTable;
734

    
735
extern CCTable cc_table[];
736

    
737
#if defined(CONFIG_USER_ONLY)
738
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
739
{
740
    if (newsp)
741
        env->regs[R_ESP] = newsp;
742
    env->regs[R_EAX] = 0;
743
}
744
#endif
745

    
746
#include "cpu-all.h"
747

    
748
#include "svm.h"
749

    
750
#endif /* CPU_I386_H */