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#if !defined (__MIPS_CPU_H__)
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#define __MIPS_CPU_H__
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#define TARGET_HAS_ICE 1
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#define ELF_MACHINE        EM_MIPS
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#include "config.h"
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#include "mips-defs.h"
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#include "cpu-defs.h"
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#include "softfloat.h"
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// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
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// XXX: move that elsewhere
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#if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
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typedef unsigned char           uint_fast8_t;
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typedef unsigned int            uint_fast16_t;
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#endif
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struct CPUMIPSState;
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typedef struct r4k_tlb_t r4k_tlb_t;
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struct r4k_tlb_t {
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    target_ulong VPN;
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    uint32_t PageMask;
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    uint_fast8_t ASID;
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    uint_fast16_t G:1;
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    uint_fast16_t C0:3;
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    uint_fast16_t C1:3;
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    uint_fast16_t V0:1;
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    uint_fast16_t V1:1;
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    uint_fast16_t D0:1;
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    uint_fast16_t D1:1;
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    target_ulong PFN[2];
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};
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typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
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struct CPUMIPSTLBContext {
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    uint32_t nb_tlb;
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    uint32_t tlb_in_use;
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    int (*map_address) (struct CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
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    void (*do_tlbwi) (void);
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    void (*do_tlbwr) (void);
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    void (*do_tlbp) (void);
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    void (*do_tlbr) (void);
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    union {
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        struct {
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            r4k_tlb_t tlb[MIPS_TLB_MAX];
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        } r4k;
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    } mmu;
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};
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typedef union fpr_t fpr_t;
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union fpr_t {
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    float64  fd;   /* ieee double precision */
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    float32  fs[2];/* ieee single precision */
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    uint64_t d;    /* binary double fixed-point */
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    uint32_t w[2]; /* binary single fixed-point */
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};
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/* define FP_ENDIAN_IDX to access the same location
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 * in the fpr_t union regardless of the host endianess
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 */
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#if defined(WORDS_BIGENDIAN)
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#  define FP_ENDIAN_IDX 1
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#else
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#  define FP_ENDIAN_IDX 0
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#endif
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typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
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struct CPUMIPSFPUContext {
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    /* Floating point registers */
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    fpr_t fpr[32];
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#ifndef USE_HOST_FLOAT_REGS
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    fpr_t ft0;
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    fpr_t ft1;
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    fpr_t ft2;
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#endif
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    float_status fp_status;
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    /* fpu implementation/revision register (fir) */
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    uint32_t fcr0;
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#define FCR0_F64 22
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#define FCR0_L 21
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#define FCR0_W 20
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#define FCR0_3D 19
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#define FCR0_PS 18
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#define FCR0_D 17
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#define FCR0_S 16
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#define FCR0_PRID 8
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#define FCR0_REV 0
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    /* fcsr */
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    uint32_t fcr31;
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#define SET_FP_COND(num,env)     do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
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#define CLEAR_FP_COND(num,env)   do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
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#define GET_FP_COND(env)         ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1))
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#define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
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#define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
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#define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
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#define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
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#define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
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#define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
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#define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
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#define FP_INEXACT        1
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#define FP_UNDERFLOW      2
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#define FP_OVERFLOW       4
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#define FP_DIV0           8
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#define FP_INVALID        16
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#define FP_UNIMPLEMENTED  32
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};
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#define NB_MMU_MODES 3
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typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
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struct CPUMIPSMVPContext {
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    int32_t CP0_MVPControl;
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#define CP0MVPCo_CPA        3
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#define CP0MVPCo_STLB        2
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#define CP0MVPCo_VPC        1
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#define CP0MVPCo_EVP        0
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    int32_t CP0_MVPConf0;
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#define CP0MVPC0_M        31
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#define CP0MVPC0_TLBS        29
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#define CP0MVPC0_GS        28
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#define CP0MVPC0_PCP        27
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#define CP0MVPC0_PTLBE        16
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#define CP0MVPC0_TCA        15
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#define CP0MVPC0_PVPE        10
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#define CP0MVPC0_PTC        0
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    int32_t CP0_MVPConf1;
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#define CP0MVPC1_CIM        31
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#define CP0MVPC1_CIF        30
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#define CP0MVPC1_PCX        20
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#define CP0MVPC1_PCP2        10
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#define CP0MVPC1_PCP1        0
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};
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typedef struct mips_def_t mips_def_t;
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#define MIPS_SHADOW_SET_MAX 16
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#define MIPS_TC_MAX 5
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#define MIPS_DSP_ACC 4
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typedef struct CPUMIPSState CPUMIPSState;
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struct CPUMIPSState {
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    /* General integer registers */
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    target_ulong gpr[MIPS_SHADOW_SET_MAX][32];
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    /* Special registers */
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    target_ulong PC[MIPS_TC_MAX];
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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    target_ulong t0;
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    target_ulong t1;
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#endif
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    target_ulong HI[MIPS_TC_MAX][MIPS_DSP_ACC];
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    target_ulong LO[MIPS_TC_MAX][MIPS_DSP_ACC];
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    target_ulong ACX[MIPS_TC_MAX][MIPS_DSP_ACC];
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    target_ulong DSPControl[MIPS_TC_MAX];
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    CPUMIPSMVPContext *mvp;
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    CPUMIPSTLBContext *tlb;
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    CPUMIPSFPUContext *fpu;
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    uint32_t current_tc;
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    target_ulong *current_tc_gprs;
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    target_ulong *current_tc_hi;
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    uint32_t SEGBITS;
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    target_ulong SEGMask;
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    uint32_t PABITS;
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    target_ulong PAMask;
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    int32_t CP0_Index;
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    /* CP0_MVP* are per MVP registers. */
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    int32_t CP0_Random;
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    int32_t CP0_VPEControl;
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#define CP0VPECo_YSI        21
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#define CP0VPECo_GSI        20
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#define CP0VPECo_EXCPT        16
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#define CP0VPECo_TE        15
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#define CP0VPECo_TargTC        0
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    int32_t CP0_VPEConf0;
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#define CP0VPEC0_M        31
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#define CP0VPEC0_XTC        21
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#define CP0VPEC0_TCS        19
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#define CP0VPEC0_SCS        18
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#define CP0VPEC0_DSC        17
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#define CP0VPEC0_ICS        16
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#define CP0VPEC0_MVP        1
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#define CP0VPEC0_VPA        0
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    int32_t CP0_VPEConf1;
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#define CP0VPEC1_NCX        20
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#define CP0VPEC1_NCP2        10
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#define CP0VPEC1_NCP1        0
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    target_ulong CP0_YQMask;
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    target_ulong CP0_VPESchedule;
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    target_ulong CP0_VPEScheFBack;
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    int32_t CP0_VPEOpt;
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#define CP0VPEOpt_IWX7        15
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#define CP0VPEOpt_IWX6        14
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#define CP0VPEOpt_IWX5        13
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#define CP0VPEOpt_IWX4        12
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#define CP0VPEOpt_IWX3        11
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#define CP0VPEOpt_IWX2        10
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#define CP0VPEOpt_IWX1        9
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#define CP0VPEOpt_IWX0        8
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#define CP0VPEOpt_DWX7        7
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#define CP0VPEOpt_DWX6        6
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#define CP0VPEOpt_DWX5        5
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#define CP0VPEOpt_DWX4        4
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#define CP0VPEOpt_DWX3        3
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#define CP0VPEOpt_DWX2        2
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#define CP0VPEOpt_DWX1        1
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#define CP0VPEOpt_DWX0        0
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    target_ulong CP0_EntryLo0;
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    int32_t CP0_TCStatus[MIPS_TC_MAX];
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#define CP0TCSt_TCU3        31
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#define CP0TCSt_TCU2        30
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#define CP0TCSt_TCU1        29
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#define CP0TCSt_TCU0        28
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#define CP0TCSt_TMX        27
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#define CP0TCSt_RNST        23
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#define CP0TCSt_TDS        21
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#define CP0TCSt_DT        20
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#define CP0TCSt_DA        15
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#define CP0TCSt_A        13
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#define CP0TCSt_TKSU        11
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#define CP0TCSt_IXMT        10
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#define CP0TCSt_TASID        0
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    int32_t CP0_TCBind[MIPS_TC_MAX];
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#define CP0TCBd_CurTC        21
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#define CP0TCBd_TBE        17
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#define CP0TCBd_CurVPE        0
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    target_ulong CP0_TCHalt[MIPS_TC_MAX];
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    target_ulong CP0_TCContext[MIPS_TC_MAX];
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    target_ulong CP0_TCSchedule[MIPS_TC_MAX];
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    target_ulong CP0_TCScheFBack[MIPS_TC_MAX];
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    target_ulong CP0_EntryLo1;
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    target_ulong CP0_Context;
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    int32_t CP0_PageMask;
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    int32_t CP0_PageGrain;
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    int32_t CP0_Wired;
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    int32_t CP0_SRSConf0_rw_bitmask;
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    int32_t CP0_SRSConf0;
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#define CP0SRSC0_M        31
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#define CP0SRSC0_SRS3        20
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#define CP0SRSC0_SRS2        10
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#define CP0SRSC0_SRS1        0
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    int32_t CP0_SRSConf1_rw_bitmask;
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    int32_t CP0_SRSConf1;
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#define CP0SRSC1_M        31
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#define CP0SRSC1_SRS6        20
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#define CP0SRSC1_SRS5        10
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#define CP0SRSC1_SRS4        0
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    int32_t CP0_SRSConf2_rw_bitmask;
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    int32_t CP0_SRSConf2;
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#define CP0SRSC2_M        31
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#define CP0SRSC2_SRS9        20
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#define CP0SRSC2_SRS8        10
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#define CP0SRSC2_SRS7        0
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    int32_t CP0_SRSConf3_rw_bitmask;
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    int32_t CP0_SRSConf3;
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#define CP0SRSC3_M        31
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#define CP0SRSC3_SRS12        20
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#define CP0SRSC3_SRS11        10
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#define CP0SRSC3_SRS10        0
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    int32_t CP0_SRSConf4_rw_bitmask;
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    int32_t CP0_SRSConf4;
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#define CP0SRSC4_SRS15        20
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#define CP0SRSC4_SRS14        10
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#define CP0SRSC4_SRS13        0
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    int32_t CP0_HWREna;
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    target_ulong CP0_BadVAddr;
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    int32_t CP0_Count;
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    target_ulong CP0_EntryHi;
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    int32_t CP0_Compare;
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    int32_t CP0_Status;
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#define CP0St_CU3   31
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#define CP0St_CU2   30
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#define CP0St_CU1   29
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#define CP0St_CU0   28
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#define CP0St_RP    27
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#define CP0St_FR    26
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#define CP0St_RE    25
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#define CP0St_MX    24
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#define CP0St_PX    23
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#define CP0St_BEV   22
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#define CP0St_TS    21
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#define CP0St_SR    20
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#define CP0St_NMI   19
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#define CP0St_IM    8
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#define CP0St_KX    7
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#define CP0St_SX    6
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#define CP0St_UX    5
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#define CP0St_KSU   3
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#define CP0St_ERL   2
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#define CP0St_EXL   1
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#define CP0St_IE    0
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    int32_t CP0_IntCtl;
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#define CP0IntCtl_IPTI 29
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#define CP0IntCtl_IPPC1 26
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#define CP0IntCtl_VS 5
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    int32_t CP0_SRSCtl;
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#define CP0SRSCtl_HSS 26
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#define CP0SRSCtl_EICSS 18
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#define CP0SRSCtl_ESS 12
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#define CP0SRSCtl_PSS 6
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#define CP0SRSCtl_CSS 0
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    int32_t CP0_SRSMap;
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#define CP0SRSMap_SSV7 28
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#define CP0SRSMap_SSV6 24
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#define CP0SRSMap_SSV5 20
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#define CP0SRSMap_SSV4 16
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#define CP0SRSMap_SSV3 12
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#define CP0SRSMap_SSV2 8
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#define CP0SRSMap_SSV1 4
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#define CP0SRSMap_SSV0 0
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    int32_t CP0_Cause;
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#define CP0Ca_BD   31
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#define CP0Ca_TI   30
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#define CP0Ca_CE   28
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#define CP0Ca_DC   27
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#define CP0Ca_PCI  26
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#define CP0Ca_IV   23
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#define CP0Ca_WP   22
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#define CP0Ca_IP    8
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#define CP0Ca_IP_mask 0x0000FF00
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#define CP0Ca_EC    2
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    target_ulong CP0_EPC;
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    int32_t CP0_PRid;
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    int32_t CP0_EBase;
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    int32_t CP0_Config0;
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#define CP0C0_M    31
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#define CP0C0_K23  28
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#define CP0C0_KU   25
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#define CP0C0_MDU  20
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#define CP0C0_MM   17
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#define CP0C0_BM   16
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#define CP0C0_BE   15
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#define CP0C0_AT   13
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#define CP0C0_AR   10
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#define CP0C0_MT   7
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#define CP0C0_VI   3
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#define CP0C0_K0   0
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    int32_t CP0_Config1;
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#define CP0C1_M    31
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#define CP0C1_MMU  25
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#define CP0C1_IS   22
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#define CP0C1_IL   19
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#define CP0C1_IA   16
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#define CP0C1_DS   13
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#define CP0C1_DL   10
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#define CP0C1_DA   7
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#define CP0C1_C2   6
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#define CP0C1_MD   5
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#define CP0C1_PC   4
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#define CP0C1_WR   3
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#define CP0C1_CA   2
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#define CP0C1_EP   1
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#define CP0C1_FP   0
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    int32_t CP0_Config2;
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#define CP0C2_M    31
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#define CP0C2_TU   28
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#define CP0C2_TS   24
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#define CP0C2_TL   20
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#define CP0C2_TA   16
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#define CP0C2_SU   12
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#define CP0C2_SS   8
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#define CP0C2_SL   4
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#define CP0C2_SA   0
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    int32_t CP0_Config3;
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#define CP0C3_M    31
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#define CP0C3_DSPP 10
370
#define CP0C3_LPA  7
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#define CP0C3_VEIC 6
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#define CP0C3_VInt 5
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#define CP0C3_SP   4
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#define CP0C3_MT   2
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#define CP0C3_SM   1
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#define CP0C3_TL   0
377
    int32_t CP0_Config6;
378
    int32_t CP0_Config7;
379
    /* XXX: Maybe make LLAddr per-TC? */
380
    target_ulong CP0_LLAddr;
381
    target_ulong CP0_WatchLo[8];
382
    int32_t CP0_WatchHi[8];
383
    target_ulong CP0_XContext;
384
    int32_t CP0_Framemask;
385
    int32_t CP0_Debug;
386
#define CP0DB_DBD  31
387
#define CP0DB_DM   30
388
#define CP0DB_LSNM 28
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#define CP0DB_Doze 27
390
#define CP0DB_Halt 26
391
#define CP0DB_CNT  25
392
#define CP0DB_IBEP 24
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#define CP0DB_DBEP 21
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#define CP0DB_IEXI 20
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#define CP0DB_VER  15
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#define CP0DB_DEC  10
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#define CP0DB_SSt  8
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#define CP0DB_DINT 5
399
#define CP0DB_DIB  4
400
#define CP0DB_DDBS 3
401
#define CP0DB_DDBL 2
402
#define CP0DB_DBp  1
403
#define CP0DB_DSS  0
404
    int32_t CP0_Debug_tcstatus[MIPS_TC_MAX];
405
    target_ulong CP0_DEPC;
406
    int32_t CP0_Performance0;
407
    int32_t CP0_TagLo;
408
    int32_t CP0_DataLo;
409
    int32_t CP0_TagHi;
410
    int32_t CP0_DataHi;
411
    target_ulong CP0_ErrorEPC;
412
    int32_t CP0_DESAVE;
413
    /* Qemu */
414
    int interrupt_request;
415
    int error_code;
416
    int user_mode_only; /* user mode only simulation */
417
    uint32_t hflags;    /* CPU State */
418
    /* TMASK defines different execution modes */
419
#define MIPS_HFLAG_TMASK  0x01FF
420
#define MIPS_HFLAG_MODE   0x0007 /* execution modes                    */
421
    /* The KSU flags must be the lowest bits in hflags. The flag order
422
       must be the same as defined for CP0 Status. This allows to use
423
       the bits as the value of mmu_idx. */
424
#define MIPS_HFLAG_KSU    0x0003 /* kernel/supervisor/user mode mask   */
425
#define MIPS_HFLAG_UM       0x0002 /* user mode flag */
426
#define MIPS_HFLAG_SM       0x0001 /* supervisor mode flag */
427
#define MIPS_HFLAG_KM       0x0000 /* kernel mode flag */
428
#define MIPS_HFLAG_DM     0x0004 /* Debug mode                         */
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#define MIPS_HFLAG_64     0x0008 /* 64-bit instructions enabled        */
430
#define MIPS_HFLAG_CP0    0x0010 /* CP0 enabled                        */
431
#define MIPS_HFLAG_FPU    0x0020 /* FPU enabled                        */
432
#define MIPS_HFLAG_F64    0x0040 /* 64-bit FPU enabled                 */
433
    /* True if the MIPS IV COP1X instructions can be used.  This also
434
       controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
435
       and RSQRT.D.  */
436
#define MIPS_HFLAG_COP1X  0x0080 /* COP1X instructions enabled         */
437
#define MIPS_HFLAG_RE     0x0100 /* Reversed endianness                */
438
    /* If translation is interrupted between the branch instruction and
439
     * the delay slot, record what type of branch it is so that we can
440
     * resume translation properly.  It might be possible to reduce
441
     * this from three bits to two.  */
442
#define MIPS_HFLAG_BMASK  0x0e00
443
#define MIPS_HFLAG_B      0x0200 /* Unconditional branch               */
444
#define MIPS_HFLAG_BC     0x0400 /* Conditional branch                 */
445
#define MIPS_HFLAG_BL     0x0600 /* Likely branch                      */
446
#define MIPS_HFLAG_BR     0x0800 /* branch to register (can't link TB) */
447
    target_ulong btarget;        /* Jump / branch target               */
448
    int bcond;                   /* Branch condition (if needed)       */
449

    
450
    int SYNCI_Step; /* Address step size for SYNCI */
451
    int CCRes; /* Cycle count resolution/divisor */
452
    uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
453
    uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
454
    int insn_flags; /* Supported instruction set */
455

    
456
#ifdef CONFIG_USER_ONLY
457
    target_ulong tls_value;
458
#endif
459

    
460
    CPU_COMMON
461

    
462
    const mips_def_t *cpu_model;
463
#ifndef CONFIG_USER_ONLY
464
    void *irq[8];
465
#endif
466

    
467
    struct QEMUTimer *timer; /* Internal timer */
468
};
469

    
470
int no_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
471
                        target_ulong address, int rw, int access_type);
472
int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
473
                           target_ulong address, int rw, int access_type);
474
int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
475
                     target_ulong address, int rw, int access_type);
476
void r4k_do_tlbwi (void);
477
void r4k_do_tlbwr (void);
478
void r4k_do_tlbp (void);
479
void r4k_do_tlbr (void);
480
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
481

    
482
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
483
                          int unused);
484

    
485
#define CPUState CPUMIPSState
486
#define cpu_init cpu_mips_init
487
#define cpu_exec cpu_mips_exec
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#define cpu_gen_code cpu_mips_gen_code
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#define cpu_signal_handler cpu_mips_signal_handler
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#define cpu_list mips_cpu_list
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/* MMU modes definitions. We carefully match the indices with our
493
   hflags layout. */
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _super
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#define MMU_MODE2_SUFFIX _user
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#define MMU_USER_IDX 2
498
static inline int cpu_mmu_index (CPUState *env)
499
{
500
    return env->hflags & MIPS_HFLAG_KSU;
501
}
502

    
503
#if defined(CONFIG_USER_ONLY)
504
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
505
{
506
    if (newsp)
507
        env->gpr[env->current_tc][29] = newsp;
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    env->gpr[env->current_tc][7] = 0;
509
    env->gpr[env->current_tc][2] = 0;
510
}
511
#endif
512

    
513
#include "cpu-all.h"
514

    
515
/* Memory access type :
516
 * may be needed for precise access rights control and precise exceptions.
517
 */
518
enum {
519
    /* 1 bit to define user level / supervisor access */
520
    ACCESS_USER  = 0x00,
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    ACCESS_SUPER = 0x01,
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    /* 1 bit to indicate direction */
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    ACCESS_STORE = 0x02,
524
    /* Type of instruction that generated the access */
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    ACCESS_CODE  = 0x10, /* Code fetch access                */
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    ACCESS_INT   = 0x20, /* Integer load/store access        */
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    ACCESS_FLOAT = 0x30, /* floating point load/store access */
528
};
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530
/* Exceptions */
531
enum {
532
    EXCP_NONE          = -1,
533
    EXCP_RESET         = 0,
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    EXCP_SRESET,
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    EXCP_DSS,
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    EXCP_DINT,
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    EXCP_DDBL,
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    EXCP_DDBS,
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    EXCP_NMI,
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    EXCP_MCHECK,
541
    EXCP_EXT_INTERRUPT, /* 8 */
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    EXCP_DFWATCH,
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    EXCP_DIB,
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    EXCP_IWATCH,
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    EXCP_AdEL,
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    EXCP_AdES,
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    EXCP_TLBF,
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    EXCP_IBE,
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    EXCP_DBp, /* 16 */
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    EXCP_SYSCALL,
551
    EXCP_BREAK,
552
    EXCP_CpU,
553
    EXCP_RI,
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    EXCP_OVERFLOW,
555
    EXCP_TRAP,
556
    EXCP_FPE,
557
    EXCP_DWATCH, /* 24 */
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    EXCP_LTLBL,
559
    EXCP_TLBL,
560
    EXCP_TLBS,
561
    EXCP_DBE,
562
    EXCP_THREAD,
563
    EXCP_MDMX,
564
    EXCP_C2E,
565
    EXCP_CACHE, /* 32 */
566

    
567
    EXCP_LAST = EXCP_CACHE,
568
};
569

    
570
int cpu_mips_exec(CPUMIPSState *s);
571
CPUMIPSState *cpu_mips_init(const char *cpu_model);
572
uint32_t cpu_mips_get_clock (void);
573
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
574

    
575
#endif /* !defined (__MIPS_CPU_H__) */