root / target-sh4 / helper.c @ f8ed7070
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/*
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* SH4 emulation
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*
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* Copyright (c) 2005 Samuel Tardieu
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <signal.h> |
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#include <assert.h> |
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|
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#include "cpu.h" |
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#include "exec-all.h" |
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#include "hw/sh_intc.h" |
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|
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#if defined(CONFIG_USER_ONLY)
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void do_interrupt (CPUState *env)
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{
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env->exception_index = -1;
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} |
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|
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int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{
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env->tea = address; |
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env->exception_index = 0;
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switch (rw) {
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case 0: |
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env->tea = address; |
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env->exception_index = 0x0a0;
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break;
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case 1: |
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env->tea = address; |
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env->exception_index = 0x0c0;
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break;
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} |
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return 1; |
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} |
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|
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target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
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{
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return addr;
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} |
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|
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#else /* !CONFIG_USER_ONLY */ |
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|
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#define MMU_OK 0 |
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#define MMU_ITLB_MISS (-1) |
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#define MMU_ITLB_MULTIPLE (-2) |
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#define MMU_ITLB_VIOLATION (-3) |
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#define MMU_DTLB_MISS_READ (-4) |
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#define MMU_DTLB_MISS_WRITE (-5) |
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#define MMU_DTLB_INITIAL_WRITE (-6) |
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#define MMU_DTLB_VIOLATION_READ (-7) |
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#define MMU_DTLB_VIOLATION_WRITE (-8) |
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#define MMU_DTLB_MULTIPLE (-9) |
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#define MMU_DTLB_MISS (-10) |
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|
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void do_interrupt(CPUState * env)
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{
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int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
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int do_exp, irq_vector = env->exception_index;
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/* prioritize exceptions over interrupts */
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do_exp = env->exception_index != -1;
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do_irq = do_irq && (env->exception_index == -1);
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|
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if (env->sr & SR_BL) {
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if (do_exp && env->exception_index != 0x1e0) { |
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env->exception_index = 0x000; /* masked exception -> reset */ |
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} |
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if (do_irq) {
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return; /* masked */ |
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} |
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} |
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|
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if (do_irq) {
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irq_vector = sh_intc_get_pending_vector(env->intc_handle, |
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(env->sr >> 4) & 0xf); |
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if (irq_vector == -1) { |
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return; /* masked */ |
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} |
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} |
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|
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if (loglevel & CPU_LOG_INT) {
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const char *expname; |
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switch (env->exception_index) {
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case 0x0e0: |
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expname = "addr_error";
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break;
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case 0x040: |
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expname = "tlb_miss";
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break;
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case 0x0a0: |
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expname = "tlb_violation";
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break;
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case 0x180: |
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expname = "illegal_instruction";
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break;
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case 0x1a0: |
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expname = "slot_illegal_instruction";
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break;
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case 0x800: |
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expname = "fpu_disable";
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break;
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case 0x820: |
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expname = "slot_fpu";
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break;
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case 0x100: |
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expname = "data_write";
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break;
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case 0x060: |
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expname = "dtlb_miss_write";
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break;
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case 0x0c0: |
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expname = "dtlb_violation_write";
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break;
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case 0x120: |
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expname = "fpu_exception";
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break;
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case 0x080: |
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expname = "initial_page_write";
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break;
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case 0x160: |
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expname = "trapa";
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break;
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default:
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expname = do_irq ? "interrupt" : "???"; |
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break;
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} |
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fprintf(logfile, "exception 0x%03x [%s] raised\n",
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irq_vector, expname); |
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cpu_dump_state(env, logfile, fprintf, 0);
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} |
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env->ssr = env->sr; |
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env->spc = env->pc; |
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env->sgr = env->gregs[15];
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env->sr |= SR_BL | SR_MD | SR_RB; |
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if (do_exp) {
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env->expevt = env->exception_index; |
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switch (env->exception_index) {
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case 0x000: |
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case 0x020: |
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case 0x140: |
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env->sr &= ~SR_FD; |
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env->sr |= 0xf << 4; /* IMASK */ |
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env->pc = 0xa0000000;
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break;
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case 0x040: |
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case 0x060: |
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env->pc = env->vbr + 0x400;
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break;
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case 0x160: |
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env->spc += 2; /* special case for TRAPA */ |
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/* fall through */
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default:
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env->pc = env->vbr + 0x100;
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break;
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} |
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return;
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} |
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if (do_irq) {
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env->intevt = irq_vector; |
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env->pc = env->vbr + 0x600;
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return;
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} |
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} |
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static void update_itlb_use(CPUState * env, int itlbnb) |
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{
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uint8_t or_mask = 0, and_mask = (uint8_t) - 1; |
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switch (itlbnb) {
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case 0: |
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and_mask = 0x1f;
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break;
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case 1: |
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and_mask = 0xe7;
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or_mask = 0x80;
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break;
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case 2: |
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and_mask = 0xfb;
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or_mask = 0x50;
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break;
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case 3: |
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or_mask = 0x2c;
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break;
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} |
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env->mmucr &= (and_mask << 24) | 0x00ffffff; |
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env->mmucr |= (or_mask << 24);
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} |
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|
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static int itlb_replacement(CPUState * env) |
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{
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if ((env->mmucr & 0xe0000000) == 0xe0000000) |
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return 0; |
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if ((env->mmucr & 0x98000000) == 0x18000000) |
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return 1; |
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if ((env->mmucr & 0x54000000) == 0x04000000) |
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return 2; |
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if ((env->mmucr & 0x2c000000) == 0x00000000) |
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return 3; |
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assert(0);
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} |
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|
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/* Find the corresponding entry in the right TLB
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Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
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*/
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static int find_tlb_entry(CPUState * env, target_ulong address, |
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tlb_t * entries, uint8_t nbtlb, int use_asid)
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{
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int match = MMU_DTLB_MISS;
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uint32_t start, end; |
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uint8_t asid; |
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int i;
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asid = env->pteh & 0xff;
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|
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for (i = 0; i < nbtlb; i++) { |
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if (!entries[i].v)
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continue; /* Invalid entry */ |
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if (use_asid && entries[i].asid != asid && !entries[i].sh)
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continue; /* Bad ASID */ |
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#if 0
|
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switch (entries[i].sz) {
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case 0:
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size = 1024; /* 1kB */
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break;
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case 1:
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size = 4 * 1024; /* 4kB */
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break;
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case 2:
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size = 64 * 1024; /* 64kB */
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break;
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case 3:
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size = 1024 * 1024; /* 1MB */
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break;
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default:
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assert(0);
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}
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#endif
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start = (entries[i].vpn << 10) & ~(entries[i].size - 1); |
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end = start + entries[i].size - 1;
|
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if (address >= start && address <= end) { /* Match */ |
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if (match != MMU_DTLB_MISS)
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return MMU_DTLB_MULTIPLE; /* Multiple match */ |
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match = i; |
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} |
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} |
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return match;
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} |
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|
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/* Find itlb entry - update itlb from utlb if necessary and asked for
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Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
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Update the itlb from utlb if update is not 0
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*/
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int find_itlb_entry(CPUState * env, target_ulong address,
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int use_asid, int update) |
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{
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int e, n;
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|
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e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid); |
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if (e == MMU_DTLB_MULTIPLE)
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e = MMU_ITLB_MULTIPLE; |
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else if (e == MMU_DTLB_MISS && update) { |
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e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid); |
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if (e >= 0) { |
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n = itlb_replacement(env); |
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env->itlb[n] = env->utlb[e]; |
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e = n; |
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} else if (e == MMU_DTLB_MISS) |
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e = MMU_ITLB_MISS; |
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} else if (e == MMU_DTLB_MISS) |
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e = MMU_ITLB_MISS; |
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if (e >= 0) |
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update_itlb_use(env, e); |
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return e;
|
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} |
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|
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/* Find utlb entry
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Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
|
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int find_utlb_entry(CPUState * env, target_ulong address, int use_asid) |
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{
|
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uint8_t urb, urc; |
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|
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/* Increment URC */
|
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urb = ((env->mmucr) >> 18) & 0x3f; |
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urc = ((env->mmucr) >> 10) & 0x3f; |
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urc++; |
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if (urc == urb || urc == UTLB_SIZE - 1) |
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urc = 0;
|
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env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10); |
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|
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/* Return entry */
|
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return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
|
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} |
| 319 |
|
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/* Match address against MMU
|
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Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
|
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MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
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MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
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MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION
|
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*/
|
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static int get_mmu_address(CPUState * env, target_ulong * physical, |
| 327 |
int *prot, target_ulong address,
|
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int rw, int access_type) |
| 329 |
{
|
| 330 |
int use_asid, is_code, n;
|
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tlb_t *matching = NULL;
|
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|
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use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0; |
| 334 |
is_code = env->pc == address; /* Hack */
|
| 335 |
|
| 336 |
/* Use a hack to find if this is an instruction or data access */
|
| 337 |
if (env->pc == address && !(rw & PAGE_WRITE)) {
|
| 338 |
n = find_itlb_entry(env, address, use_asid, 1);
|
| 339 |
if (n >= 0) { |
| 340 |
matching = &env->itlb[n]; |
| 341 |
if ((env->sr & SR_MD) & !(matching->pr & 2)) |
| 342 |
n = MMU_ITLB_VIOLATION; |
| 343 |
else
|
| 344 |
*prot = PAGE_READ; |
| 345 |
} |
| 346 |
} else {
|
| 347 |
n = find_utlb_entry(env, address, use_asid); |
| 348 |
if (n >= 0) { |
| 349 |
matching = &env->utlb[n]; |
| 350 |
switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) { |
| 351 |
case 0: /* 000 */ |
| 352 |
case 2: /* 010 */ |
| 353 |
n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE : |
| 354 |
MMU_DTLB_VIOLATION_READ; |
| 355 |
break;
|
| 356 |
case 1: /* 001 */ |
| 357 |
case 4: /* 100 */ |
| 358 |
case 5: /* 101 */ |
| 359 |
if (rw & PAGE_WRITE)
|
| 360 |
n = MMU_DTLB_VIOLATION_WRITE; |
| 361 |
else
|
| 362 |
*prot = PAGE_READ; |
| 363 |
break;
|
| 364 |
case 3: /* 011 */ |
| 365 |
case 6: /* 110 */ |
| 366 |
case 7: /* 111 */ |
| 367 |
*prot = rw & (PAGE_READ | PAGE_WRITE); |
| 368 |
break;
|
| 369 |
} |
| 370 |
} else if (n == MMU_DTLB_MISS) { |
| 371 |
n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE : |
| 372 |
MMU_DTLB_MISS_READ; |
| 373 |
} |
| 374 |
} |
| 375 |
if (n >= 0) { |
| 376 |
*physical = ((matching->ppn << 10) & ~(matching->size - 1)) | |
| 377 |
(address & (matching->size - 1));
|
| 378 |
if ((rw & PAGE_WRITE) & !matching->d)
|
| 379 |
n = MMU_DTLB_INITIAL_WRITE; |
| 380 |
else
|
| 381 |
n = MMU_OK; |
| 382 |
} |
| 383 |
return n;
|
| 384 |
} |
| 385 |
|
| 386 |
int get_physical_address(CPUState * env, target_ulong * physical,
|
| 387 |
int *prot, target_ulong address,
|
| 388 |
int rw, int access_type) |
| 389 |
{
|
| 390 |
/* P1, P2 and P4 areas do not use translation */
|
| 391 |
if ((address >= 0x80000000 && address < 0xc0000000) || |
| 392 |
address >= 0xe0000000) {
|
| 393 |
if (!(env->sr & SR_MD)
|
| 394 |
&& (address < 0xe0000000 || address > 0xe4000000)) { |
| 395 |
/* Unauthorized access in user mode (only store queues are available) */
|
| 396 |
fprintf(stderr, "Unauthorized access\n");
|
| 397 |
return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
|
| 398 |
MMU_DTLB_MISS_READ; |
| 399 |
} |
| 400 |
/* Mask upper 3 bits */
|
| 401 |
*physical = address & 0x1FFFFFFF;
|
| 402 |
*prot = PAGE_READ | PAGE_WRITE; |
| 403 |
return MMU_OK;
|
| 404 |
} |
| 405 |
|
| 406 |
/* If MMU is disabled, return the corresponding physical page */
|
| 407 |
if (!env->mmucr & MMUCR_AT) {
|
| 408 |
*physical = address & 0x1FFFFFFF;
|
| 409 |
*prot = PAGE_READ | PAGE_WRITE; |
| 410 |
return MMU_OK;
|
| 411 |
} |
| 412 |
|
| 413 |
/* We need to resort to the MMU */
|
| 414 |
return get_mmu_address(env, physical, prot, address, rw, access_type);
|
| 415 |
} |
| 416 |
|
| 417 |
int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
| 418 |
int mmu_idx, int is_softmmu) |
| 419 |
{
|
| 420 |
target_ulong physical, page_offset, page_size; |
| 421 |
int prot, ret, access_type;
|
| 422 |
|
| 423 |
switch (rw) {
|
| 424 |
case 0: |
| 425 |
rw = PAGE_READ; |
| 426 |
break;
|
| 427 |
case 1: |
| 428 |
rw = PAGE_WRITE; |
| 429 |
break;
|
| 430 |
case 2: /* READ_ACCESS_TYPE == 2 defined in softmmu_template.h */ |
| 431 |
rw = PAGE_READ; |
| 432 |
break;
|
| 433 |
default:
|
| 434 |
/* fatal error */
|
| 435 |
assert(0);
|
| 436 |
} |
| 437 |
|
| 438 |
/* XXXXX */
|
| 439 |
#if 0
|
| 440 |
fprintf(stderr, "%s pc %08x ad %08x rw %d mmu_idx %d smmu %d\n",
|
| 441 |
__func__, env->pc, address, rw, mmu_idx, is_softmmu);
|
| 442 |
#endif
|
| 443 |
|
| 444 |
access_type = ACCESS_INT; |
| 445 |
ret = |
| 446 |
get_physical_address(env, &physical, &prot, address, rw, |
| 447 |
access_type); |
| 448 |
|
| 449 |
if (ret != MMU_OK) {
|
| 450 |
env->tea = address; |
| 451 |
switch (ret) {
|
| 452 |
case MMU_ITLB_MISS:
|
| 453 |
case MMU_DTLB_MISS_READ:
|
| 454 |
env->exception_index = 0x040;
|
| 455 |
break;
|
| 456 |
case MMU_DTLB_MULTIPLE:
|
| 457 |
case MMU_ITLB_MULTIPLE:
|
| 458 |
env->exception_index = 0x140;
|
| 459 |
break;
|
| 460 |
case MMU_ITLB_VIOLATION:
|
| 461 |
env->exception_index = 0x0a0;
|
| 462 |
break;
|
| 463 |
case MMU_DTLB_MISS_WRITE:
|
| 464 |
env->exception_index = 0x060;
|
| 465 |
break;
|
| 466 |
case MMU_DTLB_INITIAL_WRITE:
|
| 467 |
env->exception_index = 0x080;
|
| 468 |
break;
|
| 469 |
case MMU_DTLB_VIOLATION_READ:
|
| 470 |
env->exception_index = 0x0a0;
|
| 471 |
break;
|
| 472 |
case MMU_DTLB_VIOLATION_WRITE:
|
| 473 |
env->exception_index = 0x0c0;
|
| 474 |
break;
|
| 475 |
default:
|
| 476 |
assert(0);
|
| 477 |
} |
| 478 |
return 1; |
| 479 |
} |
| 480 |
|
| 481 |
page_size = TARGET_PAGE_SIZE; |
| 482 |
page_offset = |
| 483 |
(address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
|
| 484 |
address = (address & TARGET_PAGE_MASK) + page_offset; |
| 485 |
physical = (physical & TARGET_PAGE_MASK) + page_offset; |
| 486 |
|
| 487 |
return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
|
| 488 |
} |
| 489 |
|
| 490 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
| 491 |
{
|
| 492 |
target_ulong physical; |
| 493 |
int prot;
|
| 494 |
|
| 495 |
get_physical_address(env, &physical, &prot, addr, PAGE_READ, 0);
|
| 496 |
return physical;
|
| 497 |
} |
| 498 |
|
| 499 |
void cpu_load_tlb(CPUState * env)
|
| 500 |
{
|
| 501 |
int n = cpu_mmucr_urc(env->mmucr);
|
| 502 |
tlb_t * entry = &env->utlb[n]; |
| 503 |
|
| 504 |
/* Take values into cpu status from registers. */
|
| 505 |
entry->asid = (uint8_t)cpu_pteh_asid(env->pteh); |
| 506 |
entry->vpn = cpu_pteh_vpn(env->pteh); |
| 507 |
entry->v = (uint8_t)cpu_ptel_v(env->ptel); |
| 508 |
entry->ppn = cpu_ptel_ppn(env->ptel); |
| 509 |
entry->sz = (uint8_t)cpu_ptel_sz(env->ptel); |
| 510 |
switch (entry->sz) {
|
| 511 |
case 0: /* 00 */ |
| 512 |
entry->size = 1024; /* 1K */ |
| 513 |
break;
|
| 514 |
case 1: /* 01 */ |
| 515 |
entry->size = 1024 * 4; /* 4K */ |
| 516 |
break;
|
| 517 |
case 2: /* 10 */ |
| 518 |
entry->size = 1024 * 64; /* 64K */ |
| 519 |
break;
|
| 520 |
case 3: /* 11 */ |
| 521 |
entry->size = 1024 * 1024; /* 1M */ |
| 522 |
break;
|
| 523 |
default:
|
| 524 |
assert(0);
|
| 525 |
break;
|
| 526 |
} |
| 527 |
entry->sh = (uint8_t)cpu_ptel_sh(env->ptel); |
| 528 |
entry->c = (uint8_t)cpu_ptel_c(env->ptel); |
| 529 |
entry->pr = (uint8_t)cpu_ptel_pr(env->ptel); |
| 530 |
entry->d = (uint8_t)cpu_ptel_d(env->ptel); |
| 531 |
entry->wt = (uint8_t)cpu_ptel_wt(env->ptel); |
| 532 |
entry->sa = (uint8_t)cpu_ptea_sa(env->ptea); |
| 533 |
entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); |
| 534 |
} |
| 535 |
|
| 536 |
#endif
|