Revision f930d07e
b/hw/apb_pci.c | ||
---|---|---|
70 | 70 |
}; |
71 | 71 |
|
72 | 72 |
static void apb_config_writel (void *opaque, target_phys_addr_t addr, |
73 |
uint32_t val)
|
|
73 |
uint32_t val)
|
|
74 | 74 |
{ |
75 | 75 |
//PCIBus *s = opaque; |
76 | 76 |
|
... | ... | |
80 | 80 |
case 0x18: // AFAR |
81 | 81 |
case 0x20: // Diagnostic |
82 | 82 |
case 0x28: // Target address space |
83 |
// XXX
|
|
83 |
// XXX
|
|
84 | 84 |
default: |
85 |
break;
|
|
85 |
break;
|
|
86 | 86 |
} |
87 | 87 |
} |
88 | 88 |
|
89 | 89 |
static uint32_t apb_config_readl (void *opaque, |
90 |
target_phys_addr_t addr)
|
|
90 |
target_phys_addr_t addr)
|
|
91 | 91 |
{ |
92 | 92 |
//PCIBus *s = opaque; |
93 | 93 |
uint32_t val; |
... | ... | |
98 | 98 |
case 0x18: // AFAR |
99 | 99 |
case 0x20: // Diagnostic |
100 | 100 |
case 0x28: // Target address space |
101 |
// XXX
|
|
101 |
// XXX
|
|
102 | 102 |
default: |
103 |
val = 0;
|
|
104 |
break;
|
|
103 |
val = 0;
|
|
104 |
break;
|
|
105 | 105 |
} |
106 | 106 |
return val; |
107 | 107 |
} |
... | ... | |
222 | 222 |
pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read, |
223 | 223 |
pci_apb_config_write, s); |
224 | 224 |
apb_config = cpu_register_io_memory(0, apb_config_read, |
225 |
apb_config_write, s);
|
|
225 |
apb_config_write, s);
|
|
226 | 226 |
pci_mem_data = cpu_register_io_memory(0, pci_apb_read, |
227 | 227 |
pci_apb_write, s); |
228 | 228 |
pci_ioport = cpu_register_io_memory(0, pci_apb_ioread, |
b/hw/cs4231.c | ||
---|---|---|
79 | 79 |
break; |
80 | 80 |
} |
81 | 81 |
DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret); |
82 |
break;
|
|
82 |
break;
|
|
83 | 83 |
default: |
84 | 84 |
ret = s->regs[saddr]; |
85 | 85 |
DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret); |
86 |
break;
|
|
86 |
break;
|
|
87 | 87 |
} |
88 | 88 |
return ret; |
89 | 89 |
} |
... | ... | |
122 | 122 |
break; |
123 | 123 |
default: |
124 | 124 |
s->regs[saddr] = val; |
125 |
break;
|
|
125 |
break;
|
|
126 | 126 |
} |
127 | 127 |
} |
128 | 128 |
|
b/hw/esp.c | ||
---|---|---|
107 | 107 |
if (s->dma) { |
108 | 108 |
espdma_memory_read(s->dma_opaque, buf, dmalen); |
109 | 109 |
} else { |
110 |
buf[0] = 0;
|
|
111 |
memcpy(&buf[1], s->ti_buf, dmalen);
|
|
112 |
dmalen++;
|
|
110 |
buf[0] = 0;
|
|
111 |
memcpy(&buf[1], s->ti_buf, dmalen);
|
|
112 |
dmalen++;
|
|
113 | 113 |
} |
114 | 114 |
|
115 | 115 |
s->ti_size = 0; |
... | ... | |
124 | 124 |
|
125 | 125 |
if (target >= MAX_DISKS || !s->scsi_dev[target]) { |
126 | 126 |
// No such drive |
127 |
s->rregs[4] = STAT_IN;
|
|
128 |
s->rregs[5] = INTR_DC;
|
|
129 |
s->rregs[6] = SEQ_0;
|
|
130 |
qemu_irq_raise(s->irq);
|
|
131 |
return 0;
|
|
127 |
s->rregs[4] = STAT_IN;
|
|
128 |
s->rregs[5] = INTR_DC;
|
|
129 |
s->rregs[6] = SEQ_0;
|
|
130 |
qemu_irq_raise(s->irq);
|
|
131 |
return 0;
|
|
132 | 132 |
} |
133 | 133 |
s->current_dev = s->scsi_dev[target]; |
134 | 134 |
return dmalen; |
... | ... | |
190 | 190 |
s->ti_buf[1] = 0; |
191 | 191 |
if (s->dma) { |
192 | 192 |
espdma_memory_write(s->dma_opaque, s->ti_buf, 2); |
193 |
s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
|
|
194 |
s->rregs[5] = INTR_BS | INTR_FC;
|
|
195 |
s->rregs[6] = SEQ_CD;
|
|
193 |
s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
|
|
194 |
s->rregs[5] = INTR_BS | INTR_FC;
|
|
195 |
s->rregs[6] = SEQ_CD;
|
|
196 | 196 |
} else { |
197 |
s->ti_size = 2;
|
|
198 |
s->ti_rptr = 0;
|
|
199 |
s->ti_wptr = 0;
|
|
200 |
s->rregs[7] = 2;
|
|
197 |
s->ti_size = 2;
|
|
198 |
s->ti_rptr = 0;
|
|
199 |
s->ti_wptr = 0;
|
|
200 |
s->rregs[7] = 2;
|
|
201 | 201 |
} |
202 | 202 |
qemu_irq_raise(s->irq); |
203 | 203 |
} |
... | ... | |
359 | 359 |
DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]); |
360 | 360 |
switch (saddr) { |
361 | 361 |
case 2: |
362 |
// FIFO
|
|
363 |
if (s->ti_size > 0) {
|
|
364 |
s->ti_size--;
|
|
362 |
// FIFO
|
|
363 |
if (s->ti_size > 0) {
|
|
364 |
s->ti_size--;
|
|
365 | 365 |
if ((s->rregs[4] & 6) == 0) { |
366 | 366 |
/* Data in/out. */ |
367 | 367 |
fprintf(stderr, "esp: PIO data read not implemented\n"); |
... | ... | |
370 | 370 |
s->rregs[2] = s->ti_buf[s->ti_rptr++]; |
371 | 371 |
} |
372 | 372 |
qemu_irq_raise(s->irq); |
373 |
}
|
|
374 |
if (s->ti_size == 0) {
|
|
373 |
}
|
|
374 |
if (s->ti_size == 0) {
|
|
375 | 375 |
s->ti_rptr = 0; |
376 | 376 |
s->ti_wptr = 0; |
377 | 377 |
} |
378 |
break;
|
|
378 |
break;
|
|
379 | 379 |
case 5: |
380 | 380 |
// interrupt |
381 | 381 |
// Clear interrupt/error status bits |
382 | 382 |
s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE); |
383 |
qemu_irq_lower(s->irq);
|
|
383 |
qemu_irq_lower(s->irq);
|
|
384 | 384 |
break; |
385 | 385 |
default: |
386 |
break;
|
|
386 |
break;
|
|
387 | 387 |
} |
388 | 388 |
return s->rregs[saddr]; |
389 | 389 |
} |
... | ... | |
401 | 401 |
s->rregs[4] &= ~STAT_TC; |
402 | 402 |
break; |
403 | 403 |
case 2: |
404 |
// FIFO
|
|
404 |
// FIFO
|
|
405 | 405 |
if (s->do_cmd) { |
406 | 406 |
s->cmdbuf[s->cmdlen++] = val & 0xff; |
407 | 407 |
} else if ((s->rregs[4] & 6) == 0) { |
... | ... | |
413 | 413 |
s->ti_size++; |
414 | 414 |
s->ti_buf[s->ti_wptr++] = val & 0xff; |
415 | 415 |
} |
416 |
break;
|
|
416 |
break;
|
|
417 | 417 |
case 3: |
418 | 418 |
s->rregs[saddr] = val; |
419 |
// Command
|
|
420 |
if (val & 0x80) {
|
|
421 |
s->dma = 1;
|
|
419 |
// Command
|
|
420 |
if (val & 0x80) {
|
|
421 |
s->dma = 1;
|
|
422 | 422 |
/* Reload DMA counter. */ |
423 | 423 |
s->rregs[0] = s->wregs[0]; |
424 | 424 |
s->rregs[1] = s->wregs[1]; |
425 |
} else {
|
|
426 |
s->dma = 0;
|
|
427 |
}
|
|
428 |
switch(val & 0x7f) {
|
|
429 |
case 0:
|
|
430 |
DPRINTF("NOP (%2.2x)\n", val);
|
|
431 |
break;
|
|
432 |
case 1:
|
|
433 |
DPRINTF("Flush FIFO (%2.2x)\n", val);
|
|
425 |
} else {
|
|
426 |
s->dma = 0;
|
|
427 |
}
|
|
428 |
switch(val & 0x7f) {
|
|
429 |
case 0:
|
|
430 |
DPRINTF("NOP (%2.2x)\n", val);
|
|
431 |
break;
|
|
432 |
case 1:
|
|
433 |
DPRINTF("Flush FIFO (%2.2x)\n", val);
|
|
434 | 434 |
//s->ti_size = 0; |
435 |
s->rregs[5] = INTR_FC;
|
|
436 |
s->rregs[6] = 0;
|
|
437 |
break;
|
|
438 |
case 2:
|
|
439 |
DPRINTF("Chip reset (%2.2x)\n", val);
|
|
440 |
esp_reset(s);
|
|
441 |
break;
|
|
442 |
case 3:
|
|
443 |
DPRINTF("Bus reset (%2.2x)\n", val);
|
|
444 |
s->rregs[5] = INTR_RST;
|
|
435 |
s->rregs[5] = INTR_FC;
|
|
436 |
s->rregs[6] = 0;
|
|
437 |
break;
|
|
438 |
case 2:
|
|
439 |
DPRINTF("Chip reset (%2.2x)\n", val);
|
|
440 |
esp_reset(s);
|
|
441 |
break;
|
|
442 |
case 3:
|
|
443 |
DPRINTF("Bus reset (%2.2x)\n", val);
|
|
444 |
s->rregs[5] = INTR_RST;
|
|
445 | 445 |
if (!(s->wregs[8] & 0x40)) { |
446 | 446 |
qemu_irq_raise(s->irq); |
447 | 447 |
} |
448 |
break;
|
|
449 |
case 0x10:
|
|
450 |
handle_ti(s);
|
|
451 |
break;
|
|
452 |
case 0x11:
|
|
453 |
DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
|
|
454 |
write_response(s);
|
|
455 |
break;
|
|
456 |
case 0x12:
|
|
457 |
DPRINTF("Message Accepted (%2.2x)\n", val);
|
|
458 |
write_response(s);
|
|
459 |
s->rregs[5] = INTR_DC;
|
|
460 |
s->rregs[6] = 0;
|
|
461 |
break;
|
|
462 |
case 0x1a:
|
|
463 |
DPRINTF("Set ATN (%2.2x)\n", val);
|
|
464 |
break;
|
|
465 |
case 0x42:
|
|
466 |
DPRINTF("Set ATN (%2.2x)\n", val);
|
|
467 |
handle_satn(s);
|
|
468 |
break;
|
|
469 |
case 0x43:
|
|
470 |
DPRINTF("Set ATN & stop (%2.2x)\n", val);
|
|
471 |
handle_satn_stop(s);
|
|
472 |
break;
|
|
448 |
break;
|
|
449 |
case 0x10:
|
|
450 |
handle_ti(s);
|
|
451 |
break;
|
|
452 |
case 0x11:
|
|
453 |
DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
|
|
454 |
write_response(s);
|
|
455 |
break;
|
|
456 |
case 0x12:
|
|
457 |
DPRINTF("Message Accepted (%2.2x)\n", val);
|
|
458 |
write_response(s);
|
|
459 |
s->rregs[5] = INTR_DC;
|
|
460 |
s->rregs[6] = 0;
|
|
461 |
break;
|
|
462 |
case 0x1a:
|
|
463 |
DPRINTF("Set ATN (%2.2x)\n", val);
|
|
464 |
break;
|
|
465 |
case 0x42:
|
|
466 |
DPRINTF("Set ATN (%2.2x)\n", val);
|
|
467 |
handle_satn(s);
|
|
468 |
break;
|
|
469 |
case 0x43:
|
|
470 |
DPRINTF("Set ATN & stop (%2.2x)\n", val);
|
|
471 |
handle_satn_stop(s);
|
|
472 |
break;
|
|
473 | 473 |
case 0x44: |
474 | 474 |
DPRINTF("Enable selection (%2.2x)\n", val); |
475 | 475 |
break; |
476 |
default:
|
|
477 |
DPRINTF("Unhandled ESP command (%2.2x)\n", val);
|
|
478 |
break;
|
|
479 |
}
|
|
480 |
break;
|
|
476 |
default:
|
|
477 |
DPRINTF("Unhandled ESP command (%2.2x)\n", val);
|
|
478 |
break;
|
|
479 |
}
|
|
480 |
break;
|
|
481 | 481 |
case 4 ... 7: |
482 |
break;
|
|
482 |
break;
|
|
483 | 483 |
case 8: |
484 | 484 |
s->rregs[saddr] = val; |
485 | 485 |
break; |
... | ... | |
492 | 492 |
s->rregs[saddr] = val; |
493 | 493 |
break; |
494 | 494 |
default: |
495 |
break;
|
|
495 |
break;
|
|
496 | 496 |
} |
497 | 497 |
s->wregs[saddr] = val; |
498 | 498 |
} |
b/hw/iommu.c | ||
---|---|---|
81 | 81 |
#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ |
82 | 82 |
#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ |
83 | 83 |
#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses |
84 |
produced by this device as pure
|
|
84 |
produced by this device as pure
|
|
85 | 85 |
physical. */ |
86 | 86 |
#define IOMMU_SBCFG_MASK 0x00010003 |
87 | 87 |
|
... | ... | |
98 | 98 |
|
99 | 99 |
#define PAGE_SHIFT 12 |
100 | 100 |
#define PAGE_SIZE (1 << PAGE_SHIFT) |
101 |
#define PAGE_MASK (PAGE_SIZE - 1)
|
|
101 |
#define PAGE_MASK (PAGE_SIZE - 1)
|
|
102 | 102 |
|
103 | 103 |
typedef struct IOMMUState { |
104 | 104 |
target_phys_addr_t addr; |
... | ... | |
114 | 114 |
saddr = (addr - s->addr) >> 2; |
115 | 115 |
switch (saddr) { |
116 | 116 |
default: |
117 |
DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
|
|
118 |
return s->regs[saddr];
|
|
119 |
break;
|
|
117 |
DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
|
|
118 |
return s->regs[saddr];
|
|
119 |
break;
|
|
120 | 120 |
} |
121 | 121 |
return 0; |
122 | 122 |
} |
... | ... | |
130 | 130 |
DPRINTF("write reg[%d] = %x\n", (int)saddr, val); |
131 | 131 |
switch (saddr) { |
132 | 132 |
case IOMMU_CTRL: |
133 |
switch (val & IOMMU_CTRL_RNGE) {
|
|
134 |
case IOMMU_RNGE_16MB:
|
|
135 |
s->iostart = 0xffffffffff000000ULL;
|
|
136 |
break;
|
|
137 |
case IOMMU_RNGE_32MB:
|
|
138 |
s->iostart = 0xfffffffffe000000ULL;
|
|
139 |
break;
|
|
140 |
case IOMMU_RNGE_64MB:
|
|
141 |
s->iostart = 0xfffffffffc000000ULL;
|
|
142 |
break;
|
|
143 |
case IOMMU_RNGE_128MB:
|
|
144 |
s->iostart = 0xfffffffff8000000ULL;
|
|
145 |
break;
|
|
146 |
case IOMMU_RNGE_256MB:
|
|
147 |
s->iostart = 0xfffffffff0000000ULL;
|
|
148 |
break;
|
|
149 |
case IOMMU_RNGE_512MB:
|
|
150 |
s->iostart = 0xffffffffe0000000ULL;
|
|
151 |
break;
|
|
152 |
case IOMMU_RNGE_1GB:
|
|
153 |
s->iostart = 0xffffffffc0000000ULL;
|
|
154 |
break;
|
|
155 |
default:
|
|
156 |
case IOMMU_RNGE_2GB:
|
|
157 |
s->iostart = 0xffffffff80000000ULL;
|
|
158 |
break;
|
|
159 |
}
|
|
160 |
DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
|
|
161 |
s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
|
|
162 |
break;
|
|
133 |
switch (val & IOMMU_CTRL_RNGE) {
|
|
134 |
case IOMMU_RNGE_16MB:
|
|
135 |
s->iostart = 0xffffffffff000000ULL;
|
|
136 |
break;
|
|
137 |
case IOMMU_RNGE_32MB:
|
|
138 |
s->iostart = 0xfffffffffe000000ULL;
|
|
139 |
break;
|
|
140 |
case IOMMU_RNGE_64MB:
|
|
141 |
s->iostart = 0xfffffffffc000000ULL;
|
|
142 |
break;
|
|
143 |
case IOMMU_RNGE_128MB:
|
|
144 |
s->iostart = 0xfffffffff8000000ULL;
|
|
145 |
break;
|
|
146 |
case IOMMU_RNGE_256MB:
|
|
147 |
s->iostart = 0xfffffffff0000000ULL;
|
|
148 |
break;
|
|
149 |
case IOMMU_RNGE_512MB:
|
|
150 |
s->iostart = 0xffffffffe0000000ULL;
|
|
151 |
break;
|
|
152 |
case IOMMU_RNGE_1GB:
|
|
153 |
s->iostart = 0xffffffffc0000000ULL;
|
|
154 |
break;
|
|
155 |
default:
|
|
156 |
case IOMMU_RNGE_2GB:
|
|
157 |
s->iostart = 0xffffffff80000000ULL;
|
|
158 |
break;
|
|
159 |
}
|
|
160 |
DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
|
|
161 |
s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
|
|
162 |
break;
|
|
163 | 163 |
case IOMMU_BASE: |
164 |
s->regs[saddr] = val & IOMMU_BASE_MASK;
|
|
165 |
break;
|
|
164 |
s->regs[saddr] = val & IOMMU_BASE_MASK;
|
|
165 |
break;
|
|
166 | 166 |
case IOMMU_TLBFLUSH: |
167 |
DPRINTF("tlb flush %x\n", val);
|
|
168 |
s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
|
|
169 |
break;
|
|
167 |
DPRINTF("tlb flush %x\n", val);
|
|
168 |
s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
|
|
169 |
break;
|
|
170 | 170 |
case IOMMU_PGFLUSH: |
171 |
DPRINTF("page flush %x\n", val);
|
|
172 |
s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
|
|
173 |
break;
|
|
171 |
DPRINTF("page flush %x\n", val);
|
|
172 |
s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
|
|
173 |
break;
|
|
174 | 174 |
case IOMMU_SBCFG0: |
175 | 175 |
case IOMMU_SBCFG1: |
176 | 176 |
case IOMMU_SBCFG2: |
177 | 177 |
case IOMMU_SBCFG3: |
178 |
s->regs[saddr] = val & IOMMU_SBCFG_MASK;
|
|
179 |
break;
|
|
178 |
s->regs[saddr] = val & IOMMU_SBCFG_MASK;
|
|
179 |
break;
|
|
180 | 180 |
case IOMMU_ARBEN: |
181 | 181 |
// XXX implement SBus probing: fault when reading unmapped |
182 | 182 |
// addresses, fault cause and address stored to MMU/IOMMU |
183 |
s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
|
|
184 |
break;
|
|
183 |
s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
|
|
184 |
break;
|
|
185 | 185 |
default: |
186 |
s->regs[saddr] = val;
|
|
187 |
break;
|
|
186 |
s->regs[saddr] = val;
|
|
187 |
break;
|
|
188 | 188 |
} |
189 | 189 |
} |
190 | 190 |
|
... | ... | |
283 | 283 |
int i; |
284 | 284 |
|
285 | 285 |
for (i = 0; i < IOMMU_NREGS; i++) |
286 |
qemu_put_be32s(f, &s->regs[i]);
|
|
286 |
qemu_put_be32s(f, &s->regs[i]);
|
|
287 | 287 |
qemu_put_be64s(f, &s->iostart); |
288 | 288 |
} |
289 | 289 |
|
b/hw/slavio_intctl.c | ||
---|---|---|
100 | 100 |
DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val); |
101 | 101 |
switch (saddr) { |
102 | 102 |
case 1: // clear pending softints |
103 |
if (val & 0x4000)
|
|
104 |
val |= 80000000;
|
|
105 |
val &= 0xfffe0000;
|
|
106 |
s->intreg_pending[cpu] &= ~val;
|
|
103 |
if (val & 0x4000)
|
|
104 |
val |= 80000000;
|
|
105 |
val &= 0xfffe0000;
|
|
106 |
s->intreg_pending[cpu] &= ~val;
|
|
107 | 107 |
slavio_check_interrupts(s); |
108 |
DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
|
|
109 |
break;
|
|
108 |
DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
|
|
109 |
break;
|
|
110 | 110 |
case 2: // set softint |
111 |
val &= 0xfffe0000;
|
|
112 |
s->intreg_pending[cpu] |= val;
|
|
111 |
val &= 0xfffe0000;
|
|
112 |
s->intreg_pending[cpu] |= val;
|
|
113 | 113 |
slavio_check_interrupts(s); |
114 |
DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
|
|
115 |
break;
|
|
114 |
DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
|
|
115 |
break;
|
|
116 | 116 |
default: |
117 |
break;
|
|
117 |
break;
|
|
118 | 118 |
} |
119 | 119 |
} |
120 | 120 |
|
... | ... | |
165 | 165 |
DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); |
166 | 166 |
switch (saddr) { |
167 | 167 |
case 2: // clear (enable) |
168 |
// Force clear unused bits
|
|
169 |
val &= ~0x4fb2007f;
|
|
170 |
s->intregm_disabled &= ~val;
|
|
171 |
DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
|
|
172 |
slavio_check_interrupts(s);
|
|
173 |
break;
|
|
168 |
// Force clear unused bits
|
|
169 |
val &= ~0x4fb2007f;
|
|
170 |
s->intregm_disabled &= ~val;
|
|
171 |
DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
|
|
172 |
slavio_check_interrupts(s);
|
|
173 |
break;
|
|
174 | 174 |
case 3: // set (disable, clear pending) |
175 |
// Force clear unused bits
|
|
176 |
val &= ~0x4fb2007f;
|
|
177 |
s->intregm_disabled |= val;
|
|
178 |
s->intregm_pending &= ~val;
|
|
175 |
// Force clear unused bits
|
|
176 |
val &= ~0x4fb2007f;
|
|
177 |
s->intregm_disabled |= val;
|
|
178 |
s->intregm_pending &= ~val;
|
|
179 | 179 |
slavio_check_interrupts(s); |
180 |
DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
|
|
181 |
break;
|
|
180 |
DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
|
|
181 |
break;
|
|
182 | 182 |
case 4: |
183 |
s->target_cpu = val & (MAX_CPUS - 1);
|
|
183 |
s->target_cpu = val & (MAX_CPUS - 1);
|
|
184 | 184 |
slavio_check_interrupts(s); |
185 |
DPRINTF("Set master irq cpu %d\n", s->target_cpu);
|
|
186 |
break;
|
|
185 |
DPRINTF("Set master irq cpu %d\n", s->target_cpu);
|
|
186 |
break;
|
|
187 | 187 |
default: |
188 |
break;
|
|
188 |
break;
|
|
189 | 189 |
} |
190 | 190 |
} |
191 | 191 |
|
... | ... | |
207 | 207 |
int i; |
208 | 208 |
|
209 | 209 |
for (i = 0; i < MAX_CPUS; i++) { |
210 |
term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
|
|
210 |
term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
|
|
211 | 211 |
} |
212 | 212 |
term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled); |
213 | 213 |
} |
... | ... | |
310 | 310 |
int i; |
311 | 311 |
|
312 | 312 |
for (i = 0; i < MAX_CPUS; i++) { |
313 |
qemu_put_be32s(f, &s->intreg_pending[i]);
|
|
313 |
qemu_put_be32s(f, &s->intreg_pending[i]);
|
|
314 | 314 |
} |
315 | 315 |
qemu_put_be32s(f, &s->intregm_pending); |
316 | 316 |
qemu_put_be32s(f, &s->intregm_disabled); |
... | ... | |
326 | 326 |
return -EINVAL; |
327 | 327 |
|
328 | 328 |
for (i = 0; i < MAX_CPUS; i++) { |
329 |
qemu_get_be32s(f, &s->intreg_pending[i]);
|
|
329 |
qemu_get_be32s(f, &s->intreg_pending[i]);
|
|
330 | 330 |
} |
331 | 331 |
qemu_get_be32s(f, &s->intregm_pending); |
332 | 332 |
qemu_get_be32s(f, &s->intregm_disabled); |
... | ... | |
341 | 341 |
int i; |
342 | 342 |
|
343 | 343 |
for (i = 0; i < MAX_CPUS; i++) { |
344 |
s->intreg_pending[i] = 0;
|
|
344 |
s->intreg_pending[i] = 0;
|
|
345 | 345 |
} |
346 | 346 |
s->intregm_disabled = ~0xffb2007f; |
347 | 347 |
s->intregm_pending = 0; |
... | ... | |
363 | 363 |
|
364 | 364 |
s->intbit_to_level = intbit_to_level; |
365 | 365 |
for (i = 0; i < MAX_CPUS; i++) { |
366 |
slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
|
|
367 |
cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
|
|
366 |
slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
|
|
367 |
cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
|
|
368 | 368 |
slavio_intctl_io_memory); |
369 | 369 |
s->cpu_irqs[i] = parent_irq[i]; |
370 | 370 |
} |
b/hw/slavio_misc.c | ||
---|---|---|
76 | 76 |
|
77 | 77 |
MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config); |
78 | 78 |
if (power_failing && (s->config & 0x8)) { |
79 |
s->aux2 |= 0x4;
|
|
79 |
s->aux2 |= 0x4;
|
|
80 | 80 |
} else { |
81 |
s->aux2 &= ~0x4;
|
|
81 |
s->aux2 &= ~0x4;
|
|
82 | 82 |
} |
83 | 83 |
slavio_misc_update_irq(s); |
84 | 84 |
} |
... | ... | |
89 | 89 |
|
90 | 90 |
switch (addr & 0xfff0000) { |
91 | 91 |
case 0x1800000: |
92 |
MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
|
|
93 |
s->config = val & 0xff;
|
|
94 |
slavio_misc_update_irq(s);
|
|
95 |
break;
|
|
92 |
MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
|
|
93 |
s->config = val & 0xff;
|
|
94 |
slavio_misc_update_irq(s);
|
|
95 |
break;
|
|
96 | 96 |
case 0x1900000: |
97 |
MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
|
|
98 |
s->aux1 = val & 0xff;
|
|
99 |
break;
|
|
97 |
MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
|
|
98 |
s->aux1 = val & 0xff;
|
|
99 |
break;
|
|
100 | 100 |
case 0x1910000: |
101 |
val &= 0x3;
|
|
102 |
MISC_DPRINTF("Write aux2 %2.2x\n", val);
|
|
103 |
val |= s->aux2 & 0x4;
|
|
104 |
if (val & 0x2) // Clear Power Fail int
|
|
105 |
val &= 0x1;
|
|
106 |
s->aux2 = val;
|
|
107 |
if (val & 1)
|
|
108 |
qemu_system_shutdown_request();
|
|
109 |
slavio_misc_update_irq(s);
|
|
110 |
break;
|
|
101 |
val &= 0x3;
|
|
102 |
MISC_DPRINTF("Write aux2 %2.2x\n", val);
|
|
103 |
val |= s->aux2 & 0x4;
|
|
104 |
if (val & 0x2) // Clear Power Fail int
|
|
105 |
val &= 0x1;
|
|
106 |
s->aux2 = val;
|
|
107 |
if (val & 1)
|
|
108 |
qemu_system_shutdown_request();
|
|
109 |
slavio_misc_update_irq(s);
|
|
110 |
break;
|
|
111 | 111 |
case 0x1a00000: |
112 |
MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
|
|
113 |
s->diag = val & 0xff;
|
|
114 |
break;
|
|
112 |
MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
|
|
113 |
s->diag = val & 0xff;
|
|
114 |
break;
|
|
115 | 115 |
case 0x1b00000: |
116 |
MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
|
|
117 |
s->mctrl = val & 0xff;
|
|
118 |
break;
|
|
116 |
MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
|
|
117 |
s->mctrl = val & 0xff;
|
|
118 |
break;
|
|
119 | 119 |
case 0x1f00000: |
120 |
MISC_DPRINTF("Write system control %2.2x\n", val & 0xff);
|
|
121 |
if (val & 1) {
|
|
122 |
s->sysctrl = 0x2;
|
|
123 |
qemu_system_reset_request();
|
|
124 |
}
|
|
125 |
break;
|
|
120 |
MISC_DPRINTF("Write system control %2.2x\n", val & 0xff);
|
|
121 |
if (val & 1) {
|
|
122 |
s->sysctrl = 0x2;
|
|
123 |
qemu_system_reset_request();
|
|
124 |
}
|
|
125 |
break;
|
|
126 | 126 |
case 0xa000000: |
127 |
MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
|
|
127 |
MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
|
|
128 | 128 |
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
129 |
break;
|
|
129 |
break;
|
|
130 | 130 |
} |
131 | 131 |
} |
132 | 132 |
|
... | ... | |
137 | 137 |
|
138 | 138 |
switch (addr & 0xfff0000) { |
139 | 139 |
case 0x1800000: |
140 |
ret = s->config;
|
|
141 |
MISC_DPRINTF("Read config %2.2x\n", ret);
|
|
142 |
break;
|
|
140 |
ret = s->config;
|
|
141 |
MISC_DPRINTF("Read config %2.2x\n", ret);
|
|
142 |
break;
|
|
143 | 143 |
case 0x1900000: |
144 |
ret = s->aux1;
|
|
145 |
MISC_DPRINTF("Read aux1 %2.2x\n", ret);
|
|
146 |
break;
|
|
144 |
ret = s->aux1;
|
|
145 |
MISC_DPRINTF("Read aux1 %2.2x\n", ret);
|
|
146 |
break;
|
|
147 | 147 |
case 0x1910000: |
148 |
ret = s->aux2;
|
|
149 |
MISC_DPRINTF("Read aux2 %2.2x\n", ret);
|
|
150 |
break;
|
|
148 |
ret = s->aux2;
|
|
149 |
MISC_DPRINTF("Read aux2 %2.2x\n", ret);
|
|
150 |
break;
|
|
151 | 151 |
case 0x1a00000: |
152 |
ret = s->diag;
|
|
153 |
MISC_DPRINTF("Read diag %2.2x\n", ret);
|
|
154 |
break;
|
|
152 |
ret = s->diag;
|
|
153 |
MISC_DPRINTF("Read diag %2.2x\n", ret);
|
|
154 |
break;
|
|
155 | 155 |
case 0x1b00000: |
156 |
ret = s->mctrl;
|
|
157 |
MISC_DPRINTF("Read modem control %2.2x\n", ret);
|
|
158 |
break;
|
|
156 |
ret = s->mctrl;
|
|
157 |
MISC_DPRINTF("Read modem control %2.2x\n", ret);
|
|
158 |
break;
|
|
159 | 159 |
case 0x1f00000: |
160 |
MISC_DPRINTF("Read system control %2.2x\n", ret);
|
|
161 |
ret = s->sysctrl;
|
|
162 |
break;
|
|
160 |
MISC_DPRINTF("Read system control %2.2x\n", ret);
|
|
161 |
ret = s->sysctrl;
|
|
162 |
break;
|
|
163 | 163 |
case 0xa000000: |
164 |
MISC_DPRINTF("Read power management %2.2x\n", ret);
|
|
165 |
break;
|
|
164 |
MISC_DPRINTF("Read power management %2.2x\n", ret);
|
|
165 |
break;
|
|
166 | 166 |
} |
167 | 167 |
return ret; |
168 | 168 |
} |
b/hw/slavio_serial.c | ||
---|---|---|
139 | 139 |
int val; |
140 | 140 |
|
141 | 141 |
if (q->count == 0) { |
142 |
return 0;
|
|
142 |
return 0;
|
|
143 | 143 |
} else { |
144 | 144 |
val = q->data[q->rptr]; |
145 | 145 |
if (++q->rptr == SERIO_QUEUE_SIZE) |
... | ... | |
148 | 148 |
} |
149 | 149 |
SER_DPRINTF("channel %c get 0x%02x\n", CHN_C(s), val); |
150 | 150 |
if (q->count > 0) |
151 |
serial_receive_byte(s, 0);
|
|
151 |
serial_receive_byte(s, 0);
|
|
152 | 152 |
return val; |
153 | 153 |
} |
154 | 154 |
|
155 | 155 |
static int slavio_serial_update_irq_chn(ChannelState *s) |
156 | 156 |
{ |
157 | 157 |
if ((s->wregs[1] & 1) && // interrupts enabled |
158 |
(((s->wregs[1] & 2) && s->txint == 1) || // tx ints enabled, pending
|
|
159 |
((((s->wregs[1] & 0x18) == 8) || ((s->wregs[1] & 0x18) == 0x10)) &&
|
|
160 |
s->rxint == 1) || // rx ints enabled, pending
|
|
161 |
((s->wregs[15] & 0x80) && (s->rregs[0] & 0x80)))) { // break int e&p
|
|
158 |
(((s->wregs[1] & 2) && s->txint == 1) || // tx ints enabled, pending
|
|
159 |
((((s->wregs[1] & 0x18) == 8) || ((s->wregs[1] & 0x18) == 0x10)) &&
|
|
160 |
s->rxint == 1) || // rx ints enabled, pending
|
|
161 |
((s->wregs[15] & 0x80) && (s->rregs[0] & 0x80)))) { // break int e&p
|
|
162 | 162 |
return 1; |
163 | 163 |
} |
164 | 164 |
return 0; |
... | ... | |
181 | 181 |
|
182 | 182 |
s->reg = 0; |
183 | 183 |
for (i = 0; i < SERIAL_SIZE; i++) { |
184 |
s->rregs[i] = 0;
|
|
185 |
s->wregs[i] = 0;
|
|
184 |
s->rregs[i] = 0;
|
|
185 |
s->wregs[i] = 0;
|
|
186 | 186 |
} |
187 | 187 |
s->wregs[4] = 4; |
188 | 188 |
s->wregs[9] = 0xc0; |
... | ... | |
367 | 367 |
s = &serial->chn[channel]; |
368 | 368 |
switch (saddr) { |
369 | 369 |
case 0: |
370 |
SER_DPRINTF("Write channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, val & 0xff);
|
|
371 |
newreg = 0;
|
|
372 |
switch (s->reg) {
|
|
373 |
case 0:
|
|
374 |
newreg = val & 7;
|
|
375 |
val &= 0x38;
|
|
376 |
switch (val) {
|
|
377 |
case 8:
|
|
378 |
newreg |= 0x8;
|
|
379 |
break;
|
|
380 |
case 0x28:
|
|
370 |
SER_DPRINTF("Write channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, val & 0xff);
|
|
371 |
newreg = 0;
|
|
372 |
switch (s->reg) {
|
|
373 |
case 0:
|
|
374 |
newreg = val & 7;
|
|
375 |
val &= 0x38;
|
|
376 |
switch (val) {
|
|
377 |
case 8:
|
|
378 |
newreg |= 0x8;
|
|
379 |
break;
|
|
380 |
case 0x28:
|
|
381 | 381 |
clr_txint(s); |
382 |
break;
|
|
383 |
case 0x38:
|
|
382 |
break;
|
|
383 |
case 0x38:
|
|
384 | 384 |
if (s->rxint_under_svc) |
385 | 385 |
clr_rxint(s); |
386 | 386 |
else if (s->txint_under_svc) |
387 | 387 |
clr_txint(s); |
388 |
break;
|
|
389 |
default:
|
|
390 |
break;
|
|
391 |
}
|
|
392 |
break;
|
|
388 |
break;
|
|
389 |
default:
|
|
390 |
break;
|
|
391 |
}
|
|
392 |
break;
|
|
393 | 393 |
case 1 ... 3: |
394 | 394 |
case 6 ... 8: |
395 | 395 |
case 10 ... 11: |
396 | 396 |
case 14 ... 15: |
397 |
s->wregs[s->reg] = val;
|
|
398 |
break;
|
|
397 |
s->wregs[s->reg] = val;
|
|
398 |
break;
|
|
399 | 399 |
case 4: |
400 | 400 |
case 5: |
401 | 401 |
case 12: |
402 | 402 |
case 13: |
403 |
s->wregs[s->reg] = val;
|
|
403 |
s->wregs[s->reg] = val;
|
|
404 | 404 |
slavio_serial_update_parameters(s); |
405 |
break;
|
|
406 |
case 9:
|
|
407 |
switch (val & 0xc0) {
|
|
408 |
case 0:
|
|
409 |
default:
|
|
410 |
break;
|
|
411 |
case 0x40:
|
|
412 |
slavio_serial_reset_chn(&serial->chn[1]);
|
|
413 |
return;
|
|
414 |
case 0x80:
|
|
415 |
slavio_serial_reset_chn(&serial->chn[0]);
|
|
416 |
return;
|
|
417 |
case 0xc0:
|
|
418 |
slavio_serial_reset(serial);
|
|
419 |
return;
|
|
420 |
}
|
|
421 |
break;
|
|
422 |
default:
|
|
423 |
break;
|
|
424 |
}
|
|
425 |
if (s->reg == 0)
|
|
426 |
s->reg = newreg;
|
|
427 |
else
|
|
428 |
s->reg = 0;
|
|
429 |
break;
|
|
405 |
break;
|
|
406 |
case 9:
|
|
407 |
switch (val & 0xc0) {
|
|
408 |
case 0:
|
|
409 |
default:
|
|
410 |
break;
|
|
411 |
case 0x40:
|
|
412 |
slavio_serial_reset_chn(&serial->chn[1]);
|
|
413 |
return;
|
|
414 |
case 0x80:
|
|
415 |
slavio_serial_reset_chn(&serial->chn[0]);
|
|
416 |
return;
|
|
417 |
case 0xc0:
|
|
418 |
slavio_serial_reset(serial);
|
|
419 |
return;
|
|
420 |
}
|
|
421 |
break;
|
|
422 |
default:
|
|
423 |
break;
|
|
424 |
}
|
|
425 |
if (s->reg == 0)
|
|
426 |
s->reg = newreg;
|
|
427 |
else
|
|
428 |
s->reg = 0;
|
|
429 |
break;
|
|
430 | 430 |
case 1: |
431 |
SER_DPRINTF("Write channel %c, ch %d\n", CHN_C(s), val);
|
|
431 |
SER_DPRINTF("Write channel %c, ch %d\n", CHN_C(s), val);
|
|
432 | 432 |
s->tx = val; |
433 |
if (s->wregs[5] & 8) { // tx enabled
|
|
434 |
if (s->chr)
|
|
435 |
qemu_chr_write(s->chr, &s->tx, 1);
|
|
436 |
else if (s->type == kbd) {
|
|
437 |
handle_kbd_command(s, val);
|
|
438 |
}
|
|
439 |
}
|
|
433 |
if (s->wregs[5] & 8) { // tx enabled
|
|
434 |
if (s->chr)
|
|
435 |
qemu_chr_write(s->chr, &s->tx, 1);
|
|
436 |
else if (s->type == kbd) {
|
|
437 |
handle_kbd_command(s, val);
|
|
438 |
}
|
|
439 |
}
|
|
440 | 440 |
s->rregs[0] |= 4; // Tx buffer empty |
441 | 441 |
s->rregs[1] |= 1; // All sent |
442 | 442 |
set_txint(s); |
443 |
break;
|
|
443 |
break;
|
|
444 | 444 |
default: |
445 |
break;
|
|
445 |
break;
|
|
446 | 446 |
} |
447 | 447 |
} |
448 | 448 |
|
... | ... | |
459 | 459 |
s = &serial->chn[channel]; |
460 | 460 |
switch (saddr) { |
461 | 461 |
case 0: |
462 |
SER_DPRINTF("Read channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, s->rregs[s->reg]);
|
|
463 |
ret = s->rregs[s->reg];
|
|
464 |
s->reg = 0;
|
|
465 |
return ret;
|
|
462 |
SER_DPRINTF("Read channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, s->rregs[s->reg]);
|
|
463 |
ret = s->rregs[s->reg];
|
|
464 |
s->reg = 0;
|
|
465 |
return ret;
|
|
466 | 466 |
case 1: |
467 |
s->rregs[0] &= ~1;
|
|
467 |
s->rregs[0] &= ~1;
|
|
468 | 468 |
clr_rxint(s); |
469 |
if (s->type == kbd || s->type == mouse)
|
|
470 |
ret = get_queue(s);
|
|
471 |
else
|
|
472 |
ret = s->rx;
|
|
473 |
SER_DPRINTF("Read channel %c, ch %d\n", CHN_C(s), ret);
|
|
474 |
return ret;
|
|
469 |
if (s->type == kbd || s->type == mouse)
|
|
470 |
ret = get_queue(s);
|
|
471 |
else
|
|
472 |
ret = s->rx;
|
|
473 |
SER_DPRINTF("Read channel %c, ch %d\n", CHN_C(s), ret);
|
|
474 |
return ret;
|
|
475 | 475 |
default: |
476 |
break;
|
|
476 |
break;
|
|
477 | 477 |
} |
478 | 478 |
return 0; |
479 | 479 |
} |
... | ... | |
484 | 484 |
int ret; |
485 | 485 |
|
486 | 486 |
if (((s->wregs[3] & 1) == 0) // Rx not enabled |
487 |
|| ((s->rregs[0] & 1) == 1)) // char already available
|
|
488 |
ret = 0;
|
|
487 |
|| ((s->rregs[0] & 1) == 1)) // char already available
|
|
488 |
ret = 0;
|
|
489 | 489 |
else |
490 |
ret = 1;
|
|
490 |
ret = 1;
|
|
491 | 491 |
//SER_DPRINTF("channel %c can receive %d\n", CHN_C(s), ret); |
492 | 492 |
return ret; |
493 | 493 |
} |
... | ... | |
584 | 584 |
|
585 | 585 |
ret = slavio_serial_load_chn(f, &s->chn[0], version_id); |
586 | 586 |
if (ret != 0) |
587 |
return ret;
|
|
587 |
return ret;
|
|
588 | 588 |
ret = slavio_serial_load_chn(f, &s->chn[1], version_id); |
589 | 589 |
return ret; |
590 | 590 |
|
... | ... | |
607 | 607 |
s->chn[1].chr = chr2; |
608 | 608 |
|
609 | 609 |
for (i = 0; i < 2; i++) { |
610 |
s->chn[i].irq = irq;
|
|
611 |
s->chn[i].chn = 1 - i;
|
|
612 |
s->chn[i].type = ser;
|
|
613 |
if (s->chn[i].chr) {
|
|
614 |
qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive,
|
|
610 |
s->chn[i].irq = irq;
|
|
611 |
s->chn[i].chn = 1 - i;
|
|
612 |
s->chn[i].type = ser;
|
|
613 |
if (s->chn[i].chr) {
|
|
614 |
qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive,
|
|
615 | 615 |
serial_receive1, serial_event, &s->chn[i]); |
616 |
}
|
|
616 |
}
|
|
617 | 617 |
} |
618 | 618 |
s->chn[0].otherchn = &s->chn[1]; |
619 | 619 |
s->chn[1].otherchn = &s->chn[0]; |
... | ... | |
698 | 698 |
switch (val) { |
699 | 699 |
case 1: // Reset, return type code |
700 | 700 |
clear_queue(s); |
701 |
put_queue(s, 0xff);
|
|
702 |
put_queue(s, 4); // Type 4
|
|
703 |
put_queue(s, 0x7f);
|
|
704 |
break;
|
|
701 |
put_queue(s, 0xff);
|
|
702 |
put_queue(s, 4); // Type 4
|
|
703 |
put_queue(s, 0x7f);
|
|
704 |
break;
|
|
705 | 705 |
case 0xe: // Set leds |
706 | 706 |
s->led_mode = 1; |
707 | 707 |
break; |
708 | 708 |
case 7: // Query layout |
709 | 709 |
case 0xf: |
710 | 710 |
clear_queue(s); |
711 |
put_queue(s, 0xfe);
|
|
712 |
put_queue(s, 0); // XXX, layout?
|
|
713 |
break;
|
|
711 |
put_queue(s, 0xfe);
|
|
712 |
put_queue(s, 0); // XXX, layout?
|
|
713 |
break;
|
|
714 | 714 |
default: |
715 |
break;
|
|
715 |
break;
|
|
716 | 716 |
} |
717 | 717 |
} |
718 | 718 |
|
... | ... | |
768 | 768 |
if (!s) |
769 | 769 |
return; |
770 | 770 |
for (i = 0; i < 2; i++) { |
771 |
s->chn[i].irq = irq;
|
|
772 |
s->chn[i].chn = 1 - i;
|
|
773 |
s->chn[i].chr = NULL;
|
|
771 |
s->chn[i].irq = irq;
|
|
772 |
s->chn[i].chn = 1 - i;
|
|
773 |
s->chn[i].chr = NULL;
|
|
774 | 774 |
} |
775 | 775 |
s->chn[0].otherchn = &s->chn[1]; |
776 | 776 |
s->chn[1].otherchn = &s->chn[0]; |
b/hw/slavio_timer.c | ||
---|---|---|
86 | 86 |
DPRINTF("callback: count %x%08x\n", s->counthigh, s->count); |
87 | 87 |
s->reached = 0x80000000; |
88 | 88 |
if (s->mode != 1) |
89 |
qemu_irq_raise(s->irq);
|
|
89 |
qemu_irq_raise(s->irq);
|
|
90 | 90 |
} |
91 | 91 |
|
92 | 92 |
static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) |
... | ... | |
97 | 97 |
saddr = (addr & TIMER_MAXADDR) >> 2; |
98 | 98 |
switch (saddr) { |
99 | 99 |
case 0: |
100 |
// read limit (system counter mode) or read most signifying
|
|
101 |
// part of counter (user mode)
|
|
102 |
if (s->mode != 1) {
|
|
103 |
// clear irq
|
|
100 |
// read limit (system counter mode) or read most signifying
|
|
101 |
// part of counter (user mode)
|
|
102 |
if (s->mode != 1) {
|
|
103 |
// clear irq
|
|
104 | 104 |
qemu_irq_lower(s->irq); |
105 |
s->reached = 0;
|
|
105 |
s->reached = 0;
|
|
106 | 106 |
ret = s->limit & 0x7fffffff; |
107 |
}
|
|
108 |
else {
|
|
109 |
slavio_timer_get_out(s);
|
|
107 |
}
|
|
108 |
else {
|
|
109 |
slavio_timer_get_out(s);
|
|
110 | 110 |
ret = s->counthigh & 0x7fffffff; |
111 |
}
|
|
111 |
}
|
|
112 | 112 |
break; |
113 | 113 |
case 1: |
114 |
// read counter and reached bit (system mode) or read lsbits
|
|
115 |
// of counter (user mode)
|
|
116 |
slavio_timer_get_out(s);
|
|
117 |
if (s->mode != 1)
|
|
114 |
// read counter and reached bit (system mode) or read lsbits
|
|
115 |
// of counter (user mode)
|
|
116 |
slavio_timer_get_out(s);
|
|
117 |
if (s->mode != 1)
|
|
118 | 118 |
ret = (s->count & 0x7fffffff) | s->reached; |
119 |
else
|
|
119 |
else
|
|
120 | 120 |
ret = s->count; |
121 | 121 |
break; |
122 | 122 |
case 3: |
123 |
// read start/stop status
|
|
123 |
// read start/stop status
|
|
124 | 124 |
ret = s->stopped; |
125 | 125 |
break; |
126 | 126 |
case 4: |
127 |
// read user/system mode
|
|
127 |
// read user/system mode
|
|
128 | 128 |
ret = s->slave_mode; |
129 | 129 |
break; |
130 | 130 |
default: |
... | ... | |
161 | 161 |
qemu_irq_lower(s->irq); |
162 | 162 |
// fall through |
163 | 163 |
case 2: |
164 |
// set limit without resetting counter
|
|
164 |
// set limit without resetting counter
|
|
165 | 165 |
s->limit = val & 0x7ffffe00ULL; |
166 | 166 |
if (!s->limit) |
167 | 167 |
s->limit = 0x7ffffe00ULL; |
168 | 168 |
ptimer_set_limit(s->timer, s->limit >> 9, reload); |
169 |
break;
|
|
169 |
break;
|
|
170 | 170 |
case 1: |
171 |
// set user counter limit LSW, reset counter
|
|
171 |
// set user counter limit LSW, reset counter
|
|
172 | 172 |
if (s->mode == 1) { |
173 | 173 |
qemu_irq_lower(s->irq); |
174 | 174 |
s->limit &= 0x7fffffff00000000ULL; |
... | ... | |
179 | 179 |
} |
180 | 180 |
break; |
181 | 181 |
case 3: |
182 |
// start/stop user counter
|
|
183 |
if (s->mode == 1) {
|
|
184 |
if (val & 1) {
|
|
182 |
// start/stop user counter
|
|
183 |
if (s->mode == 1) {
|
|
184 |
if (val & 1) {
|
|
185 | 185 |
ptimer_stop(s->timer); |
186 |
s->stopped = 1;
|
|
187 |
}
|
|
188 |
else {
|
|
186 |
s->stopped = 1;
|
|
187 |
}
|
|
188 |
else {
|
|
189 | 189 |
ptimer_run(s->timer, 0); |
190 |
s->stopped = 0;
|
|
191 |
}
|
|
192 |
}
|
|
193 |
break;
|
|
190 |
s->stopped = 0;
|
|
191 |
}
|
|
192 |
}
|
|
193 |
break;
|
|
194 | 194 |
case 4: |
195 |
// bit 0: user (1) or system (0) counter mode
|
|
195 |
// bit 0: user (1) or system (0) counter mode
|
|
196 | 196 |
{ |
197 | 197 |
unsigned int i; |
198 | 198 |
|
... | ... | |
211 | 211 |
} |
212 | 212 |
s->slave_mode = val & ((1 << MAX_CPUS) - 1); |
213 | 213 |
} |
214 |
break;
|
|
214 |
break;
|
|
215 | 215 |
default: |
216 |
break;
|
|
216 |
break;
|
|
217 | 217 |
} |
218 | 218 |
} |
219 | 219 |
|
... | ... | |
294 | 294 |
ptimer_set_period(s->timer, 500ULL); |
295 | 295 |
|
296 | 296 |
slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read, |
297 |
slavio_timer_mem_write, s);
|
|
297 |
slavio_timer_mem_write, s);
|
|
298 | 298 |
if (mode < 2) |
299 | 299 |
cpu_register_physical_memory(addr, CPU_TIMER_SIZE, slavio_timer_io_memory); |
300 | 300 |
else |
b/hw/sun4m.c | ||
---|---|---|
52 | 52 |
#define PROM_SIZE_MAX (512 * 1024) |
53 | 53 |
#define PROM_PADDR 0xff0000000ULL |
54 | 54 |
#define PROM_VADDR 0xffd00000 |
55 |
#define PROM_FILENAME "openbios-sparc32"
|
|
55 |
#define PROM_FILENAME "openbios-sparc32"
|
|
56 | 56 |
|
57 | 57 |
#define MAX_CPUS 16 |
58 | 58 |
#define MAX_PILS 16 |
... | ... | |
158 | 158 |
extern int nographic; |
159 | 159 |
|
160 | 160 |
static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
161 |
int boot_device, uint32_t RAM_size,
|
|
162 |
uint32_t kernel_size,
|
|
163 |
int width, int height, int depth,
|
|
161 |
int boot_device, uint32_t RAM_size,
|
|
162 |
uint32_t kernel_size,
|
|
163 |
int width, int height, int depth,
|
|
164 | 164 |
int machine_id) |
165 | 165 |
{ |
166 | 166 |
unsigned char tmp = 0; |
... | ... | |
179 | 179 |
nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR); |
180 | 180 |
nvram_set_lword(nvram, 0x3C, kernel_size); |
181 | 181 |
if (cmdline) { |
182 |
strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
|
|
183 |
nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
|
182 |
strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
|
|
183 |
nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
|
184 | 184 |
nvram_set_lword(nvram, 0x44, strlen(cmdline)); |
185 | 185 |
} |
186 | 186 |
// initrd_image, initrd_size passed differently |
... | ... | |
444 | 444 |
kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, |
445 | 445 |
NULL); |
446 | 446 |
if (kernel_size < 0) |
447 |
kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
|
448 |
if (kernel_size < 0)
|
|
449 |
kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
|
447 |
kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
|
448 |
if (kernel_size < 0)
|
|
449 |
kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
|
450 | 450 |
if (kernel_size < 0) { |
451 | 451 |
fprintf(stderr, "qemu: could not load kernel '%s'\n", |
452 | 452 |
kernel_filename); |
453 |
exit(1);
|
|
453 |
exit(1);
|
|
454 | 454 |
} |
455 | 455 |
|
456 | 456 |
/* load initrd */ |
... | ... | |
464 | 464 |
} |
465 | 465 |
} |
466 | 466 |
if (initrd_size > 0) { |
467 |
for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
|
|
468 |
if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
|
|
469 |
== 0x48647253) { // HdrS
|
|
470 |
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
|
471 |
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
|
472 |
break;
|
|
473 |
}
|
|
474 |
}
|
|
467 |
for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
|
|
468 |
if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
|
|
469 |
== 0x48647253) { // HdrS
|
|
470 |
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
|
471 |
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
|
472 |
break;
|
|
473 |
}
|
|
474 |
}
|
|
475 | 475 |
} |
476 | 476 |
} |
477 | 477 |
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, |
... | ... | |
509 | 509 |
.cs_irq = 5, |
510 | 510 |
.machine_id = 0x80, |
511 | 511 |
.intbit_to_level = { |
512 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
|
|
513 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
|
|
512 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
|
|
513 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
|
|
514 | 514 |
}, |
515 | 515 |
}, |
516 | 516 |
/* SS-10 */ |
... | ... | |
542 | 542 |
.cs_irq = -1, |
543 | 543 |
.machine_id = 0x72, |
544 | 544 |
.intbit_to_level = { |
545 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
|
|
546 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
|
|
545 |
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
|
|
546 |
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
|
|
547 | 547 |
}, |
548 | 548 |
}, |
549 | 549 |
}; |
b/hw/sun4u.c | ||
---|---|---|
28 | 28 |
#define CMDLINE_ADDR 0x003ff000 |
29 | 29 |
#define INITRD_LOAD_ADDR 0x00300000 |
30 | 30 |
#define PROM_SIZE_MAX (512 * 1024) |
31 |
#define PROM_ADDR 0x1fff0000000ULL
|
|
32 |
#define PROM_VADDR 0x000ffd00000ULL
|
|
31 |
#define PROM_ADDR 0x1fff0000000ULL
|
|
32 |
#define PROM_VADDR 0x000ffd00000ULL
|
|
33 | 33 |
#define APB_SPECIAL_BASE 0x1fe00000000ULL |
34 |
#define APB_MEM_BASE 0x1ff00000000ULL
|
|
35 |
#define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
|
|
36 |
#define PROM_FILENAME "openbios-sparc64"
|
|
34 |
#define APB_MEM_BASE 0x1ff00000000ULL
|
|
35 |
#define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
|
|
36 |
#define PROM_FILENAME "openbios-sparc64"
|
|
37 | 37 |
#define NVRAM_SIZE 0x2000 |
38 | 38 |
|
39 | 39 |
/* TSC handling */ |
... | ... | |
162 | 162 |
odd = count & 1; |
163 | 163 |
count &= ~1; |
164 | 164 |
for (i = 0; i != count; i++) { |
165 |
crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
|
|
165 |
crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
|
|
166 | 166 |
} |
167 | 167 |
if (odd) { |
168 |
crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
|
|
168 |
crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
|
|
169 | 169 |
} |
170 | 170 |
|
171 | 171 |
return crc; |
... | ... | |
387 | 387 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
388 | 388 |
ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL); |
389 | 389 |
if (ret < 0) { |
390 |
fprintf(stderr, "qemu: could not load prom '%s'\n",
|
|
391 |
buf);
|
|
392 |
exit(1);
|
|
390 |
fprintf(stderr, "qemu: could not load prom '%s'\n",
|
|
391 |
buf);
|
|
392 |
exit(1);
|
|
393 | 393 |
} |
394 | 394 |
|
395 | 395 |
kernel_size = 0; |
... | ... | |
398 | 398 |
/* XXX: put correct offset */ |
399 | 399 |
kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); |
400 | 400 |
if (kernel_size < 0) |
401 |
kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
|
402 |
if (kernel_size < 0)
|
|
403 |
kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
|
401 |
kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
|
402 |
if (kernel_size < 0)
|
|
403 |
kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
|
|
404 | 404 |
if (kernel_size < 0) { |
405 | 405 |
fprintf(stderr, "qemu: could not load kernel '%s'\n", |
406 | 406 |
kernel_filename); |
407 |
exit(1);
|
|
407 |
exit(1);
|
|
408 | 408 |
} |
409 | 409 |
|
410 | 410 |
/* load initrd */ |
... | ... | |
417 | 417 |
} |
418 | 418 |
} |
419 | 419 |
if (initrd_size > 0) { |
420 |
for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
|
|
421 |
if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
|
|
422 |
== 0x48647253) { // HdrS
|
|
423 |
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
|
424 |
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
|
425 |
break;
|
|
426 |
}
|
|
427 |
}
|
|
420 |
for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
|
|
421 |
if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
|
|
422 |
== 0x48647253) { // HdrS
|
|
423 |
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
|
424 |
stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
|
425 |
break;
|
|
426 |
}
|
|
427 |
}
|
|
428 | 428 |
} |
429 | 429 |
} |
430 | 430 |
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL); |
... | ... | |
446 | 446 |
for(i = 0; i < nb_nics; i++) { |
447 | 447 |
if (!nd_table[i].model) |
448 | 448 |
nd_table[i].model = "ne2k_pci"; |
449 |
pci_nic_init(pci_bus, &nd_table[i], -1);
|
|
449 |
pci_nic_init(pci_bus, &nd_table[i], -1);
|
|
450 | 450 |
} |
451 | 451 |
|
452 | 452 |
irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32); |
b/hw/tcx.c | ||
---|---|---|
84 | 84 |
} |
85 | 85 |
|
86 | 86 |
static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
87 |
const uint8_t *s, int width)
|
|
87 |
const uint8_t *s, int width)
|
|
88 | 88 |
{ |
89 | 89 |
int x; |
90 | 90 |
uint8_t val; |
91 | 91 |
uint32_t *p = (uint32_t *)d; |
92 | 92 |
|
93 | 93 |
for(x = 0; x < width; x++) { |
94 |
val = *s++;
|
|
94 |
val = *s++;
|
|
95 | 95 |
*p++ = s1->palette[val]; |
96 | 96 |
} |
97 | 97 |
} |
98 | 98 |
|
99 | 99 |
static void tcx_draw_line16(TCXState *s1, uint8_t *d, |
100 |
const uint8_t *s, int width)
|
|
100 |
const uint8_t *s, int width)
|
|
101 | 101 |
{ |
102 | 102 |
int x; |
103 | 103 |
uint8_t val; |
104 | 104 |
uint16_t *p = (uint16_t *)d; |
105 | 105 |
|
106 | 106 |
for(x = 0; x < width; x++) { |
107 |
val = *s++;
|
|
107 |
val = *s++;
|
|
108 | 108 |
*p++ = s1->palette[val]; |
109 | 109 |
} |
110 | 110 |
} |
111 | 111 |
|
112 | 112 |
static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
113 |
const uint8_t *s, int width)
|
|
113 |
const uint8_t *s, int width)
|
|
114 | 114 |
{ |
115 | 115 |
int x; |
116 | 116 |
uint8_t val; |
117 | 117 |
|
118 | 118 |
for(x = 0; x < width; x++) { |
119 |
val = *s++;
|
|
119 |
val = *s++;
|
|
120 | 120 |
*d++ = s1->palette[val]; |
121 | 121 |
} |
122 | 122 |
} |
... | ... | |
183 | 183 |
void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); |
184 | 184 |
|
185 | 185 |
if (ts->ds->depth == 0) |
186 |
return;
|
|
186 |
return;
|
|
187 | 187 |
page = ts->vram_offset; |
188 | 188 |
y_start = -1; |
189 | 189 |
page_min = 0xffffffff; |
... | ... | |
195 | 195 |
|
196 | 196 |
switch (ts->ds->depth) { |
197 | 197 |
case 32: |
198 |
f = tcx_draw_line32;
|
|
199 |
break;
|
|
198 |
f = tcx_draw_line32;
|
|
199 |
break;
|
|
200 | 200 |
case 15: |
201 | 201 |
case 16: |
202 |
f = tcx_draw_line16;
|
|
203 |
break;
|
|
202 |
f = tcx_draw_line16;
|
|
203 |
break;
|
|
204 | 204 |
default: |
205 | 205 |
case 8: |
206 |
f = tcx_draw_line8;
|
|
207 |
break;
|
|
206 |
f = tcx_draw_line8;
|
|
207 |
break;
|
|
208 | 208 |
case 0: |
209 |
return;
|
|
209 |
return;
|
|
210 | 210 |
} |
211 | 211 |
|
212 | 212 |
for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
213 |
if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
|
|
214 |
if (y_start < 0)
|
|
213 |
if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
|
|
214 |
if (y_start < 0)
|
|
215 | 215 |
y_start = y; |
216 | 216 |
if (page < page_min) |
217 | 217 |
page_min = page; |
218 | 218 |
if (page > page_max) |
219 | 219 |
page_max = page; |
220 |
f(ts, d, s, ts->width); |
|
221 |
d += dd; |
|
222 |
s += ds; |
|
223 |
f(ts, d, s, ts->width); |
|
224 |
d += dd; |
|
225 |
s += ds; |
|
226 |
f(ts, d, s, ts->width); |
|
227 |
d += dd; |
|
228 |
s += ds; |
|
229 |
f(ts, d, s, ts->width); |
|
230 |
d += dd; |
|
231 |
s += ds; |
|
232 |
} else { |
|
220 |
f(ts, d, s, ts->width); |
Also available in: Unified diff