Revision f930d07e hw/iommu.c
| b/hw/iommu.c | ||
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| 81 | 81 |
#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ |
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#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ |
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#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses |
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produced by this device as pure
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produced by this device as pure
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physical. */ |
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#define IOMMU_SBCFG_MASK 0x00010003 |
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#define PAGE_SHIFT 12 |
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#define PAGE_SIZE (1 << PAGE_SHIFT) |
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#define PAGE_MASK (PAGE_SIZE - 1)
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#define PAGE_MASK (PAGE_SIZE - 1)
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typedef struct IOMMUState {
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target_phys_addr_t addr; |
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saddr = (addr - s->addr) >> 2; |
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switch (saddr) {
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default: |
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DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
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return s->regs[saddr];
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break;
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DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
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return s->regs[saddr];
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break;
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} |
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return 0; |
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} |
| ... | ... | |
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DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
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switch (saddr) {
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case IOMMU_CTRL: |
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switch (val & IOMMU_CTRL_RNGE) {
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case IOMMU_RNGE_16MB:
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s->iostart = 0xffffffffff000000ULL;
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break;
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case IOMMU_RNGE_32MB:
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s->iostart = 0xfffffffffe000000ULL;
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break;
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case IOMMU_RNGE_64MB:
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s->iostart = 0xfffffffffc000000ULL;
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break;
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case IOMMU_RNGE_128MB:
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s->iostart = 0xfffffffff8000000ULL;
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break;
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case IOMMU_RNGE_256MB:
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s->iostart = 0xfffffffff0000000ULL;
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break;
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case IOMMU_RNGE_512MB:
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s->iostart = 0xffffffffe0000000ULL;
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break;
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case IOMMU_RNGE_1GB:
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s->iostart = 0xffffffffc0000000ULL;
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break;
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default:
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case IOMMU_RNGE_2GB:
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s->iostart = 0xffffffff80000000ULL;
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break;
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}
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DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
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s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
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break;
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switch (val & IOMMU_CTRL_RNGE) {
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case IOMMU_RNGE_16MB:
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s->iostart = 0xffffffffff000000ULL;
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break;
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case IOMMU_RNGE_32MB:
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s->iostart = 0xfffffffffe000000ULL;
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break;
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case IOMMU_RNGE_64MB:
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s->iostart = 0xfffffffffc000000ULL;
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break;
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case IOMMU_RNGE_128MB:
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s->iostart = 0xfffffffff8000000ULL;
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break;
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case IOMMU_RNGE_256MB:
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s->iostart = 0xfffffffff0000000ULL;
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break;
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case IOMMU_RNGE_512MB:
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s->iostart = 0xffffffffe0000000ULL;
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break;
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case IOMMU_RNGE_1GB:
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s->iostart = 0xffffffffc0000000ULL;
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break;
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default:
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case IOMMU_RNGE_2GB:
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s->iostart = 0xffffffff80000000ULL;
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break;
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}
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DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
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s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
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break;
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case IOMMU_BASE: |
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s->regs[saddr] = val & IOMMU_BASE_MASK;
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break;
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s->regs[saddr] = val & IOMMU_BASE_MASK;
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break;
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case IOMMU_TLBFLUSH: |
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DPRINTF("tlb flush %x\n", val);
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s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
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break;
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DPRINTF("tlb flush %x\n", val);
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s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
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break;
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case IOMMU_PGFLUSH: |
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DPRINTF("page flush %x\n", val);
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s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
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break;
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DPRINTF("page flush %x\n", val);
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s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
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break;
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case IOMMU_SBCFG0: |
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case IOMMU_SBCFG1: |
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case IOMMU_SBCFG2: |
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case IOMMU_SBCFG3: |
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s->regs[saddr] = val & IOMMU_SBCFG_MASK;
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break;
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s->regs[saddr] = val & IOMMU_SBCFG_MASK;
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break;
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case IOMMU_ARBEN: |
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// XXX implement SBus probing: fault when reading unmapped |
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// addresses, fault cause and address stored to MMU/IOMMU |
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s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
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break;
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s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
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break;
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default: |
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s->regs[saddr] = val;
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break;
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s->regs[saddr] = val;
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break;
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} |
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} |
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|
| ... | ... | |
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int i; |
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for (i = 0; i < IOMMU_NREGS; i++) |
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qemu_put_be32s(f, &s->regs[i]);
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qemu_put_be32s(f, &s->regs[i]);
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qemu_put_be64s(f, &s->iostart); |
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} |
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