Revision f930d07e hw/slavio_intctl.c
| b/hw/slavio_intctl.c | ||
|---|---|---|
| 100 | 100 |
DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
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| 101 | 101 |
switch (saddr) {
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| 102 | 102 |
case 1: // clear pending softints |
| 103 |
if (val & 0x4000)
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| 104 |
val |= 80000000;
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| 105 |
val &= 0xfffe0000;
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| 106 |
s->intreg_pending[cpu] &= ~val;
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| 103 |
if (val & 0x4000)
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| 104 |
val |= 80000000;
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| 105 |
val &= 0xfffe0000;
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| 106 |
s->intreg_pending[cpu] &= ~val;
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| 107 | 107 |
slavio_check_interrupts(s); |
| 108 |
DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
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| 109 |
break;
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| 108 |
DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
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| 109 |
break;
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| 110 | 110 |
case 2: // set softint |
| 111 |
val &= 0xfffe0000;
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| 112 |
s->intreg_pending[cpu] |= val;
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| 111 |
val &= 0xfffe0000;
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| 112 |
s->intreg_pending[cpu] |= val;
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| 113 | 113 |
slavio_check_interrupts(s); |
| 114 |
DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
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| 115 |
break;
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| 114 |
DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
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| 115 |
break;
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| 116 | 116 |
default: |
| 117 |
break;
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| 117 |
break;
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| 118 | 118 |
} |
| 119 | 119 |
} |
| 120 | 120 |
|
| ... | ... | |
| 165 | 165 |
DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
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| 166 | 166 |
switch (saddr) {
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| 167 | 167 |
case 2: // clear (enable) |
| 168 |
// Force clear unused bits
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| 169 |
val &= ~0x4fb2007f;
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| 170 |
s->intregm_disabled &= ~val;
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| 171 |
DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
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| 172 |
slavio_check_interrupts(s);
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| 173 |
break;
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| 168 |
// Force clear unused bits
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| 169 |
val &= ~0x4fb2007f;
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| 170 |
s->intregm_disabled &= ~val;
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| 171 |
DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
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| 172 |
slavio_check_interrupts(s);
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| 173 |
break;
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| 174 | 174 |
case 3: // set (disable, clear pending) |
| 175 |
// Force clear unused bits
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| 176 |
val &= ~0x4fb2007f;
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| 177 |
s->intregm_disabled |= val;
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| 178 |
s->intregm_pending &= ~val;
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| 175 |
// Force clear unused bits
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| 176 |
val &= ~0x4fb2007f;
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| 177 |
s->intregm_disabled |= val;
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| 178 |
s->intregm_pending &= ~val;
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| 179 | 179 |
slavio_check_interrupts(s); |
| 180 |
DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
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| 181 |
break;
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| 180 |
DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
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| 181 |
break;
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| 182 | 182 |
case 4: |
| 183 |
s->target_cpu = val & (MAX_CPUS - 1);
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| 183 |
s->target_cpu = val & (MAX_CPUS - 1);
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| 184 | 184 |
slavio_check_interrupts(s); |
| 185 |
DPRINTF("Set master irq cpu %d\n", s->target_cpu);
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| 186 |
break;
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| 185 |
DPRINTF("Set master irq cpu %d\n", s->target_cpu);
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| 186 |
break;
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| 187 | 187 |
default: |
| 188 |
break;
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| 188 |
break;
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| 189 | 189 |
} |
| 190 | 190 |
} |
| 191 | 191 |
|
| ... | ... | |
| 207 | 207 |
int i; |
| 208 | 208 |
|
| 209 | 209 |
for (i = 0; i < MAX_CPUS; i++) {
|
| 210 |
term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
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| 210 |
term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
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| 211 | 211 |
} |
| 212 | 212 |
term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
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| 213 | 213 |
} |
| ... | ... | |
| 310 | 310 |
int i; |
| 311 | 311 |
|
| 312 | 312 |
for (i = 0; i < MAX_CPUS; i++) {
|
| 313 |
qemu_put_be32s(f, &s->intreg_pending[i]);
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| 313 |
qemu_put_be32s(f, &s->intreg_pending[i]);
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| 314 | 314 |
} |
| 315 | 315 |
qemu_put_be32s(f, &s->intregm_pending); |
| 316 | 316 |
qemu_put_be32s(f, &s->intregm_disabled); |
| ... | ... | |
| 326 | 326 |
return -EINVAL; |
| 327 | 327 |
|
| 328 | 328 |
for (i = 0; i < MAX_CPUS; i++) {
|
| 329 |
qemu_get_be32s(f, &s->intreg_pending[i]);
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| 329 |
qemu_get_be32s(f, &s->intreg_pending[i]);
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| 330 | 330 |
} |
| 331 | 331 |
qemu_get_be32s(f, &s->intregm_pending); |
| 332 | 332 |
qemu_get_be32s(f, &s->intregm_disabled); |
| ... | ... | |
| 341 | 341 |
int i; |
| 342 | 342 |
|
| 343 | 343 |
for (i = 0; i < MAX_CPUS; i++) {
|
| 344 |
s->intreg_pending[i] = 0;
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| 344 |
s->intreg_pending[i] = 0;
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| 345 | 345 |
} |
| 346 | 346 |
s->intregm_disabled = ~0xffb2007f; |
| 347 | 347 |
s->intregm_pending = 0; |
| ... | ... | |
| 363 | 363 |
|
| 364 | 364 |
s->intbit_to_level = intbit_to_level; |
| 365 | 365 |
for (i = 0; i < MAX_CPUS; i++) {
|
| 366 |
slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
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|
| 367 |
cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
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| 366 |
slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
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| 367 |
cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
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| 368 | 368 |
slavio_intctl_io_memory); |
| 369 | 369 |
s->cpu_irqs[i] = parent_irq[i]; |
| 370 | 370 |
} |
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