Revision f93eb9ff hw/mainstone.c
b/hw/mainstone.c | ||
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59 | 59 |
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enum mainstone_model_e { mainstone }; |
61 | 61 |
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static struct arm_boot_info mainstone_binfo = { |
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.loader_start = PXA2XX_SDRAM_BASE, |
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.ram_size = 0x04000000, |
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}; |
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62 | 67 |
static void mainstone_common_init(int ram_size, int vga_ram_size, |
63 | 68 |
DisplayState *ds, const char *kernel_filename, |
64 | 69 |
const char *kernel_cmdline, const char *initrd_filename, |
65 | 70 |
const char *cpu_model, enum mainstone_model_e model, int arm_id) |
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{ |
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uint32_t mainstone_ram = 0x04000000;
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uint32_t mainstone_ram = mainstone_binfo.ram_size;
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uint32_t mainstone_rom = 0x00800000; |
69 | 74 |
uint32_t mainstone_flash = 0x02000000; |
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uint32_t sector_len = 256 * 1024; |
... | ... | |
90 | 95 |
qemu_ram_alloc(mainstone_rom) | IO_MEM_ROM); |
91 | 96 |
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/* Setup initial (reset) machine state */ |
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cpu->env->regs[15] = PXA2XX_SDRAM_BASE;
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cpu->env->regs[15] = mainstone_binfo.loader_start;
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94 | 99 |
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/* There are two 32MiB flash devices on the board */ |
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for (i = 0; i < 2; i ++) { |
... | ... | |
121 | 126 |
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smc91c111_init(&nd_table[0], MST_ETH_PHYS, mst_irq[ETHERNET_IRQ]); |
123 | 128 |
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arm_load_kernel(cpu->env, mainstone_ram, kernel_filename, kernel_cmdline, |
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initrd_filename, arm_id, PXA2XX_SDRAM_BASE); |
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mainstone_binfo.kernel_filename = kernel_filename; |
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mainstone_binfo.kernel_cmdline = kernel_cmdline; |
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mainstone_binfo.initrd_filename = initrd_filename; |
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mainstone_binfo.board_id = arm_id; |
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arm_load_kernel(cpu->env, &mainstone_binfo); |
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126 | 134 |
} |
127 | 135 |
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128 | 136 |
static void mainstone_init(int ram_size, int vga_ram_size, |
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