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/*
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 * Misc ARM declarations
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 *
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 * Copyright (c) 2006 CodeSourcery.
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 * Written by Paul Brook
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 *
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 * This code is licenced under the LGPL.
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 *
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 */
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#ifndef ARM_MISC_H
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#define ARM_MISC_H 1
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/* The CPU is also modeled as an interrupt controller.  */
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#define ARM_PIC_CPU_IRQ 0
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#define ARM_PIC_CPU_FIQ 1
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qemu_irq *arm_pic_init_cpu(CPUState *env);
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/* armv7m.c */
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qemu_irq *armv7m_init(int flash_size, int sram_size,
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                      const char *kernel_filename, const char *cpu_model);
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/* arm_boot.c */
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struct arm_boot_info {
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    int ram_size;
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    const char *kernel_filename;
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    const char *kernel_cmdline;
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    const char *initrd_filename;
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    target_phys_addr_t loader_start;
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    int nb_cpus;
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    int board_id;
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    int (*atag_board)(struct arm_boot_info *info, void *p);
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};
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void arm_load_kernel(CPUState *env, struct arm_boot_info *info);
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/* armv7m_nvic.c */
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int system_clock_scale;
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qemu_irq *armv7m_nvic_init(CPUState *env);
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/* stellaris_enent.c */
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void stellaris_enet_init(NICInfo *nd, uint32_t base, qemu_irq irq);
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#endif /* !ARM_MISC_H */
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