Introduce range.h
Extract range functions from pci.h. These will be used by later patchesby non-PCI devices. Adjust current users.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>(cherry picked from commit bf1b00712375bea65f2254dea8281fa646eebbd5)
pcie: simplify range check
Simplify code slighly by reversing the polarityfor the range check
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
pcie: clean up hot plug notification
Simplify logic for hotplug notification, by tracking state of thelogical interrupt condition. We then simply use this variable to makethe interrupt decision, according to spec.
API is made cleaner as we no longer force users to pass in...
pci: improve w1c mask handling
- save/restore must not check w1c bits since they are in fact guest controlled- clear w1c bits on reset
Note: for express there are different kinds ofreset, some leave part of config space alone.We will likely need a sticky bit mask to implement this....
x3130: pcie downstream port
Implement TI x3130 pcie downstream port switch.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
x3130: pcie upstream port
Implement TI x3130 pcie upstream port switch.
ioh3420: pcie root port in X58 ioh
Implements pcie root port switch in intel X58 iohwhose device id is 0x3420.
pcie port: define struct PCIEPort/PCIESlot and helper functions
define struct PCIEPort which represents common partof pci express port.(root, upstream and downstream.)add a helper function for pcie port which can be used commonly byroot/upstream/downstream port....
pci/bridge: fix pci_bridge_reset()
The lower bits of base/limit registers is RO and shouldn't be zerocleared on reset. This patch fixes it.In fact, the default value of base/limit registers aren't specifiedin the spec. And some bridges disable forwarding on reset instead of...
pcie: comment on hpev_intx
document hpev_intx.
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