Archipelago » qemu

/*

 *  PowerPC emulation helpers for qemu.

 *

 *  Copyright (c) 2003-2007 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include <signal.h>

#include <assert.h>

#include "cpu.h"

#include "exec-all.h"

#include "helper_regs.h"

//#define DEBUG_MMU

//#define DEBUG_BATS

//#define DEBUG_SOFTWARE_TLB

//#define DUMP_PAGE_TABLES

//#define DEBUG_EXCEPTIONS

//#define FLUSH_ALL_TLBS

/*****************************************************************************/

/* PowerPC MMU emulation */

#if defined(CONFIG_USER_ONLY)

int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,

                              int mmu_idx, int is_softmmu)

{

    int exception, error_code;

    if (rw == 2) {

        exception = POWERPC_EXCP_ISI;

        error_code = 0x40000000;

    } else {

        exception = POWERPC_EXCP_DSI;

        error_code = 0x40000000;

        if (rw)

            error_code |= 0x02000000;

        env->spr[SPR_DAR] = address;

        env->spr[SPR_DSISR] = error_code;

    }

    env->exception_index = exception;

    env->error_code = error_code;

    return 1;

}

target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)

{

    return addr;

}

#else

/* Common routines used by software and hardware TLBs emulation */

static always_inline int pte_is_valid (target_ulong pte0)

{

    return pte0 & 0x80000000 ? 1 : 0;

}

static always_inline void pte_invalidate (target_ulong *pte0)

{

    *pte0 &= ~0x80000000;

}

#if defined(TARGET_PPC64)

static always_inline int pte64_is_valid (target_ulong pte0)

{

    return pte0 & 0x0000000000000001ULL ? 1 : 0;

}

static always_inline void pte64_invalidate (target_ulong *pte0)

{

    *pte0 &= ~0x0000000000000001ULL;

}

#endif

#define PTE_PTEM_MASK 0x7FFFFFBF

#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)

#if defined(TARGET_PPC64)

#define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL

#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)

#endif

static always_inline int pp_check (int key, int pp, int nx)

{

    int access;

    /* Compute access rights */

    /* When pp is 3/7, the result is undefined. Set it to noaccess */

    access = 0;

    if (key == 0) {

        switch (pp) {

        case 0x0:

        case 0x1:

        case 0x2:

            access |= PAGE_WRITE;

            /* No break here */

        case 0x3:

        case 0x6:

            access |= PAGE_READ;

            break;

        }

    } else {

        switch (pp) {

        case 0x0:

        case 0x6:

            access = 0;

            break;

        case 0x1:

        case 0x3:

            access = PAGE_READ;

            break;

        case 0x2:

            access = PAGE_READ | PAGE_WRITE;

            break;

        }

    }

    if (nx == 0)

        access |= PAGE_EXEC;

    return access;

}

static always_inline int check_prot (int prot, int rw, int access_type)

{

    int ret;

    if (access_type == ACCESS_CODE) {

        if (prot & PAGE_EXEC)

            ret = 0;

        else

            ret = -2;

    } else if (rw) {

        if (prot & PAGE_WRITE)

            ret = 0;

        else

            ret = -2;

    } else {

        if (prot & PAGE_READ)

            ret = 0;

        else

            ret = -2;

    }

    return ret;

}

static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,

                                     target_ulong pte0, target_ulong pte1,

                                     int h, int rw, int type)

{

    target_ulong ptem, mmask;

    int access, ret, pteh, ptev, pp;

    access = 0;

    ret = -1;

    /* Check validity and table match */

#if defined(TARGET_PPC64)

    if (is_64b) {

        ptev = pte64_is_valid(pte0);

        pteh = (pte0 >> 1) & 1;

    } else

#endif

    {

        ptev = pte_is_valid(pte0);

        pteh = (pte0 >> 6) & 1;

    }

    if (ptev && h == pteh) {

        /* Check vsid & api */

#if defined(TARGET_PPC64)

        if (is_64b) {

            ptem = pte0 & PTE64_PTEM_MASK;

            mmask = PTE64_CHECK_MASK;

            pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004);

            ctx->nx |= (pte1 >> 2) & 1; /* No execute bit */

            ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit    */

        } else

#endif

        {

            ptem = pte0 & PTE_PTEM_MASK;

            mmask = PTE_CHECK_MASK;

            pp = pte1 & 0x00000003;

        }

        if (ptem == ctx->ptem) {

            if (ctx->raddr != (target_ulong)-1) {

                /* all matches should have equal RPN, WIMG & PP */

                if ((ctx->raddr & mmask) != (pte1 & mmask)) {

                    if (loglevel != 0)

                        fprintf(logfile, "Bad RPN/WIMG/PP\n");

                    return -3;

                }

            }

            /* Compute access rights */

            access = pp_check(ctx->key, pp, ctx->nx);

            /* Keep the matching PTE informations */

            ctx->raddr = pte1;

            ctx->prot = access;

            ret = check_prot(ctx->prot, rw, type);

            if (ret == 0) {

                /* Access granted */

#if defined (DEBUG_MMU)

                if (loglevel != 0)

                    fprintf(logfile, "PTE access granted !\n");

#endif

            } else {

                /* Access right violation */

#if defined (DEBUG_MMU)

                if (loglevel != 0)

                    fprintf(logfile, "PTE access rejected\n");

#endif

            }

        }

    }

    return ret;

}

static int pte32_check (mmu_ctx_t *ctx, target_ulong pte0, target_ulong pte1,

                        int h, int rw, int type)

{

    return _pte_check(ctx, 0, pte0, pte1, h, rw, type);

}

#if defined(TARGET_PPC64)

static int pte64_check (mmu_ctx_t *ctx, target_ulong pte0, target_ulong pte1,

                        int h, int rw, int type)

{

    return _pte_check(ctx, 1, pte0, pte1, h, rw, type);

}

#endif

static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,

                             int ret, int rw)

{

    int store = 0;

    /* Update page flags */

    if (!(*pte1p & 0x00000100)) {

        /* Update accessed flag */

        *pte1p |= 0x00000100;

        store = 1;

    }

    if (!(*pte1p & 0x00000080)) {

        if (rw == 1 && ret == 0) {

            /* Update changed flag */

            *pte1p |= 0x00000080;

            store = 1;

        } else {

            /* Force page fault for first write access */

            ctx->prot &= ~PAGE_WRITE;

        }

    }

    return store;

}

/* Software driven TLB helpers */

static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,

                              int way, int is_code)

{

    int nr;

    /* Select TLB num in a way from address */

    nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);

    /* Select TLB way */

    nr += env->tlb_per_way * way;

    /* 6xx have separate TLBs for instructions and data */

    if (is_code && env->id_tlbs == 1)

        nr += env->nb_tlb;

    return nr;

}

static void ppc6xx_tlb_invalidate_all (CPUState *env)

{

    ppc6xx_tlb_t *tlb;

    int nr, max;

#if defined (DEBUG_SOFTWARE_TLB) && 0

    if (loglevel != 0) {

        fprintf(logfile, "Invalidate all TLBs\n");

    }

#endif

    /* Invalidate all defined software TLB */

    max = env->nb_tlb;

    if (env->id_tlbs == 1)

        max *= 2;

    for (nr = 0; nr < max; nr++) {

        tlb = &env->tlb[nr].tlb6;

        pte_invalidate(&tlb->pte0);

    }

    tlb_flush(env, 1);

}

static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,

                                                        target_ulong eaddr,

                                                        int is_code,

                                                        int match_epn)

{

#if !defined(FLUSH_ALL_TLBS)

    ppc6xx_tlb_t *tlb;

    int way, nr;

    /* Invalidate ITLB + DTLB, all ways */

    for (way = 0; way < env->nb_ways; way++) {

        nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);

        tlb = &env->tlb[nr].tlb6;

        if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {

#if defined (DEBUG_SOFTWARE_TLB)

            if (loglevel != 0) {

                fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",

                        nr, env->nb_tlb, eaddr);

            }

#endif

            pte_invalidate(&tlb->pte0);

            tlb_flush_page(env, tlb->EPN);

        }

    }

#else

    /* XXX: PowerPC specification say this is valid as well */

    ppc6xx_tlb_invalidate_all(env);

#endif

}

static void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,

                                        int is_code)

{

    __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);

}

void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,

                       target_ulong pte0, target_ulong pte1)

{

    ppc6xx_tlb_t *tlb;

    int nr;

    nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);

    tlb = &env->tlb[nr].tlb6;

#if defined (DEBUG_SOFTWARE_TLB)

    if (loglevel != 0) {

        fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX

                " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);

    }

#endif

    /* Invalidate any pending reference in Qemu for this virtual address */

    __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);

    tlb->pte0 = pte0;

    tlb->pte1 = pte1;

    tlb->EPN = EPN;

    /* Store last way for LRU mechanism */

    env->last_way = way;

}

static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,

                             target_ulong eaddr, int rw, int access_type)

{

    ppc6xx_tlb_t *tlb;

    int nr, best, way;

    int ret;

    best = -1;

    ret = -1; /* No TLB found */

    for (way = 0; way < env->nb_ways; way++) {

        nr = ppc6xx_tlb_getnum(env, eaddr, way,

                               access_type == ACCESS_CODE ? 1 : 0);

        tlb = &env->tlb[nr].tlb6;

        /* This test "emulates" the PTE index match for hardware TLBs */

        if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {

#if defined (DEBUG_SOFTWARE_TLB)

            if (loglevel != 0) {

                fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX

                        "] <> " ADDRX "\n",

                        nr, env->nb_tlb,

                        pte_is_valid(tlb->pte0) ? "valid" : "inval",

                        tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);

            }

#endif

            continue;

        }

#if defined (DEBUG_SOFTWARE_TLB)

        if (loglevel != 0) {

            fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX

                    " %c %c\n",

                    nr, env->nb_tlb,

                    pte_is_valid(tlb->pte0) ? "valid" : "inval",

                    tlb->EPN, eaddr, tlb->pte1,

                    rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');

        }

#endif

        switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {

        case -3:

            /* TLB inconsistency */

            return -1;

        case -2:

            /* Access violation */

            ret = -2;

            best = nr;

            break;

        case -1:

        default:

            /* No match */

            break;

        case 0:

            /* access granted */

            /* XXX: we should go on looping to check all TLBs consistency

             *      but we can speed-up the whole thing as the

             *      result would be undefined if TLBs are not consistent.

             */

            ret = 0;

            best = nr;

            goto done;

        }

    }

    if (best != -1) {

    done:

#if defined (DEBUG_SOFTWARE_TLB)

        if (loglevel != 0) {

            fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",

                    ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);

        }

#endif

        /* Update page flags */

        pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);

    }

    return ret;

}

/* Perform BAT hit & translation */

static int get_bat (CPUState *env, mmu_ctx_t *ctx,

                    target_ulong virtual, int rw, int type)

{

    target_ulong *BATlt, *BATut, *BATu, *BATl;

    target_ulong base, BEPIl, BEPIu, bl;

    int i, pp, pr;

    int ret = -1;

#if defined (DEBUG_BATS)

    if (loglevel != 0) {

        fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,

                type == ACCESS_CODE ? 'I' : 'D', virtual);

    }

#endif

    pr = msr_pr;

    switch (type) {

    case ACCESS_CODE:

        BATlt = env->IBAT[1];

        BATut = env->IBAT[0];

        break;

    default:

        BATlt = env->DBAT[1];

        BATut = env->DBAT[0];

        break;

    }

#if defined (DEBUG_BATS)

    if (loglevel != 0) {

        fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,

                type == ACCESS_CODE ? 'I' : 'D', virtual);

    }

#endif

    base = virtual & 0xFFFC0000;

    for (i = 0; i < 4; i++) {

        BATu = &BATut[i];

        BATl = &BATlt[i];

        BEPIu = *BATu & 0xF0000000;

        BEPIl = *BATu & 0x0FFE0000;

        bl = (*BATu & 0x00001FFC) << 15;

#if defined (DEBUG_BATS)

        if (loglevel != 0) {

            fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX

                    " BATl 0x" ADDRX "\n",

                    __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,

                    *BATu, *BATl);

        }

#endif

        if ((virtual & 0xF0000000) == BEPIu &&

            ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {

            /* BAT matches */

            if (((pr == 0) && (*BATu & 0x00000002)) ||

                ((pr != 0) && (*BATu & 0x00000001))) {

                /* Get physical address */

                ctx->raddr = (*BATl & 0xF0000000) |

                    ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |

                    (virtual & 0x0001F000);

                /* Compute access rights */

                pp = *BATl & 0x00000003;

                ctx->prot = 0;

                if (pp != 0) {

                    ctx->prot = PAGE_READ | PAGE_EXEC;

                    if (pp == 0x2)

                        ctx->prot |= PAGE_WRITE;

                }

                ret = check_prot(ctx->prot, rw, type);

#if defined (DEBUG_BATS)

                if (ret == 0 && loglevel != 0) {

                    fprintf(logfile, "BAT %d match: r 0x" PADDRX

                            " prot=%c%c\n",

                            i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',

                            ctx->prot & PAGE_WRITE ? 'W' : '-');

                }

#endif

                break;

            }

        }

    }

    if (ret < 0) {

#if defined (DEBUG_BATS)

        if (loglevel != 0) {

            fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);

            for (i = 0; i < 4; i++) {

                BATu = &BATut[i];

                BATl = &BATlt[i];

                BEPIu = *BATu & 0xF0000000;

                BEPIl = *BATu & 0x0FFE0000;

                bl = (*BATu & 0x00001FFC) << 15;

                fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX

                        " BATl 0x" ADDRX " \n\t"

                        "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",

                        __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,

                        *BATu, *BATl, BEPIu, BEPIl, bl);

            }

        }

#endif

    }

    /* No hit */

    return ret;

}

/* PTE table lookup */

static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,

                                    int rw, int type)

{

    target_ulong base, pte0, pte1;

    int i, good = -1;

    int ret, r;

    ret = -1; /* No entry found */

    base = ctx->pg_addr[h];

    for (i = 0; i < 8; i++) {

#if defined(TARGET_PPC64)

        if (is_64b) {

            pte0 = ldq_phys(base + (i * 16));

            pte1 =  ldq_phys(base + (i * 16) + 8);

            r = pte64_check(ctx, pte0, pte1, h, rw, type);

#if defined (DEBUG_MMU)

            if (loglevel != 0) {

                fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX

                        " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",

                        base + (i * 16), pte0, pte1,

                        (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1),

                        ctx->ptem);

            }

#endif

        } else

#endif

        {

            pte0 = ldl_phys(base + (i * 8));

            pte1 =  ldl_phys(base + (i * 8) + 4);

            r = pte32_check(ctx, pte0, pte1, h, rw, type);

#if defined (DEBUG_MMU)

            if (loglevel != 0) {

                fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX

                        " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",

                        base + (i * 8), pte0, pte1,

                        (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1),

                        ctx->ptem);

            }

#endif

        }

        switch (r) {

        case -3:

            /* PTE inconsistency */

            return -1;

        case -2:

            /* Access violation */

            ret = -2;

            good = i;

            break;

        case -1:

        default:

            /* No PTE match */

            break;

        case 0:

            /* access granted */

            /* XXX: we should go on looping to check all PTEs consistency

             *      but if we can speed-up the whole thing as the

             *      result would be undefined if PTEs are not consistent.

             */

            ret = 0;

            good = i;

            goto done;

        }

    }

    if (good != -1) {

    done:

#if defined (DEBUG_MMU)

        if (loglevel != 0) {

            fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "

                    "ret=%d\n",

                    ctx->raddr, ctx->prot, ret);

        }

#endif

        /* Update page flags */

        pte1 = ctx->raddr;

        if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {

#if defined(TARGET_PPC64)

            if (is_64b) {

                stq_phys_notdirty(base + (good * 16) + 8, pte1);

            } else

#endif

            {

                stl_phys_notdirty(base + (good * 8) + 4, pte1);

            }

        }

    }

    return ret;

}

static int find_pte32 (mmu_ctx_t *ctx, int h, int rw, int type)

{

    return _find_pte(ctx, 0, h, rw, type);

}

#if defined(TARGET_PPC64)

static int find_pte64 (mmu_ctx_t *ctx, int h, int rw, int type)

{

    return _find_pte(ctx, 1, h, rw, type);

}

#endif

static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx,

                                   int h, int rw, int type)

{

#if defined(TARGET_PPC64)

    if (env->mmu_model == POWERPC_MMU_64B)

        return find_pte64(ctx, h, rw, type);

#endif

    return find_pte32(ctx, h, rw, type);

}

#if defined(TARGET_PPC64)

static inline int slb_is_valid (uint64_t slb64)

{

    return slb64 & 0x0000000008000000ULL ? 1 : 0;

}

static inline void slb_invalidate (uint64_t *slb64)

{

    *slb64 &= ~0x0000000008000000ULL;

}

static int slb_lookup (CPUPPCState *env, target_ulong eaddr,

                       target_ulong *vsid, target_ulong *page_mask, int *attr)

{

    target_phys_addr_t sr_base;

    target_ulong mask;

    uint64_t tmp64;

    uint32_t tmp;

    int n, ret;

    ret = -5;

    sr_base = env->spr[SPR_ASR];

#if defined(DEBUG_SLB)

    if (loglevel != 0) {

        fprintf(logfile, "%s: eaddr " ADDRX " base " PADDRX "\n",

                __func__, eaddr, sr_base);

    }

#endif

    mask = 0x0000000000000000ULL; /* Avoid gcc warning */

    for (n = 0; n < env->slb_nr; n++) {

        tmp64 = ldq_phys(sr_base);

        tmp = ldl_phys(sr_base + 8);

#if defined(DEBUG_SLB)

        if (loglevel != 0) {

            fprintf(logfile, "%s: seg %d " PADDRX " %016" PRIx64 " %08"

                    PRIx32 "\n", __func__, n, sr_base, tmp64, tmp);

        }

#endif

        if (slb_is_valid(tmp64)) {

            /* SLB entry is valid */

            switch (tmp64 & 0x0000000006000000ULL) {

            case 0x0000000000000000ULL:

                /* 256 MB segment */

                mask = 0xFFFFFFFFF0000000ULL;

                break;

            case 0x0000000002000000ULL:

                /* 1 TB segment */

                mask = 0xFFFF000000000000ULL;

                break;

            case 0x0000000004000000ULL:

            case 0x0000000006000000ULL:

                /* Reserved => segment is invalid */

                continue;

            }

            if ((eaddr & mask) == (tmp64 & mask)) {

                /* SLB match */

                *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;

                *page_mask = ~mask;

                *attr = tmp & 0xFF;

                ret = n;

                break;

            }

        }

        sr_base += 12;

    }

    return ret;

}

void ppc_slb_invalidate_all (CPUPPCState *env)

{

    target_phys_addr_t sr_base;

    uint64_t tmp64;

    int n, do_invalidate;

    do_invalidate = 0;

    sr_base = env->spr[SPR_ASR];

    /* XXX: Warning: slbia never invalidates the first segment */

    for (n = 1; n < env->slb_nr; n++) {

        tmp64 = ldq_phys(sr_base);

        if (slb_is_valid(tmp64)) {

            slb_invalidate(&tmp64);

            stq_phys(sr_base, tmp64);

            /* XXX: given the fact that segment size is 256 MB or 1TB,

             *      and we still don't have a tlb_flush_mask(env, n, mask)

             *      in Qemu, we just invalidate all TLBs

             */

            do_invalidate = 1;

        }

        sr_base += 12;

    }

    if (do_invalidate)

        tlb_flush(env, 1);

}

void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)

{

    target_phys_addr_t sr_base;

    target_ulong vsid, page_mask;

    uint64_t tmp64;

    int attr;

    int n;

    n = slb_lookup(env, T0, &vsid, &page_mask, &attr);

    if (n >= 0) {

        sr_base = env->spr[SPR_ASR];

        sr_base += 12 * n;

        tmp64 = ldq_phys(sr_base);

        if (slb_is_valid(tmp64)) {

            slb_invalidate(&tmp64);

            stq_phys(sr_base, tmp64);

            /* XXX: given the fact that segment size is 256 MB or 1TB,

             *      and we still don't have a tlb_flush_mask(env, n, mask)

             *      in Qemu, we just invalidate all TLBs

             */

            tlb_flush(env, 1);

        }

    }

}

target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)

{

    target_phys_addr_t sr_base;

    target_ulong rt;

    uint64_t tmp64;

    uint32_t tmp;

    sr_base = env->spr[SPR_ASR];

    sr_base += 12 * slb_nr;

    tmp64 = ldq_phys(sr_base);

    tmp = ldl_phys(sr_base + 8);

    if (tmp64 & 0x0000000008000000ULL) {

        /* SLB entry is valid */

        /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */

        rt = tmp >> 8;             /* 65:88 => 40:63 */

        rt |= (tmp64 & 0x7) << 24; /* 62:64 => 37:39 */

        /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */

        rt |= ((tmp >> 4) & 0xF) << 27;

    } else {

        rt = 0;

    }

#if defined(DEBUG_SLB)

    if (loglevel != 0) {

        fprintf(logfile, "%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d "

                ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt);

    }

#endif

    return rt;

}

void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs)

{

    target_phys_addr_t sr_base;

    uint64_t tmp64;

    uint32_t tmp;

    sr_base = env->spr[SPR_ASR];

    sr_base += 12 * slb_nr;

    /* Copy Rs bits 37:63 to SLB 62:88 */

    tmp = rs << 8;

    tmp64 = (rs >> 24) & 0x7;

    /* Copy Rs bits 33:36 to SLB 89:92 */

    tmp |= ((rs >> 27) & 0xF) << 4;

    /* Set the valid bit */

    tmp64 |= 1 << 27;

    /* Set ESID */

    tmp64 |= (uint32_t)slb_nr << 28;

#if defined(DEBUG_SLB)

    if (loglevel != 0) {

        fprintf(logfile, "%s: %d " ADDRX " => " PADDRX " %016" PRIx64 " %08"

                PRIx32 "\n", __func__, slb_nr, rs, sr_base, tmp64, tmp);

    }

#endif

    /* Write SLB entry to memory */

    stq_phys(sr_base, tmp64);

    stl_phys(sr_base + 8, tmp);

}

#endif /* defined(TARGET_PPC64) */

/* Perform segment based translation */

static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,

                                                    int sdr_sh,

                                                    target_phys_addr_t hash,

                                                    target_phys_addr_t mask)

{

    return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask);

}

static int get_segment (CPUState *env, mmu_ctx_t *ctx,

                        target_ulong eaddr, int rw, int type)

{

    target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;

    target_ulong sr, vsid, vsid_mask, pgidx, page_mask;

#if defined(TARGET_PPC64)

    int attr;

#endif

    int ds, vsid_sh, sdr_sh, pr;

    int ret, ret2;

    pr = msr_pr;