163 |
163 |
|
164 |
164 |
#endif
|
165 |
165 |
|
166 |
|
GEN_OP_LD(ub, T0)
|
167 |
|
GEN_OP_LD(b, T0)
|
168 |
|
GEN_OP_ST(b, T0)
|
169 |
|
GEN_OP_LD(uw, T0)
|
170 |
|
GEN_OP_LD(w, T0)
|
171 |
|
GEN_OP_ST(w, T0)
|
172 |
|
GEN_OP_LD(l, T0)
|
173 |
|
GEN_OP_ST(l, T0)
|
174 |
166 |
GEN_OP_LD(fl, FT0)
|
175 |
167 |
GEN_OP_ST(fl, FT0)
|
176 |
168 |
GEN_OP_LD(fq, DT0)
|
... | ... | |
441 |
433 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
442 |
434 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
443 |
435 |
tcg_gen_addi_i32(cpu_T[1], cpu_T[1], B3_0 * 4);
|
444 |
|
gen_op_stl_T0_T1(ctx);
|
|
436 |
tcg_gen_qemu_st32(cpu_T[0], cpu_T[1], ctx->memidx);
|
445 |
437 |
return;
|
446 |
438 |
case 0x5000: /* mov.l @(disp,Rm),Rn */
|
447 |
439 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
448 |
440 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B3_0 * 4);
|
449 |
|
gen_op_ldl_T0_T0(ctx);
|
|
441 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx);
|
450 |
442 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
451 |
443 |
return;
|
452 |
444 |
case 0xe000: /* mov #imm,Rn */
|
... | ... | |
454 |
446 |
return;
|
455 |
447 |
case 0x9000: /* mov.w @(disp,PC),Rn */
|
456 |
448 |
tcg_gen_movi_i32(cpu_T[0], ctx->pc + 4 + B7_0 * 2);
|
457 |
|
gen_op_ldw_T0_T0(ctx);
|
|
449 |
tcg_gen_qemu_ld16s(cpu_T[0], cpu_T[0], ctx->memidx);
|
458 |
450 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
459 |
451 |
return;
|
460 |
452 |
case 0xd000: /* mov.l @(disp,PC),Rn */
|
461 |
453 |
tcg_gen_movi_i32(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3);
|
462 |
|
gen_op_ldl_T0_T0(ctx);
|
|
454 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx);
|
463 |
455 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
464 |
456 |
return;
|
465 |
457 |
case 0x7000: /* add #imm,Rn */
|
... | ... | |
488 |
480 |
case 0x2000: /* mov.b Rm,@Rn */
|
489 |
481 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
490 |
482 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
491 |
|
gen_op_stb_T0_T1(ctx);
|
|
483 |
tcg_gen_qemu_st8(cpu_T[0], cpu_T[1], ctx->memidx);
|
492 |
484 |
return;
|
493 |
485 |
case 0x2001: /* mov.w Rm,@Rn */
|
494 |
486 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
495 |
487 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
496 |
|
gen_op_stw_T0_T1(ctx);
|
|
488 |
tcg_gen_qemu_st16(cpu_T[0], cpu_T[1], ctx->memidx);
|
497 |
489 |
return;
|
498 |
490 |
case 0x2002: /* mov.l Rm,@Rn */
|
499 |
491 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
500 |
492 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
501 |
|
gen_op_stl_T0_T1(ctx);
|
|
493 |
tcg_gen_qemu_st32(cpu_T[0], cpu_T[1], ctx->memidx);
|
502 |
494 |
return;
|
503 |
495 |
case 0x6000: /* mov.b @Rm,Rn */
|
504 |
496 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
505 |
|
gen_op_ldb_T0_T0(ctx);
|
|
497 |
tcg_gen_qemu_ld8s(cpu_T[0], cpu_T[0], ctx->memidx);
|
506 |
498 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
507 |
499 |
return;
|
508 |
500 |
case 0x6001: /* mov.w @Rm,Rn */
|
509 |
501 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
510 |
|
gen_op_ldw_T0_T0(ctx);
|
|
502 |
tcg_gen_qemu_ld16s(cpu_T[0], cpu_T[0], ctx->memidx);
|
511 |
503 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
512 |
504 |
return;
|
513 |
505 |
case 0x6002: /* mov.l @Rm,Rn */
|
514 |
506 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
515 |
|
gen_op_ldl_T0_T0(ctx);
|
|
507 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx);
|
516 |
508 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
517 |
509 |
return;
|
518 |
510 |
case 0x2004: /* mov.b Rm,@-Rn */
|
519 |
|
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
520 |
|
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)],
|
521 |
|
cpu_gregs[REG(B11_8)], 1); /* modify register status */
|
522 |
|
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
523 |
|
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)],
|
524 |
|
cpu_gregs[REG(B11_8)], 1); /* recover register status */
|
525 |
|
gen_op_stb_T0_T1(ctx); /* might cause re-execution */
|
|
511 |
tcg_gen_subi_i32(cpu_T[1], cpu_gregs[REG(B11_8)], 1);
|
|
512 |
tcg_gen_qemu_st8(cpu_gregs[REG(B7_4)], cpu_T[1], ctx->memidx); /* might cause re-execution */
|
526 |
513 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)],
|
527 |
|
cpu_gregs[REG(B11_8)], 1); /* modify register status */
|
|
514 |
cpu_gregs[REG(B11_8)], 1); /* modify register status */
|
528 |
515 |
return;
|
529 |
516 |
case 0x2005: /* mov.w Rm,@-Rn */
|
530 |
|
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
531 |
|
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)],
|
532 |
|
cpu_gregs[REG(B11_8)], 2);
|
533 |
|
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
534 |
|
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)],
|
535 |
|
cpu_gregs[REG(B11_8)], 2);
|
536 |
|
gen_op_stw_T0_T1(ctx);
|
|
517 |
tcg_gen_subi_i32(cpu_T[1], cpu_gregs[REG(B11_8)], 2);
|
|
518 |
tcg_gen_qemu_st16(cpu_gregs[REG(B7_4)], cpu_T[1], ctx->memidx);
|
537 |
519 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)],
|
538 |
520 |
cpu_gregs[REG(B11_8)], 2);
|
539 |
521 |
return;
|
540 |
522 |
case 0x2006: /* mov.l Rm,@-Rn */
|
541 |
|
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
542 |
|
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)],
|
543 |
|
cpu_gregs[REG(B11_8)], 4);
|
544 |
|
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
545 |
|
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)],
|
546 |
|
cpu_gregs[REG(B11_8)], 4);
|
547 |
|
gen_op_stl_T0_T1(ctx);
|
|
523 |
tcg_gen_subi_i32(cpu_T[1], cpu_gregs[REG(B11_8)], 4);
|
|
524 |
tcg_gen_qemu_st32(cpu_gregs[REG(B7_4)], cpu_T[1], ctx->memidx);
|
548 |
525 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)],
|
549 |
526 |
cpu_gregs[REG(B11_8)], 4);
|
550 |
527 |
return;
|
551 |
528 |
case 0x6004: /* mov.b @Rm+,Rn */
|
552 |
529 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
553 |
|
gen_op_ldb_T0_T0(ctx);
|
|
530 |
tcg_gen_qemu_ld8s(cpu_T[0], cpu_T[0], ctx->memidx);
|
554 |
531 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
555 |
532 |
if ( B11_8 != B7_4 )
|
556 |
533 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)],
|
... | ... | |
558 |
535 |
return;
|
559 |
536 |
case 0x6005: /* mov.w @Rm+,Rn */
|
560 |
537 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
561 |
|
gen_op_ldw_T0_T0(ctx);
|
|
538 |
tcg_gen_qemu_ld16s(cpu_T[0], cpu_T[0], ctx->memidx);
|
562 |
539 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
563 |
540 |
if ( B11_8 != B7_4 )
|
564 |
541 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)],
|
... | ... | |
566 |
543 |
return;
|
567 |
544 |
case 0x6006: /* mov.l @Rm+,Rn */
|
568 |
545 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
569 |
|
gen_op_ldl_T0_T0(ctx);
|
|
546 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx);
|
570 |
547 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
571 |
548 |
if ( B11_8 != B7_4 )
|
572 |
549 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)],
|
... | ... | |
576 |
553 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
577 |
554 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
578 |
555 |
tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]);
|
579 |
|
gen_op_stb_T0_T1(ctx);
|
|
556 |
tcg_gen_qemu_st8(cpu_T[0], cpu_T[1], ctx->memidx);
|
580 |
557 |
return;
|
581 |
558 |
case 0x0005: /* mov.w Rm,@(R0,Rn) */
|
582 |
559 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
583 |
560 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
584 |
561 |
tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]);
|
585 |
|
gen_op_stw_T0_T1(ctx);
|
|
562 |
tcg_gen_qemu_st16(cpu_T[0], cpu_T[1], ctx->memidx);
|
586 |
563 |
return;
|
587 |
564 |
case 0x0006: /* mov.l Rm,@(R0,Rn) */
|
588 |
565 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
589 |
566 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
590 |
567 |
tcg_gen_add_i32(cpu_T[1], cpu_T[1], cpu_gregs[REG(0)]);
|
591 |
|
gen_op_stl_T0_T1(ctx);
|
|
568 |
tcg_gen_qemu_st32(cpu_T[0], cpu_T[1], ctx->memidx);
|
592 |
569 |
return;
|
593 |
570 |
case 0x000c: /* mov.b @(R0,Rm),Rn */
|
594 |
571 |
tcg_gen_add_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(0)]);
|
595 |
|
gen_op_ldb_T0_T0(ctx);
|
|
572 |
tcg_gen_qemu_ld8s(cpu_T[0], cpu_T[0], ctx->memidx);
|
596 |
573 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
597 |
574 |
return;
|
598 |
575 |
case 0x000d: /* mov.w @(R0,Rm),Rn */
|
599 |
576 |
tcg_gen_add_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(0)]);
|
600 |
|
gen_op_ldw_T0_T0(ctx);
|
|
577 |
tcg_gen_qemu_ld16s(cpu_T[0], cpu_T[0], ctx->memidx);
|
601 |
578 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
602 |
579 |
return;
|
603 |
580 |
case 0x000e: /* mov.l @(R0,Rm),Rn */
|
604 |
581 |
tcg_gen_add_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(0)]);
|
605 |
|
gen_op_ldl_T0_T0(ctx);
|
|
582 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx);
|
606 |
583 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[0]);
|
607 |
584 |
return;
|
608 |
585 |
case 0x6008: /* swap.b Rm,Rn */
|
... | ... | |
737 |
714 |
return;
|
738 |
715 |
case 0x000f: /* mac.l @Rm+,@Rn+ */
|
739 |
716 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
740 |
|
gen_op_ldl_T0_T0(ctx);
|
|
717 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx);
|
741 |
718 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
|
742 |
719 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
743 |
|
gen_op_ldl_T0_T0(ctx);
|
|
720 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx);
|
744 |
721 |
tcg_gen_helper_0_2(helper_macl, cpu_T[0], cpu_T[1]);
|
745 |
722 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], cpu_gregs[REG(B7_4)], 4);
|
746 |
723 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
747 |
724 |
return;
|
748 |
725 |
case 0x400f: /* mac.w @Rm+,@Rn+ */
|
749 |
726 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
750 |
|
gen_op_ldl_T0_T0(ctx);
|
|
727 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx);
|
751 |
728 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
|
752 |
729 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
753 |
|
gen_op_ldl_T0_T0(ctx);
|
|
730 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx);
|
754 |
731 |
tcg_gen_helper_0_2(helper_macw, cpu_T[0], cpu_T[1]);
|
755 |
732 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 2);
|
756 |
733 |
tcg_gen_addi_i32(cpu_gregs[REG(B7_4)], cpu_gregs[REG(B7_4)], 2);
|
... | ... | |
951 |
928 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
|
952 |
929 |
tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr);
|
953 |
930 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
|
954 |
|
gen_op_ldub_T0_T0(ctx);
|
|
931 |
tcg_gen_qemu_ld8u(cpu_T[0], cpu_T[0], ctx->memidx);
|
955 |
932 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], B7_0);
|
956 |
|
gen_op_stb_T0_T1(ctx);
|
|
933 |
tcg_gen_qemu_st8(cpu_T[0], cpu_T[1], ctx->memidx);
|
957 |
934 |
return;
|
958 |
935 |
case 0x8b00: /* bf label */
|
959 |
936 |
CHECK_NOT_DELAY_SLOT
|
... | ... | |
984 |
961 |
case 0xc400: /* mov.b @(disp,GBR),R0 */
|
985 |
962 |
gen_op_stc_gbr_T0();
|
986 |
963 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0);
|
987 |
|
gen_op_ldb_T0_T0(ctx);
|
|
964 |
tcg_gen_qemu_ld8s(cpu_T[0], cpu_T[0], ctx->memidx);
|
988 |
965 |
tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]);
|
989 |
966 |
return;
|
990 |
967 |
case 0xc500: /* mov.w @(disp,GBR),R0 */
|
991 |
968 |
gen_op_stc_gbr_T0();
|
992 |
969 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0 * 2);
|
993 |
|
gen_op_ldw_T0_T0(ctx);
|
|
970 |
tcg_gen_qemu_ld16s(cpu_T[0], cpu_T[0], ctx->memidx);
|
994 |
971 |
tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]);
|
995 |
972 |
return;
|
996 |
973 |
case 0xc600: /* mov.l @(disp,GBR),R0 */
|
997 |
974 |
gen_op_stc_gbr_T0();
|
998 |
975 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0 * 4);
|
999 |
|
gen_op_ldl_T0_T0(ctx);
|
|
976 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx);
|
1000 |
977 |
tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]);
|
1001 |
978 |
return;
|
1002 |
979 |
case 0xc000: /* mov.b R0,@(disp,GBR) */
|
... | ... | |
1004 |
981 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0);
|
1005 |
982 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
|
1006 |
983 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
|
1007 |
|
gen_op_stb_T0_T1(ctx);
|
|
984 |
tcg_gen_qemu_st8(cpu_T[0], cpu_T[1], ctx->memidx);
|
1008 |
985 |
return;
|
1009 |
986 |
case 0xc100: /* mov.w R0,@(disp,GBR) */
|
1010 |
987 |
gen_op_stc_gbr_T0();
|
1011 |
988 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0 * 2);
|
1012 |
989 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
|
1013 |
990 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
|
1014 |
|
gen_op_stw_T0_T1(ctx);
|
|
991 |
tcg_gen_qemu_st16(cpu_T[0], cpu_T[1], ctx->memidx);
|
1015 |
992 |
return;
|
1016 |
993 |
case 0xc200: /* mov.l R0,@(disp,GBR) */
|
1017 |
994 |
gen_op_stc_gbr_T0();
|
1018 |
995 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0 * 4);
|
1019 |
996 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
|
1020 |
997 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
|
1021 |
|
gen_op_stl_T0_T1(ctx);
|
|
998 |
tcg_gen_qemu_st32(cpu_T[0], cpu_T[1], ctx->memidx);
|
1022 |
999 |
return;
|
1023 |
1000 |
case 0x8000: /* mov.b R0,@(disp,Rn) */
|
1024 |
1001 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
|
1025 |
1002 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B7_4)]);
|
1026 |
1003 |
tcg_gen_addi_i32(cpu_T[1], cpu_T[1], B3_0);
|
1027 |
|
gen_op_stb_T0_T1(ctx);
|
|
1004 |
tcg_gen_qemu_st8(cpu_T[0], cpu_T[1], ctx->memidx);
|
1028 |
1005 |
return;
|
1029 |
1006 |
case 0x8100: /* mov.w R0,@(disp,Rn) */
|
1030 |
1007 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
|
1031 |
1008 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B7_4)]);
|
1032 |
1009 |
tcg_gen_addi_i32(cpu_T[1], cpu_T[1], B3_0 * 2);
|
1033 |
|
gen_op_stw_T0_T1(ctx);
|
|
1010 |
tcg_gen_qemu_st16(cpu_T[0], cpu_T[1], ctx->memidx);
|
1034 |
1011 |
return;
|
1035 |
1012 |
case 0x8400: /* mov.b @(disp,Rn),R0 */
|
1036 |
1013 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
1037 |
1014 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B3_0);
|
1038 |
|
gen_op_ldb_T0_T0(ctx);
|
|
1015 |
tcg_gen_qemu_ld8s(cpu_T[0], cpu_T[0], ctx->memidx);
|
1039 |
1016 |
tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]);
|
1040 |
1017 |
return;
|
1041 |
1018 |
case 0x8500: /* mov.w @(disp,Rn),R0 */
|
1042 |
1019 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
|
1043 |
1020 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B3_0 * 2);
|
1044 |
|
gen_op_ldw_T0_T0(ctx);
|
|
1021 |
tcg_gen_qemu_ld16s(cpu_T[0], cpu_T[0], ctx->memidx);
|
1045 |
1022 |
tcg_gen_mov_i32(cpu_gregs[REG(0)], cpu_T[0]);
|
1046 |
1023 |
return;
|
1047 |
1024 |
case 0xc700: /* mova @(disp,PC),R0 */
|
... | ... | |
1055 |
1032 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
|
1056 |
1033 |
tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr);
|
1057 |
1034 |
tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
|
1058 |
|
gen_op_ldub_T0_T0(ctx);
|
|
1035 |
tcg_gen_qemu_ld8u(cpu_T[0], cpu_T[0], ctx->memidx);
|
1059 |
1036 |
tcg_gen_ori_i32(cpu_T[0], cpu_T[0], B7_0);
|
1060 |
|
gen_op_stb_T0_T1(ctx);
|
|
1037 |
tcg_gen_qemu_st8(cpu_T[0], cpu_T[1], ctx->memidx);
|
1061 |
1038 |
return;
|
1062 |
1039 |
case 0xc300: /* trapa #imm */
|
1063 |
1040 |
CHECK_NOT_DELAY_SLOT
|
... | ... | |
1073 |
1050 |
case 0xcc00: /* tst.b #imm,@(R0,GBR) */
|
1074 |
1051 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
|
1075 |
1052 |
tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr);
|
1076 |
|
gen_op_ldub_T0_T0(ctx);
|
|
1053 |
tcg_gen_qemu_ld8u(cpu_T[0], cpu_T[0], ctx->memidx);
|
1077 |
1054 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], B7_0);
|
1078 |
1055 |
gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0);
|
1079 |
1056 |
return;
|
... | ... | |
1084 |
1061 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
|
1085 |
1062 |
tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr);
|
1086 |
1063 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
|
1087 |
|
gen_op_ldub_T0_T0(ctx);
|
|
1064 |
tcg_gen_qemu_ld8u(cpu_T[0], cpu_T[0], ctx->memidx);
|
1088 |
1065 |
tcg_gen_xori_i32(cpu_T[0], cpu_T[0], B7_0);
|
1089 |
|
gen_op_stb_T0_T1(ctx);
|
|
1066 |
tcg_gen_qemu_st8(cpu_T[0], cpu_T[1], ctx->memidx);
|
1090 |
1067 |
return;
|
1091 |
1068 |
}
|
1092 |
1069 |
|
... | ... | |
1097 |
1074 |
return;
|
1098 |
1075 |
case 0x4087: /* ldc.l @Rm+,Rn_BANK */
|
1099 |
1076 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1100 |
|
gen_op_ldl_T0_T0(ctx);
|
|
1077 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx);
|
1101 |
1078 |
tcg_gen_mov_i32(cpu_gregs[ALTREG(B6_4)], cpu_T[0]);
|
1102 |
1079 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
1103 |
1080 |
return;
|
... | ... | |
1110 |
1087 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
1111 |
1088 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[ALTREG(B6_4)]);
|
1112 |
1089 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
1113 |
|
gen_op_stl_T0_T1(ctx);
|
|
1090 |
tcg_gen_qemu_st32(cpu_T[0], cpu_T[1], ctx->memidx);
|
1114 |
1091 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 4);
|
1115 |
1092 |
return;
|
1116 |
1093 |
}
|
... | ... | |
1161 |
1138 |
extrald \
|
1162 |
1139 |
return; \
|
1163 |
1140 |
case ldpnum: \
|
1164 |
|
tcg_gen_mov_i32 (cpu_T[0], cpu_gregs[REG(B11_8)]); \
|
1165 |
|
gen_op_ldl_T0_T0 (ctx); \
|
|
1141 |
tcg_gen_qemu_ld32s (cpu_T[0], cpu_gregs[REG(B11_8)], ctx->memidx); \
|
1166 |
1142 |
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], \
|
1167 |
1143 |
cpu_gregs[REG(B11_8)], 4); \
|
1168 |
1144 |
gen_op_##ldop##_T0_##reg (); \
|
... | ... | |
1174 |
1150 |
return; \
|
1175 |
1151 |
case stpnum: \
|
1176 |
1152 |
gen_op_##stop##_##reg##_T0 (); \
|
1177 |
|
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], \
|
1178 |
|
cpu_gregs[REG(B11_8)], 4); \
|
1179 |
|
tcg_gen_mov_i32 (cpu_T[1], cpu_gregs[REG(B11_8)]); \
|
1180 |
|
tcg_gen_addi_i32(cpu_gregs[REG(B11_8)], \
|
1181 |
|
cpu_gregs[REG(B11_8)], 4); \
|
1182 |
|
gen_op_stl_T0_T1 (ctx); \
|
|
1153 |
tcg_gen_subi_i32(cpu_T[1], cpu_gregs[REG(B11_8)], 4); \
|
|
1154 |
tcg_gen_qemu_st32 (cpu_T[0], cpu_T[1], ctx->memidx); \
|
1183 |
1155 |
tcg_gen_subi_i32(cpu_gregs[REG(B11_8)], \
|
1184 |
1156 |
cpu_gregs[REG(B11_8)], 4); \
|
1185 |
1157 |
return;
|
... | ... | |
1199 |
1171 |
case 0x00c3: /* movca.l R0,@Rm */
|
1200 |
1172 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
|
1201 |
1173 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]);
|
1202 |
|
gen_op_stl_T0_T1(ctx);
|
|
1174 |
tcg_gen_qemu_st32(cpu_T[0], cpu_T[1], ctx->memidx);
|
1203 |
1175 |
return;
|
1204 |
1176 |
case 0x0029: /* movt Rn */
|
1205 |
1177 |
tcg_gen_andi_i32(cpu_gregs[REG(B11_8)], cpu_sr, SR_T);
|
1206 |
1178 |
return;
|
1207 |
1179 |
case 0x0093: /* ocbi @Rn */
|
1208 |
1180 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1209 |
|
gen_op_ldl_T0_T0(ctx);
|
|
1181 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx);
|
1210 |
1182 |
return;
|
1211 |
1183 |
case 0x00a3: /* ocbp @Rn */
|
1212 |
1184 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1213 |
|
gen_op_ldl_T0_T0(ctx);
|
|
1185 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx);
|
1214 |
1186 |
return;
|
1215 |
1187 |
case 0x00b3: /* ocbwb @Rn */
|
1216 |
1188 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1217 |
|
gen_op_ldl_T0_T0(ctx);
|
|
1189 |
tcg_gen_qemu_ld32s(cpu_T[0], cpu_T[0], ctx->memidx);
|
1218 |
1190 |
return;
|
1219 |
1191 |
case 0x0083: /* pref @Rn */
|
1220 |
1192 |
return;
|
... | ... | |
1261 |
1233 |
case 0x401b: /* tas.b @Rn */
|
1262 |
1234 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
|
1263 |
1235 |
tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
|
1264 |
|
gen_op_ldub_T0_T0(ctx);
|
|
1236 |
tcg_gen_qemu_ld8u(cpu_T[0], cpu_T[0], ctx->memidx);
|
1265 |
1237 |
gen_cmp_imm(TCG_COND_EQ, cpu_T[0], 0);
|
1266 |
1238 |
tcg_gen_ori_i32(cpu_T[0], cpu_T[0], 0x80);
|
1267 |
|
gen_op_stb_T0_T1(ctx);
|
|
1239 |
tcg_gen_qemu_st8(cpu_T[0], cpu_T[1], ctx->memidx);
|
1268 |
1240 |
return;
|
1269 |
1241 |
case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
|
1270 |
1242 |
gen_op_movl_fpul_FT0();
|