Statistics
| Branch: | Revision:

root / tcg / ppc / tcg-target.c @ fa4fbfb9

History | View | Annotate | Download (44 kB)

1
/*
2
 * Tiny Code Generator for QEMU
3
 *
4
 * Copyright (c) 2008 Fabrice Bellard
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
 * THE SOFTWARE.
23
 */
24

    
25
static uint8_t *tb_ret_addr;
26
static uint8_t *udiv_addr;
27
static uint8_t *div_addr;
28

    
29
#define FAST_PATH
30
#if TARGET_PHYS_ADDR_BITS <= 32
31
#define ADDEND_OFFSET 0
32
#else
33
#define ADDEND_OFFSET 4
34
#endif
35

    
36
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
37
    "r0",
38
    "r1",
39
    "rp",
40
    "r3",
41
    "r4",
42
    "r5",
43
    "r6",
44
    "r7",
45
    "r8",
46
    "r9",
47
    "r10",
48
    "r11",
49
    "r12",
50
    "r13",
51
    "r14",
52
    "r15",
53
    "r16",
54
    "r17",
55
    "r18",
56
    "r19",
57
    "r20",
58
    "r21",
59
    "r22",
60
    "r23",
61
    "r24",
62
    "r25",
63
    "r26",
64
    "r27",
65
    "r28",
66
    "r29",
67
    "r30",
68
    "r31"
69
};
70

    
71
static const int tcg_target_reg_alloc_order[] = {
72
    TCG_REG_R0,
73
    TCG_REG_R1,
74
    TCG_REG_R2,
75
    TCG_REG_R3,
76
    TCG_REG_R4,
77
    TCG_REG_R5,
78
    TCG_REG_R6,
79
    TCG_REG_R7,
80
    TCG_REG_R8,
81
    TCG_REG_R9,
82
    TCG_REG_R10,
83
    TCG_REG_R11,
84
    TCG_REG_R12,
85
    TCG_REG_R13,
86
    TCG_REG_R14,
87
    TCG_REG_R15,
88
    TCG_REG_R16,
89
    TCG_REG_R17,
90
    TCG_REG_R18,
91
    TCG_REG_R19,
92
    TCG_REG_R20,
93
    TCG_REG_R21,
94
    TCG_REG_R22,
95
    TCG_REG_R23,
96
    TCG_REG_R24,
97
    TCG_REG_R25,
98
    TCG_REG_R26,
99
    TCG_REG_R27,
100
    TCG_REG_R28,
101
    TCG_REG_R29,
102
    TCG_REG_R30,
103
    TCG_REG_R31
104
};
105

    
106
static const int tcg_target_call_iarg_regs[] = {
107
    TCG_REG_R3,
108
    TCG_REG_R4,
109
    TCG_REG_R5,
110
    TCG_REG_R6,
111
    TCG_REG_R7,
112
    TCG_REG_R8,
113
    TCG_REG_R9,
114
    TCG_REG_R10
115
};
116

    
117
static const int tcg_target_call_oarg_regs[2] = {
118
    TCG_REG_R3,
119
    TCG_REG_R4
120
};
121

    
122
static const int tcg_target_callee_save_regs[] = {
123
    TCG_REG_R13,                /* should r13 be saved? */
124
    TCG_REG_R14,
125
    TCG_REG_R15,
126
    TCG_REG_R16,
127
    TCG_REG_R17,
128
    TCG_REG_R18,
129
    TCG_REG_R19,
130
    TCG_REG_R20,
131
    TCG_REG_R21,
132
    TCG_REG_R22,
133
    TCG_REG_R23,
134
    TCG_REG_R28,
135
    TCG_REG_R29,
136
    TCG_REG_R30,
137
    TCG_REG_R31
138
};
139

    
140
static const int div_save_regs[] = {
141
    TCG_REG_R4,
142
    TCG_REG_R5,
143
    TCG_REG_R7,
144
    TCG_REG_R8,
145
    TCG_REG_R9,
146
    TCG_REG_R10,
147
    TCG_REG_R11,
148
    TCG_REG_R12,
149
    TCG_REG_R13,                /* should r13 be saved? */
150
    TCG_REG_R24,
151
    TCG_REG_R25,
152
    TCG_REG_R26,
153
    TCG_REG_R27,
154
};
155

    
156
static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
157
{
158
    tcg_target_long disp;
159

    
160
    disp = target - (tcg_target_long) pc;
161
    if ((disp << 6) >> 6 != disp)
162
        tcg_abort ();
163

    
164
    return disp & 0x3fffffc;
165
}
166

    
167
static void reloc_pc24 (void *pc, tcg_target_long target)
168
{
169
    *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
170
        | reloc_pc24_val (pc, target);
171
}
172

    
173
static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
174
{
175
    tcg_target_long disp;
176

    
177
    disp = target - (tcg_target_long) pc;
178
    if (disp != (int16_t) disp)
179
        tcg_abort ();
180

    
181
    return disp & 0xfffc;
182
}
183

    
184
static void reloc_pc14 (void *pc, tcg_target_long target)
185
{
186
    *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
187
        | reloc_pc14_val (pc, target);
188
}
189

    
190
static void patch_reloc(uint8_t *code_ptr, int type,
191
                        tcg_target_long value, tcg_target_long addend)
192
{
193
    value += addend;
194
    switch (type) {
195
    case R_PPC_REL14:
196
        reloc_pc14 (code_ptr, value);
197
        break;
198
    case R_PPC_REL24:
199
        reloc_pc24 (code_ptr, value);
200
        break;
201
    default:
202
        tcg_abort();
203
    }
204
}
205

    
206
/* maximum number of register used for input function arguments */
207
static int tcg_target_get_call_iarg_regs_count(int flags)
208
{
209
    return sizeof (tcg_target_call_iarg_regs) / sizeof (tcg_target_call_iarg_regs[0]);
210
}
211

    
212
/* parse target specific constraints */
213
static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
214
{
215
    const char *ct_str;
216

    
217
    ct_str = *pct_str;
218
    switch (ct_str[0]) {
219
    case 'A': case 'B': case 'C': case 'D':
220
        ct->ct |= TCG_CT_REG;
221
        tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
222
        break;
223
    case 'r':
224
        ct->ct |= TCG_CT_REG;
225
        tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
226
        break;
227
    case 'L':                   /* qemu_ld constraint */
228
        ct->ct |= TCG_CT_REG;
229
        tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
230
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
231
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
232
        break;
233
    case 'K':                   /* qemu_st[8..32] constraint */
234
        ct->ct |= TCG_CT_REG;
235
        tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
236
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
237
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
238
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
239
#if TARGET_LONG_BITS == 64
240
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
241
#endif
242
        break;
243
    case 'M':                   /* qemu_st64 constraint */
244
        ct->ct |= TCG_CT_REG;
245
        tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
246
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
247
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
248
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
249
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
250
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
251
        break;
252
    default:
253
        return -1;
254
    }
255
    ct_str++;
256
    *pct_str = ct_str;
257
    return 0;
258
}
259

    
260
/* test if a constant matches the constraint */
261
static int tcg_target_const_match(tcg_target_long val,
262
                                  const TCGArgConstraint *arg_ct)
263
{
264
    int ct;
265

    
266
    ct = arg_ct->ct;
267
    if (ct & TCG_CT_CONST)
268
        return 1;
269
    return 0;
270
}
271

    
272
#define OPCD(opc) ((opc)<<26)
273
#define XO31(opc) (OPCD(31)|((opc)<<1))
274
#define XO19(opc) (OPCD(19)|((opc)<<1))
275

    
276
#define B      OPCD(18)
277
#define BC     OPCD(16)
278
#define LBZ    OPCD(34)
279
#define LHZ    OPCD(40)
280
#define LHA    OPCD(42)
281
#define LWZ    OPCD(32)
282
#define STB    OPCD(38)
283
#define STH    OPCD(44)
284
#define STW    OPCD(36)
285

    
286
#define ADDI   OPCD(14)
287
#define ADDIS  OPCD(15)
288
#define ORI    OPCD(24)
289
#define ORIS   OPCD(25)
290
#define XORI   OPCD(26)
291
#define XORIS  OPCD(27)
292
#define ANDI   OPCD(28)
293
#define ANDIS  OPCD(29)
294
#define MULLI  OPCD( 7)
295
#define CMPLI  OPCD(10)
296
#define CMPI   OPCD(11)
297

    
298
#define LWZU   OPCD(33)
299
#define STWU   OPCD(37)
300

    
301
#define RLWINM OPCD(21)
302

    
303
#define BCLR   XO19(16)
304
#define BCCTR  XO19(528)
305
#define CRAND  XO19(257)
306

    
307
#define EXTSB  XO31(954)
308
#define EXTSH  XO31(922)
309
#define ADD    XO31(266)
310
#define ADDE   XO31(138)
311
#define ADDC   XO31( 10)
312
#define AND    XO31( 28)
313
#define SUBF   XO31( 40)
314
#define SUBFC  XO31(  8)
315
#define SUBFE  XO31(136)
316
#define OR     XO31(444)
317
#define XOR    XO31(316)
318
#define MULLW  XO31(235)
319
#define MULHWU XO31( 11)
320
#define DIVW   XO31(491)
321
#define DIVWU  XO31(459)
322
#define CMP    XO31(  0)
323
#define CMPL   XO31( 32)
324
#define LHBRX  XO31(790)
325
#define LWBRX  XO31(534)
326
#define STHBRX XO31(918)
327
#define STWBRX XO31(662)
328
#define MFSPR  XO31(339)
329
#define MTSPR  XO31(467)
330
#define SRAWI  XO31(824)
331
#define NEG    XO31(104)
332

    
333
#define LBZX   XO31( 87)
334
#define LHZX   XO31(276)
335
#define LHAX   XO31(343)
336
#define LWZX   XO31( 23)
337
#define STBX   XO31(215)
338
#define STHX   XO31(407)
339
#define STWX   XO31(151)
340

    
341
#define SPR(a,b) ((((a)<<5)|(b))<<11)
342
#define LR     SPR(8, 0)
343
#define CTR    SPR(9, 0)
344

    
345
#define SLW    XO31( 24)
346
#define SRW    XO31(536)
347
#define SRAW   XO31(792)
348

    
349
#define LMW    OPCD(46)
350
#define STMW   OPCD(47)
351

    
352
#define TW     XO31(4)
353
#define TRAP   (TW | TO (31))
354

    
355
#define RT(r) ((r)<<21)
356
#define RS(r) ((r)<<21)
357
#define RA(r) ((r)<<16)
358
#define RB(r) ((r)<<11)
359
#define TO(t) ((t)<<21)
360
#define SH(s) ((s)<<11)
361
#define MB(b) ((b)<<6)
362
#define ME(e) ((e)<<1)
363
#define BO(o) ((o)<<21)
364

    
365
#define LK    1
366

    
367
#define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
368
#define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
369

    
370
#define BF(n)    ((n)<<23)
371
#define BI(n, c) (((c)+((n)*4))<<16)
372
#define BT(n, c) (((c)+((n)*4))<<21)
373
#define BA(n, c) (((c)+((n)*4))<<16)
374
#define BB(n, c) (((c)+((n)*4))<<11)
375

    
376
#define BO_COND_TRUE  BO (12)
377
#define BO_COND_FALSE BO (4)
378
#define BO_ALWAYS     BO (20)
379

    
380
enum {
381
    CR_LT,
382
    CR_GT,
383
    CR_EQ,
384
    CR_SO
385
};
386

    
387
static const uint32_t tcg_to_bc[10] = {
388
    [TCG_COND_EQ]  = BC | BI (7, CR_EQ) | BO_COND_TRUE,
389
    [TCG_COND_NE]  = BC | BI (7, CR_EQ) | BO_COND_FALSE,
390
    [TCG_COND_LT]  = BC | BI (7, CR_LT) | BO_COND_TRUE,
391
    [TCG_COND_GE]  = BC | BI (7, CR_LT) | BO_COND_FALSE,
392
    [TCG_COND_LE]  = BC | BI (7, CR_GT) | BO_COND_FALSE,
393
    [TCG_COND_GT]  = BC | BI (7, CR_GT) | BO_COND_TRUE,
394
    [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
395
    [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
396
    [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
397
    [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
398
};
399

    
400
static void tcg_out_mov(TCGContext *s, int ret, int arg)
401
{
402
    tcg_out32 (s, OR | SAB (arg, ret, arg));
403
}
404

    
405
static void tcg_out_movi(TCGContext *s, TCGType type,
406
                         int ret, tcg_target_long arg)
407
{
408
    if (arg == (int16_t) arg)
409
        tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
410
    else {
411
        tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
412
        if (arg & 0xffff)
413
            tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
414
    }
415
}
416

    
417
static void tcg_out_ldst (TCGContext *s, int ret, int addr,
418
                          int offset, int op1, int op2)
419
{
420
    if (offset == (int16_t) offset)
421
        tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
422
    else {
423
        tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
424
        tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
425
    }
426
}
427

    
428
static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
429
{
430
    tcg_target_long disp;
431

    
432
    disp = target - (tcg_target_long) s->code_ptr;
433
    if ((disp << 6) >> 6 == disp)
434
        tcg_out32 (s, B | disp | mask);
435
    else {
436
        tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
437
        tcg_out32 (s, MTSPR | RS (0) | CTR);
438
        tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
439
    }
440
}
441

    
442
#if defined(CONFIG_SOFTMMU)
443
extern void __ldb_mmu(void);
444
extern void __ldw_mmu(void);
445
extern void __ldl_mmu(void);
446
extern void __ldq_mmu(void);
447

    
448
extern void __stb_mmu(void);
449
extern void __stw_mmu(void);
450
extern void __stl_mmu(void);
451
extern void __stq_mmu(void);
452

    
453
static void *qemu_ld_helpers[4] = {
454
    __ldb_mmu,
455
    __ldw_mmu,
456
    __ldl_mmu,
457
    __ldq_mmu,
458
};
459

    
460
static void *qemu_st_helpers[4] = {
461
    __stb_mmu,
462
    __stw_mmu,
463
    __stl_mmu,
464
    __stq_mmu,
465
};
466
#endif
467

    
468
static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
469
{
470
    int addr_reg, data_reg, data_reg2, r0, mem_index, s_bits, bswap;
471
#ifdef CONFIG_SOFTMMU
472
    int r1, r2;
473
    void *label1_ptr, *label2_ptr;
474
#endif
475
#if TARGET_LONG_BITS == 64
476
    int addr_reg2;
477
#endif
478

    
479
    data_reg = *args++;
480
    if (opc == 3)
481
        data_reg2 = *args++;
482
    else
483
        data_reg2 = 0;
484
    addr_reg = *args++;
485
#if TARGET_LONG_BITS == 64
486
    addr_reg2 = *args++;
487
#endif
488
    mem_index = *args;
489
    s_bits = opc & 3;
490

    
491
#ifdef CONFIG_SOFTMMU
492
    r0 = 3;
493
    r1 = 4;
494
    r2 = 0;
495

    
496
    tcg_out32 (s, (RLWINM
497
                   | RA (r0)
498
                   | RS (addr_reg)
499
                   | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
500
                   | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
501
                   | ME (31 - CPU_TLB_ENTRY_BITS)
502
                   )
503
        );
504
    tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
505
    tcg_out32 (s, (LWZU
506
                   | RT (r1)
507
                   | RA (r0)
508
                   | offsetof (CPUState, tlb_table[mem_index][0].addr_read)
509
                   )
510
        );
511
    tcg_out32 (s, (RLWINM
512
                   | RA (r2)
513
                   | RS (addr_reg)
514
                   | SH (0)
515
                   | MB ((32 - s_bits) & 31)
516
                   | ME (31 - TARGET_PAGE_BITS)
517
                   )
518
        );
519

    
520
    tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
521
#if TARGET_LONG_BITS == 64
522
    tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
523
    tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
524
    tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
525
#endif
526

    
527
    label1_ptr = s->code_ptr;
528
#ifdef FAST_PATH
529
    tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
530
#endif
531

    
532
    /* slow path */
533
#if TARGET_LONG_BITS == 32
534
    tcg_out_mov (s, 3, addr_reg);
535
    tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
536
#else
537
    tcg_out_mov (s, 3, addr_reg2);
538
    tcg_out_mov (s, 4, addr_reg);
539
    tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
540
#endif
541

    
542
    tcg_out_b (s, LK, (tcg_target_long) qemu_ld_helpers[s_bits]);
543
    switch (opc) {
544
    case 0|4:
545
        tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
546
        break;
547
    case 1|4:
548
        tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
549
        break;
550
    case 0:
551
    case 1:
552
    case 2:
553
        if (data_reg != 3)
554
            tcg_out_mov (s, data_reg, 3);
555
        break;
556
    case 3:
557
        if (data_reg == 3) {
558
            if (data_reg2 == 4) {
559
                tcg_out_mov (s, 0, 4);
560
                tcg_out_mov (s, 4, 3);
561
                tcg_out_mov (s, 3, 0);
562
            }
563
            else {
564
                tcg_out_mov (s, data_reg2, 3);
565
                tcg_out_mov (s, 3, 4);
566
            }
567
        }
568
        else {
569
            if (data_reg != 4) tcg_out_mov (s, data_reg, 4);
570
            if (data_reg2 != 3) tcg_out_mov (s, data_reg2, 3);
571
        }
572
        break;
573
    }
574
    label2_ptr = s->code_ptr;
575
    tcg_out32 (s, B);
576

    
577
    /* label1: fast path */
578
#ifdef FAST_PATH
579
    reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
580
#endif
581

    
582
    /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
583
    tcg_out32 (s, (LWZ
584
                   | RT (r0)
585
                   | RA (r0)
586
                   | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
587
                      - offsetof (CPUTLBEntry, addr_read))
588
                   ));
589
    /* r0 = env->tlb_table[mem_index][index].addend */
590
    tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
591
    /* r0 = env->tlb_table[mem_index][index].addend + addr */
592

    
593
#else  /* !CONFIG_SOFTMMU */
594
    r0 = addr_reg;
595
#endif
596

    
597
#ifdef TARGET_WORDS_BIGENDIAN
598
    bswap = 0;
599
#else
600
    bswap = 1;
601
#endif
602
    switch (opc) {
603
    default:
604
    case 0:
605
        tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
606
        break;
607
    case 0|4:
608
        tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
609
        tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
610
        break;
611
    case 1:
612
        if (bswap) tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
613
        else tcg_out32 (s, LHZ | RT (data_reg) | RA (r0));
614
        break;
615
    case 1|4:
616
        if (bswap) {
617
            tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
618
            tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
619
        }
620
        else tcg_out32 (s, LHA | RT (data_reg) | RA (r0));
621
        break;
622
    case 2:
623
        if (bswap) tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
624
        else tcg_out32 (s, LWZ | RT (data_reg)| RA (r0));
625
        break;
626
    case 3:
627
        if (bswap) {
628
            if (r0 == data_reg) {
629
                tcg_out32 (s, LWBRX | RT (0) | RB (r0));
630
                tcg_out32 (s, ADDI | RT (r0) | RA (r0) |  4);
631
                tcg_out32 (s, LWBRX | RT (data_reg2) | RB (r0));
632
                tcg_out_mov (s, data_reg, 0);
633
            }
634
            else {
635
                tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
636
                tcg_out32 (s, ADDI | RT (r0) | RA (r0) |  4);
637
                tcg_out32 (s, LWBRX | RT (data_reg2) | RB (r0));
638
            }
639
        }
640
        else {
641
            if (r0 == data_reg2) {
642
                tcg_out32 (s, LWZ | RT (0) | RA (r0));
643
                tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
644
                tcg_out_mov (s, data_reg2, 0);
645
            }
646
            else {
647
                tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
648
                tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
649
            }
650
        }
651
        break;
652
    }
653

    
654
#ifdef CONFIG_SOFTMMU
655
    reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
656
#endif
657
}
658

    
659
static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
660
{
661
    int addr_reg, r0, r1, data_reg, data_reg2, mem_index, bswap;
662
#ifdef CONFIG_SOFTMMU
663
    int r2, ir;
664
    void *label1_ptr, *label2_ptr;
665
#endif
666
#if TARGET_LONG_BITS == 64
667
    int addr_reg2;
668
#endif
669

    
670
    data_reg = *args++;
671
    if (opc == 3)
672
        data_reg2 = *args++;
673
    else
674
        data_reg2 = 0;
675
    addr_reg = *args++;
676
#if TARGET_LONG_BITS == 64
677
    addr_reg2 = *args++;
678
#endif
679
    mem_index = *args;
680

    
681
#ifdef CONFIG_SOFTMMU
682
    r0 = 3;
683
    r1 = 4;
684
    r2 = 0;
685

    
686
    tcg_out32 (s, (RLWINM
687
                   | RA (r0)
688
                   | RS (addr_reg)
689
                   | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
690
                   | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
691
                   | ME (31 - CPU_TLB_ENTRY_BITS)
692
                   )
693
        );
694
    tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
695
    tcg_out32 (s, (LWZU
696
                   | RT (r1)
697
                   | RA (r0)
698
                   | offsetof (CPUState, tlb_table[mem_index][0].addr_write)
699
                   )
700
        );
701
    tcg_out32 (s, (RLWINM
702
                   | RA (r2)
703
                   | RS (addr_reg)
704
                   | SH (0)
705
                   | MB ((32 - opc) & 31)
706
                   | ME (31 - TARGET_PAGE_BITS)
707
                   )
708
        );
709

    
710
    tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
711
#if TARGET_LONG_BITS == 64
712
    tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
713
    tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
714
    tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
715
#endif
716

    
717
    label1_ptr = s->code_ptr;
718
#ifdef FAST_PATH
719
    tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
720
#endif
721

    
722
    /* slow path */
723
#if TARGET_LONG_BITS == 32
724
    tcg_out_mov (s, 3, addr_reg);
725
    ir = 4;
726
#else
727
    tcg_out_mov (s, 3, addr_reg2);
728
    tcg_out_mov (s, 4, addr_reg);
729
    ir = 5;
730
#endif
731

    
732
    switch (opc) {
733
    case 0:
734
        tcg_out32 (s, (RLWINM
735
                       | RA (ir)
736
                       | RS (data_reg)
737
                       | SH (0)
738
                       | MB (24)
739
                       | ME (31)));
740
        break;
741
    case 1:
742
        tcg_out32 (s, (RLWINM
743
                       | RA (ir)
744
                       | RS (data_reg)
745
                       | SH (0)
746
                       | MB (16)
747
                       | ME (31)));
748
        break;
749
    case 2:
750
        tcg_out_mov (s, ir, data_reg);
751
        break;
752
    case 3:
753
        tcg_out_mov (s, 5, data_reg2);
754
        tcg_out_mov (s, 6, data_reg);
755
        ir = 6;
756
        break;
757
    }
758
    ir++;
759

    
760
    tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
761
    tcg_out_b (s, LK, (tcg_target_long) qemu_st_helpers[opc]);
762
    label2_ptr = s->code_ptr;
763
    tcg_out32 (s, B);
764

    
765
    /* label1: fast path */
766
#ifdef FAST_PATH
767
    reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
768
#endif
769

    
770
    tcg_out32 (s, (LWZ
771
                   | RT (r0)
772
                   | RA (r0)
773
                   | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
774
                      - offsetof (CPUTLBEntry, addr_write))
775
                   ));
776
    /* r0 = env->tlb_table[mem_index][index].addend */
777
    tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
778
    /* r0 = env->tlb_table[mem_index][index].addend + addr */
779

    
780
#else  /* !CONFIG_SOFTMMU */
781
    r1 = 4;
782
    r0 = addr_reg;
783
#endif
784

    
785
#ifdef TARGET_WORDS_BIGENDIAN
786
    bswap = 0;
787
#else
788
    bswap = 1;
789
#endif
790
    switch (opc) {
791
    case 0:
792
        tcg_out32 (s, STB | RS (data_reg) | RA (r0));
793
        break;
794
    case 1:
795
        if (bswap) tcg_out32 (s, STHBRX | RS (data_reg) | RA (0) | RB (r0));
796
        else tcg_out32 (s, STH | RS (data_reg) | RA (r0));
797
        break;
798
    case 2:
799
        if (bswap) tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
800
        else tcg_out32 (s, STW | RS (data_reg) | RA (r0));
801
        break;
802
    case 3:
803
        if (bswap) {
804
            tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
805
            tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
806
            tcg_out32 (s, STWBRX | RS (data_reg2) | RA (0) | RB (r1));
807
        }
808
        else {
809
            tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
810
            tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
811
        }
812
        break;
813
    }
814

    
815
#ifdef CONFIG_SOFTMMU
816
    reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
817
#endif
818
}
819

    
820
static uint64_t ppc_udiv_helper (uint64_t a, uint32_t b)
821
{
822
    uint64_t rem, quo;
823
    quo = a / b;
824
    rem = a % b;
825
    return (rem << 32) | (uint32_t) quo;
826
}
827

    
828
static uint64_t ppc_div_helper (int64_t a, int32_t b)
829
{
830
    int64_t rem, quo;
831
    quo = a / b;
832
    rem = a % b;
833
    return (rem << 32) | (uint32_t) quo;
834
}
835

    
836
void tcg_target_qemu_prologue (TCGContext *s)
837
{
838
    int i, j, frame_size;
839

    
840
    frame_size = 0
841
        + 4                     /* back chain */
842
        + 4                     /* LR */
843
        + TCG_STATIC_CALL_ARGS_SIZE
844
        + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
845
        ;
846
    frame_size = (frame_size + 15) & ~15;
847

    
848
    tcg_out32 (s, MFSPR | RT (0) | LR);
849
    tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
850
    for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
851
        tcg_out32 (s, (STW
852
                       | RS (tcg_target_callee_save_regs[i])
853
                       | RA (1)
854
                       | (i * 4 + 8 + TCG_STATIC_CALL_ARGS_SIZE)
855
                       )
856
            );
857
    tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size - 4));
858

    
859
    tcg_out32 (s, MTSPR | RS (3) | CTR);
860
    tcg_out32 (s, BCCTR | BO_ALWAYS);
861
    tb_ret_addr = s->code_ptr;
862

    
863
    for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
864
        tcg_out32 (s, (LWZ
865
                       | RT (tcg_target_callee_save_regs[i])
866
                       | RA (1)
867
                       | (i * 4 + 8 + TCG_STATIC_CALL_ARGS_SIZE)
868
                       )
869
            );
870
    tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size - 4));
871
    tcg_out32 (s, MTSPR | RS (0) | LR);
872
    tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
873
    tcg_out32 (s, BCLR | BO_ALWAYS);
874

    
875
    /* div trampolines */
876
    for (j = 0; j < 2; ++j) {
877
        tcg_target_long target;
878

    
879
        frame_size = 8 + ARRAY_SIZE (div_save_regs) * 4;
880
        frame_size = (frame_size + 15) & ~15;
881

    
882
        if (j == 0) {
883
            target = (tcg_target_long) ppc_udiv_helper;
884
            udiv_addr = s->code_ptr;
885
        }
886
        else {
887
            target = (tcg_target_long) ppc_div_helper;
888
            div_addr = s->code_ptr;
889
        }
890

    
891
        tcg_out32 (s, MFSPR | RT (0) | LR);
892
        tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
893
        for (i = 0; i < ARRAY_SIZE (div_save_regs); ++i)
894
            tcg_out32 (s, (STW
895
                           | RS (div_save_regs[i])
896
                           | RA (1)
897
                           | (i * 4 + 8)
898
                           )
899
                );
900
        tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size - 4));
901
        tcg_out_mov (s, 4, 6);
902
        tcg_out_b (s, LK, target);
903
        tcg_out_mov (s, 6, 4);
904

    
905
        for (i = 0; i < ARRAY_SIZE (div_save_regs); ++i)
906
            tcg_out32 (s, (LWZ
907
                           | RT (div_save_regs[i])
908
                           | RA (1)
909
                           | (i * 4 + 8)
910
                           )
911
                );
912
        tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size - 4));
913
        tcg_out32 (s, MTSPR | RS (0) | LR);
914
        tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
915
        tcg_out32 (s, BCLR | BO_ALWAYS);
916
    }
917
}
918

    
919
static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
920
                        tcg_target_long arg2)
921
{
922
    tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
923
}
924

    
925
static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
926
                        tcg_target_long arg2)
927
{
928
    tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
929
}
930

    
931
static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
932
{
933
    if (!si && rt == ra)
934
        return;
935

    
936
    if (si == (int16_t) si)
937
        tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
938
    else {
939
        uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
940
        tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
941
        tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
942
    }
943
}
944

    
945
static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
946
{
947
    ppc_addi (s, reg, reg, val);
948
}
949

    
950
static void tcg_out_brcond(TCGContext *s, int cond,
951
                           TCGArg arg1, TCGArg arg2, int const_arg2,
952
                           int label_index)
953
{
954
    TCGLabel *l = &s->labels[label_index];
955
    int imm;
956
    uint32_t op;
957

    
958
    switch (cond) {
959
    case TCG_COND_EQ:
960
    case TCG_COND_NE:
961
        if (const_arg2) {
962
            if ((int16_t) arg2 == arg2) {
963
                op = CMPI;
964
                imm = 1;
965
                break;
966
            }
967
            else if ((uint16_t) arg2 == arg2) {
968
                op = CMPLI;
969
                imm = 1;
970
                break;
971
            }
972
        }
973
        op = CMPL;
974
        imm = 0;
975
        break;
976

    
977
    case TCG_COND_LT:
978
    case TCG_COND_GE:
979
    case TCG_COND_LE:
980
    case TCG_COND_GT:
981
        if (const_arg2) {
982
            if ((int16_t) arg2 == arg2) {
983
                op = CMPI;
984
                imm = 1;
985
                break;
986
            }
987
        }
988
        op = CMP;
989
        imm = 0;
990
        break;
991

    
992
    case TCG_COND_LTU:
993
    case TCG_COND_GEU:
994
    case TCG_COND_LEU:
995
    case TCG_COND_GTU:
996
        if (const_arg2) {
997
            if ((uint16_t) arg2 == arg2) {
998
                op = CMPLI;
999
                imm = 1;
1000
                break;
1001
            }
1002
        }
1003
        op = CMPL;
1004
        imm = 0;
1005
        break;
1006

    
1007
    default:
1008
        tcg_abort ();
1009
    }
1010
    op |= BF (7);
1011

    
1012
    if (imm)
1013
        tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
1014
    else {
1015
        if (const_arg2) {
1016
            tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1017
            tcg_out32 (s, op | RA (arg1) | RB (0));
1018
        }
1019
        else
1020
            tcg_out32 (s, op | RA (arg1) | RB (arg2));
1021
    }
1022

    
1023
    if (l->has_value)
1024
        tcg_out32 (s, tcg_to_bc[cond] | reloc_pc14_val (s->code_ptr,
1025
                                                        l->u.value));
1026
    else {
1027
        uint16_t val = *(uint16_t *) &s->code_ptr[2];
1028

    
1029
        /* Thanks to Andrzej Zaborowski */
1030
        tcg_out32 (s, tcg_to_bc[cond] | (val & 0xfffc));
1031
        tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1032
    }
1033
}
1034

    
1035
/* brcond2 is taken verbatim from i386 tcg-target */
1036
/* XXX: we implement it at the target level to avoid having to
1037
   handle cross basic blocks temporaries */
1038
static void tcg_out_brcond2(TCGContext *s,
1039
                            const TCGArg *args, const int *const_args)
1040
{
1041
    int label_next;
1042
    label_next = gen_new_label();
1043
    switch(args[4]) {
1044
    case TCG_COND_EQ:
1045
        tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next);
1046
        tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3], args[5]);
1047
        break;
1048
    case TCG_COND_NE:
1049
        tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], args[5]);
1050
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], args[5]);
1051
        break;
1052
    case TCG_COND_LT:
1053
        tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
1054
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
1055
        tcg_out_brcond(s, TCG_COND_LT, args[0], args[2], const_args[2], args[5]);
1056
        break;
1057
    case TCG_COND_LE:
1058
        tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]);
1059
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
1060
        tcg_out_brcond(s, TCG_COND_LE, args[0], args[2], const_args[2], args[5]);
1061
        break;
1062
    case TCG_COND_GT:
1063
        tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
1064
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
1065
        tcg_out_brcond(s, TCG_COND_GT, args[0], args[2], const_args[2], args[5]);
1066
        break;
1067
    case TCG_COND_GE:
1068
        tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]);
1069
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
1070
        tcg_out_brcond(s, TCG_COND_GE, args[0], args[2], const_args[2], args[5]);
1071
        break;
1072
    case TCG_COND_LTU:
1073
        tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
1074
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
1075
        tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]);
1076
        break;
1077
    case TCG_COND_LEU:
1078
        tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]);
1079
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
1080
        tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]);
1081
        break;
1082
    case TCG_COND_GTU:
1083
        tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
1084
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
1085
        tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]);
1086
        break;
1087
    case TCG_COND_GEU:
1088
        tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]);
1089
        tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], label_next);
1090
        tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]);
1091
        break;
1092
    default:
1093
        tcg_abort();
1094
    }
1095
    tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
1096
}
1097

    
1098
static void tcg_out_div2 (TCGContext *s, int uns)
1099
{
1100
    void *label1_ptr, *label2_ptr;
1101

    
1102
    if (uns)
1103
        tcg_out32 (s, CMPLI | BF (7) | RA (3));
1104
    else {
1105
        tcg_out32 (s, SRAWI | RS (4) | RA (0) | 31);
1106
        tcg_out32 (s, CMPL | BF (7) | RA (3) | RB (4));
1107
    }
1108

    
1109
    label1_ptr = s->code_ptr;
1110
    tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
1111

    
1112
    tcg_out_b (s, LK, (tcg_target_long) (uns ? udiv_addr : div_addr));
1113

    
1114
    label2_ptr = s->code_ptr;
1115
    tcg_out32 (s, B);
1116

    
1117
    reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
1118

    
1119
    tcg_out32 (s, (uns ? DIVWU : DIVW) | TAB (6, 4, 5));
1120
    tcg_out32 (s, MULLW | TAB (0, 6, 5));
1121
    tcg_out32 (s, SUBF | TAB (3, 0, 4));
1122

    
1123
    reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
1124
}
1125

    
1126
static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1127
                       const int *const_args)
1128
{
1129
    switch (opc) {
1130
    case INDEX_op_exit_tb:
1131
        tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
1132
        tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1133
        break;
1134
    case INDEX_op_goto_tb:
1135
        if (s->tb_jmp_offset) {
1136
            /* direct jump method */
1137

    
1138
            s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1139
            s->code_ptr += 16;
1140
        }
1141
        else {
1142
            tcg_abort ();
1143
        }
1144
        s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1145
        break;
1146
    case INDEX_op_br:
1147
        {
1148
            TCGLabel *l = &s->labels[args[0]];
1149

    
1150
            if (l->has_value) {
1151
                tcg_out_b (s, 0, l->u.value);
1152
            }
1153
            else {
1154
                uint32_t val = *(uint32_t *) s->code_ptr;
1155

    
1156
                /* Thanks to Andrzej Zaborowski */
1157
                tcg_out32 (s, B | (val & 0x3fffffc));
1158
                tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1159
            }
1160
        }
1161
        break;
1162
    case INDEX_op_call:
1163
        if (const_args[0]) {
1164
            tcg_out_b (s, LK, args[0]);
1165
        }
1166
        else {
1167
            tcg_out32 (s, MTSPR | RS (args[0]) | LR);
1168
            tcg_out32 (s, BCLR | BO_ALWAYS | LK);
1169
        }
1170
        break;
1171
    case INDEX_op_jmp:
1172
        if (const_args[0]) {
1173
            tcg_out_b (s, 0, args[0]);
1174
        }
1175
        else {
1176
            tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1177
            tcg_out32 (s, BCCTR | BO_ALWAYS);
1178
        }
1179
        break;
1180
    case INDEX_op_movi_i32:
1181
        tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1182
        break;
1183
    case INDEX_op_ld8u_i32:
1184
        tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1185
        break;
1186
    case INDEX_op_ld8s_i32:
1187
        tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1188
        tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1189
        break;
1190
    case INDEX_op_ld16u_i32:
1191
        tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1192
        break;
1193
    case INDEX_op_ld16s_i32:
1194
        tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1195
        break;
1196
    case INDEX_op_ld_i32:
1197
        tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1198
        break;
1199
    case INDEX_op_st8_i32:
1200
        tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1201
        break;
1202
    case INDEX_op_st16_i32:
1203
        tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1204
        break;
1205
    case INDEX_op_st_i32:
1206
        tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1207
        break;
1208

    
1209
    case INDEX_op_add_i32:
1210
        if (const_args[2])
1211
            ppc_addi (s, args[0], args[1], args[2]);
1212
        else
1213
            tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1214
        break;
1215
    case INDEX_op_sub_i32:
1216
        if (const_args[2])
1217
            ppc_addi (s, args[0], args[1], -args[2]);
1218
        else
1219
            tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1220
        break;
1221

    
1222
    case INDEX_op_and_i32:
1223
        if (const_args[2]) {
1224
            if (!args[2])
1225
                tcg_out_movi (s, TCG_TYPE_I32, args[0], 0);
1226
            else {
1227
                if ((args[2] & 0xffff) == args[2])
1228
                    tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
1229
                else if ((args[2] & 0xffff0000) == args[2])
1230
                    tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1231
                               | ((args[2] >> 16) & 0xffff));
1232
                else if (args[2] == 0xffffffff) {
1233
                    if (args[0] != args[1])
1234
                        tcg_out_mov (s, args[0], args[1]);
1235
                }
1236
                else {
1237
                    tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1238
                    tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1239
                }
1240
            }
1241
        }
1242
        else
1243
            tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1244
        break;
1245
    case INDEX_op_or_i32:
1246
        if (const_args[2]) {
1247
            if (args[2]) {
1248
                if (args[2] & 0xffff) {
1249
                    tcg_out32 (s, ORI | RS (args[1])  | RA (args[0])
1250
                               | (args[2] & 0xffff));
1251
                    if (args[2] >> 16)
1252
                        tcg_out32 (s, ORIS | RS (args[0])  | RA (args[0])
1253
                                   | ((args[2] >> 16) & 0xffff));
1254
                }
1255
                else {
1256
                    tcg_out32 (s, ORIS | RS (args[1])  | RA (args[0])
1257
                               | ((args[2] >> 16) & 0xffff));
1258
                }
1259
            }
1260
            else {
1261
                if (args[0] != args[1])
1262
                    tcg_out_mov (s, args[0], args[1]);
1263
            }
1264
        }
1265
        else
1266
            tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1267
        break;
1268
    case INDEX_op_xor_i32:
1269
        if (const_args[2]) {
1270
            if (args[2]) {
1271
                if ((args[2] & 0xffff) == args[2])
1272
                    tcg_out32 (s, XORI | RS (args[1])  | RA (args[0])
1273
                               | (args[2] & 0xffff));
1274
                else if ((args[2] & 0xffff0000) == args[2])
1275
                    tcg_out32 (s, XORIS | RS (args[1])  | RA (args[0])
1276
                               | ((args[2] >> 16) & 0xffff));
1277
                else {
1278
                    tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1279
                    tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1280
                }
1281
            }
1282
            else {
1283
                if (args[0] != args[1])
1284
                    tcg_out_mov (s, args[0], args[1]);
1285
            }
1286
        }
1287
        else
1288
            tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1289
        break;
1290

    
1291
    case INDEX_op_mul_i32:
1292
        if (const_args[2]) {
1293
            if (args[2] == (int16_t) args[2])
1294
                tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1295
                           | (args[2] & 0xffff));
1296
            else {
1297
                tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1298
                tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1299
            }
1300
        }
1301
        else
1302
            tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1303
        break;
1304
    case INDEX_op_mulu2_i32:
1305
        if (args[0] == args[2] || args[0] == args[3]) {
1306
            tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1307
            tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1308
            tcg_out_mov (s, args[0], 0);
1309
        }
1310
        else {
1311
            tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1312
            tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1313
        }
1314
        break;
1315
    case INDEX_op_div2_i32:
1316
        tcg_out_div2 (s, 0);
1317
        break;
1318
    case INDEX_op_divu2_i32:
1319
        tcg_out_div2 (s, 1);
1320
        break;
1321

    
1322
    case INDEX_op_shl_i32:
1323
        if (const_args[2]) {
1324
            if (args[2])
1325
                tcg_out32 (s, (RLWINM
1326
                               | RA (args[0])
1327
                               | RS (args[1])
1328
                               | SH (args[2])
1329
                               | MB (0)
1330
                               | ME (31 - args[2])
1331
                               )
1332
                    );
1333
            else
1334
                tcg_out_mov (s, args[0], args[1]);
1335
        }
1336
        else
1337
            tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1338
        break;
1339
    case INDEX_op_shr_i32:
1340
        if (const_args[2]) {
1341
            if (args[2])
1342
                tcg_out32 (s, (RLWINM
1343
                               | RA (args[0])
1344
                               | RS (args[1])
1345
                               | SH (32 - args[2])
1346
                               | MB (args[2])
1347
                               | ME (31)
1348
                               )
1349
                    );
1350
            else
1351
                tcg_out_mov (s, args[0], args[1]);
1352
        }
1353
        else
1354
            tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1355
        break;
1356
    case INDEX_op_sar_i32:
1357
        if (const_args[2])
1358
            tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1359
        else
1360
            tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1361
        break;
1362

    
1363
    case INDEX_op_add2_i32:
1364
        if (args[0] == args[3] || args[0] == args[5]) {
1365
            tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1366
            tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1367
            tcg_out_mov (s, args[0], 0);
1368
        }
1369
        else {
1370
            tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1371
            tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1372
        }
1373
        break;
1374
    case INDEX_op_sub2_i32:
1375
        if (args[0] == args[3] || args[0] == args[5]) {
1376
            tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1377
            tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1378
            tcg_out_mov (s, args[0], 0);
1379
        }
1380
        else {
1381
            tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1382
            tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1383
        }
1384
        break;
1385

    
1386
    case INDEX_op_brcond_i32:
1387
        /*
1388
          args[0] = r0
1389
          args[1] = r1
1390
          args[2] = cond
1391
          args[3] = r1 is const
1392
          args[4] = label_index
1393
        */
1394
        tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1395
        break;
1396
    case INDEX_op_brcond2_i32:
1397
        tcg_out_brcond2(s, args, const_args);
1398
        break;
1399

    
1400
    case INDEX_op_neg_i32:
1401
        tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1402
        break;
1403

    
1404
    case INDEX_op_qemu_ld8u:
1405
        tcg_out_qemu_ld(s, args, 0);
1406
        break;
1407
    case INDEX_op_qemu_ld8s:
1408
        tcg_out_qemu_ld(s, args, 0 | 4);
1409
        break;
1410
    case INDEX_op_qemu_ld16u:
1411
        tcg_out_qemu_ld(s, args, 1);
1412
        break;
1413
    case INDEX_op_qemu_ld16s:
1414
        tcg_out_qemu_ld(s, args, 1 | 4);
1415
        break;
1416
    case INDEX_op_qemu_ld32u:
1417
        tcg_out_qemu_ld(s, args, 2);
1418
        break;
1419
    case INDEX_op_qemu_ld64:
1420
        tcg_out_qemu_ld(s, args, 3);
1421
        break;
1422
    case INDEX_op_qemu_st8:
1423
        tcg_out_qemu_st(s, args, 0);
1424
        break;
1425
    case INDEX_op_qemu_st16:
1426
        tcg_out_qemu_st(s, args, 1);
1427
        break;
1428
    case INDEX_op_qemu_st32:
1429
        tcg_out_qemu_st(s, args, 2);
1430
        break;
1431
    case INDEX_op_qemu_st64:
1432
        tcg_out_qemu_st(s, args, 3);
1433
        break;
1434

    
1435
    default:
1436
        tcg_dump_ops (s, stderr);
1437
        tcg_abort ();
1438
    }
1439
}
1440

    
1441
static const TCGTargetOpDef ppc_op_defs[] = {
1442
    { INDEX_op_exit_tb, { } },
1443
    { INDEX_op_goto_tb, { } },
1444
    { INDEX_op_call, { "ri" } },
1445
    { INDEX_op_jmp, { "ri" } },
1446
    { INDEX_op_br, { } },
1447

    
1448
    { INDEX_op_mov_i32, { "r", "r" } },
1449
    { INDEX_op_movi_i32, { "r" } },
1450
    { INDEX_op_ld8u_i32, { "r", "r" } },
1451
    { INDEX_op_ld8s_i32, { "r", "r" } },
1452
    { INDEX_op_ld16u_i32, { "r", "r" } },
1453
    { INDEX_op_ld16s_i32, { "r", "r" } },
1454
    { INDEX_op_ld_i32, { "r", "r" } },
1455
    { INDEX_op_st8_i32, { "r", "r" } },
1456
    { INDEX_op_st16_i32, { "r", "r" } },
1457
    { INDEX_op_st_i32, { "r", "r" } },
1458

    
1459
    { INDEX_op_add_i32, { "r", "r", "ri" } },
1460
    { INDEX_op_mul_i32, { "r", "r", "ri" } },
1461
    { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1462
    { INDEX_op_div2_i32, { "D", "A", "B", "1", "C" } },
1463
    { INDEX_op_divu2_i32, { "D", "A", "B", "1", "C" } },
1464
    { INDEX_op_sub_i32, { "r", "r", "ri" } },
1465
    { INDEX_op_and_i32, { "r", "r", "ri" } },
1466
    { INDEX_op_or_i32, { "r", "r", "ri" } },
1467
    { INDEX_op_xor_i32, { "r", "r", "ri" } },
1468

    
1469
    { INDEX_op_shl_i32, { "r", "r", "ri" } },
1470
    { INDEX_op_shr_i32, { "r", "r", "ri" } },
1471
    { INDEX_op_sar_i32, { "r", "r", "ri" } },
1472

    
1473
    { INDEX_op_brcond_i32, { "r", "ri" } },
1474

    
1475
    { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1476
    { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1477
    { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1478

    
1479
    { INDEX_op_neg_i32, { "r", "r" } },
1480

    
1481
#if TARGET_LONG_BITS == 32
1482
    { INDEX_op_qemu_ld8u, { "r", "L" } },
1483
    { INDEX_op_qemu_ld8s, { "r", "L" } },
1484
    { INDEX_op_qemu_ld16u, { "r", "L" } },
1485
    { INDEX_op_qemu_ld16s, { "r", "L" } },
1486
    { INDEX_op_qemu_ld32u, { "r", "L" } },
1487
    { INDEX_op_qemu_ld32s, { "r", "L" } },
1488
    { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1489

    
1490
    { INDEX_op_qemu_st8, { "K", "K" } },
1491
    { INDEX_op_qemu_st16, { "K", "K" } },
1492
    { INDEX_op_qemu_st32, { "K", "K" } },
1493
    { INDEX_op_qemu_st64, { "M", "M", "M" } },
1494
#else
1495
    { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1496
    { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1497
    { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1498
    { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1499
    { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1500
    { INDEX_op_qemu_ld32s, { "r", "L", "L" } },
1501
    { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1502

    
1503
    { INDEX_op_qemu_st8, { "K", "K", "K" } },
1504
    { INDEX_op_qemu_st16, { "K", "K", "K" } },
1505
    { INDEX_op_qemu_st32, { "K", "K", "K" } },
1506
    { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1507
#endif
1508

    
1509
    { -1 },
1510
};
1511

    
1512
void tcg_target_init(TCGContext *s)
1513
{
1514
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1515
    tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1516
                     (1 << TCG_REG_R0) |
1517
                     (1 << TCG_REG_R3) |
1518
                     (1 << TCG_REG_R4) |
1519
                     (1 << TCG_REG_R5) |
1520
                     (1 << TCG_REG_R6) |
1521
                     (1 << TCG_REG_R7) |
1522
                     (1 << TCG_REG_R8) |
1523
                     (1 << TCG_REG_R9) |
1524
                     (1 << TCG_REG_R10) |
1525
                     (1 << TCG_REG_R11) |
1526
                     (1 << TCG_REG_R12)
1527
        );
1528

    
1529
    tcg_regset_clear(s->reserved_regs);
1530
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1531
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
1532
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
1533

    
1534
    tcg_add_target_add_op_defs(ppc_op_defs);
1535
}