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/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "pci.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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#include "i2c.h" |
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#include "smbus.h" |
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#include "kvm.h" |
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//#define DEBUG
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/* i82731AB (PIIX4) compatible power management function */
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#define PM_FREQ 3579545 |
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#define ACPI_DBG_IO_ADDR 0xb044 |
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typedef struct PIIX4PMState { |
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PCIDevice dev; |
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uint16_t pmsts; |
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uint16_t pmen; |
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uint16_t pmcntrl; |
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uint8_t apmc; |
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uint8_t apms; |
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QEMUTimer *tmr_timer; |
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int64_t tmr_overflow_time; |
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i2c_bus *smbus; |
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uint8_t smb_stat; |
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uint8_t smb_ctl; |
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uint8_t smb_cmd; |
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uint8_t smb_addr; |
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uint8_t smb_data0; |
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uint8_t smb_data1; |
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uint8_t smb_data[32];
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uint8_t smb_index; |
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qemu_irq irq; |
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} PIIX4PMState; |
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|
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#define RSM_STS (1 << 15) |
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#define PWRBTN_STS (1 << 8) |
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#define RTC_EN (1 << 10) |
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#define PWRBTN_EN (1 << 8) |
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#define GBL_EN (1 << 5) |
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#define TMROF_EN (1 << 0) |
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|
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#define SCI_EN (1 << 0) |
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#define SUS_EN (1 << 13) |
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#define ACPI_ENABLE 0xf1 |
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#define ACPI_DISABLE 0xf0 |
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|
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#define SMBHSTSTS 0x00 |
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#define SMBHSTCNT 0x02 |
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#define SMBHSTCMD 0x03 |
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#define SMBHSTADD 0x04 |
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#define SMBHSTDAT0 0x05 |
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#define SMBHSTDAT1 0x06 |
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#define SMBBLKDAT 0x07 |
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static PIIX4PMState *pm_state;
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static uint32_t get_pmtmr(PIIX4PMState *s)
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{ |
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uint32_t d; |
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
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return d & 0xffffff; |
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} |
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static int get_pmsts(PIIX4PMState *s) |
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{ |
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int64_t d; |
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int pmsts;
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pmsts = s->pmsts; |
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
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if (d >= s->tmr_overflow_time)
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s->pmsts |= TMROF_EN; |
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return pmsts;
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} |
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static void pm_update_sci(PIIX4PMState *s) |
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{ |
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int sci_level, pmsts;
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int64_t expire_time; |
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pmsts = get_pmsts(s); |
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sci_level = (((pmsts & s->pmen) & |
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(RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
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qemu_set_irq(s->irq, sci_level); |
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/* schedule a timer interruption if needed */
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if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
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expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ); |
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qemu_mod_timer(s->tmr_timer, expire_time); |
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} else {
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qemu_del_timer(s->tmr_timer); |
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} |
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} |
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static void pm_tmr_timer(void *opaque) |
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{ |
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PIIX4PMState *s = opaque; |
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pm_update_sci(s); |
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} |
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|
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static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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PIIX4PMState *s = opaque; |
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addr &= 0x3f;
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switch(addr) {
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case 0x00: |
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{ |
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int64_t d; |
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int pmsts;
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pmsts = get_pmsts(s); |
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if (pmsts & val & TMROF_EN) {
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/* if TMRSTS is reset, then compute the new overflow time */
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
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s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; |
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} |
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s->pmsts &= ~val; |
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pm_update_sci(s); |
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} |
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break;
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case 0x02: |
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s->pmen = val; |
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pm_update_sci(s); |
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break;
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case 0x04: |
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{ |
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int sus_typ;
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s->pmcntrl = val & ~(SUS_EN); |
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if (val & SUS_EN) {
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/* change suspend type */
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sus_typ = (val >> 10) & 7; |
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switch(sus_typ) {
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case 0: /* soft power off */ |
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qemu_system_shutdown_request(); |
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break;
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case 1: |
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/* RSM_STS should be set on resume. Pretend that resume
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was caused by power button */
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s->pmsts |= (RSM_STS | PWRBTN_STS); |
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qemu_system_reset_request(); |
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#if defined(TARGET_I386)
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cmos_set_s3_resume(); |
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#endif
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default:
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break;
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} |
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} |
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} |
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break;
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default:
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break;
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} |
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#ifdef DEBUG
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printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
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#endif
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} |
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static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) |
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{ |
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PIIX4PMState *s = opaque; |
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uint32_t val; |
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addr &= 0x3f;
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switch(addr) {
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case 0x00: |
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val = get_pmsts(s); |
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break;
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case 0x02: |
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val = s->pmen; |
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break;
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case 0x04: |
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val = s->pmcntrl; |
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break;
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default:
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val = 0;
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break;
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} |
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#ifdef DEBUG
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printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
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#endif
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return val;
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} |
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static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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// PIIX4PMState *s = opaque;
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addr &= 0x3f;
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#ifdef DEBUG
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printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
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#endif
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} |
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static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) |
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{ |
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PIIX4PMState *s = opaque; |
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uint32_t val; |
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addr &= 0x3f;
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switch(addr) {
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case 0x08: |
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val = get_pmtmr(s); |
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break;
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default:
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val = 0;
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break;
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} |
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#ifdef DEBUG
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printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
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#endif
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return val;
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} |
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static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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PIIX4PMState *s = opaque; |
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addr &= 1;
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#ifdef DEBUG
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printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
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#endif
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if (addr == 0) { |
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s->apmc = val; |
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/* ACPI specs 3.0, 4.7.2.5 */
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if (val == ACPI_ENABLE) {
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s->pmcntrl |= SCI_EN; |
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} else if (val == ACPI_DISABLE) { |
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s->pmcntrl &= ~SCI_EN; |
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} |
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if (s->dev.config[0x5b] & (1 << 1)) { |
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cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); |
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} |
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} else {
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s->apms = val; |
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} |
256 |
} |
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static uint32_t pm_smi_readb(void *opaque, uint32_t addr) |
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{ |
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PIIX4PMState *s = opaque; |
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uint32_t val; |
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addr &= 1;
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if (addr == 0) { |
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val = s->apmc; |
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} else {
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val = s->apms; |
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} |
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#ifdef DEBUG
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printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
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#endif
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return val;
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} |
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static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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#if defined(DEBUG)
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printf("ACPI: DBG: 0x%08x\n", val);
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#endif
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} |
281 |
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static void smb_transaction(PIIX4PMState *s) |
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{ |
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uint8_t prot = (s->smb_ctl >> 2) & 0x07; |
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uint8_t read = s->smb_addr & 0x01;
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uint8_t cmd = s->smb_cmd; |
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uint8_t addr = s->smb_addr >> 1;
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i2c_bus *bus = s->smbus; |
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#ifdef DEBUG
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printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
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#endif
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switch(prot) {
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case 0x0: |
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smbus_quick_command(bus, addr, read); |
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break;
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case 0x1: |
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if (read) {
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s->smb_data0 = smbus_receive_byte(bus, addr); |
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} else {
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smbus_send_byte(bus, addr, cmd); |
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} |
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break;
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case 0x2: |
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if (read) {
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s->smb_data0 = smbus_read_byte(bus, addr, cmd); |
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} else {
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smbus_write_byte(bus, addr, cmd, s->smb_data0); |
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} |
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break;
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case 0x3: |
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if (read) {
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uint16_t val; |
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val = smbus_read_word(bus, addr, cmd); |
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s->smb_data0 = val; |
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s->smb_data1 = val >> 8;
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} else {
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smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
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} |
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break;
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case 0x5: |
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if (read) {
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s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data); |
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} else {
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smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0); |
326 |
} |
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break;
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default:
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goto error;
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} |
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return;
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error:
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s->smb_stat |= 0x04;
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} |
336 |
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static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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PIIX4PMState *s = opaque; |
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addr &= 0x3f;
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#ifdef DEBUG
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printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
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#endif
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switch(addr) {
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case SMBHSTSTS:
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s->smb_stat = 0;
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s->smb_index = 0;
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break;
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case SMBHSTCNT:
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s->smb_ctl = val; |
351 |
if (val & 0x40) |
352 |
smb_transaction(s); |
353 |
break;
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case SMBHSTCMD:
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s->smb_cmd = val; |
356 |
break;
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357 |
case SMBHSTADD:
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s->smb_addr = val; |
359 |
break;
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360 |
case SMBHSTDAT0:
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s->smb_data0 = val; |
362 |
break;
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case SMBHSTDAT1:
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364 |
s->smb_data1 = val; |
365 |
break;
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366 |
case SMBBLKDAT:
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s->smb_data[s->smb_index++] = val; |
368 |
if (s->smb_index > 31) |
369 |
s->smb_index = 0;
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370 |
break;
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371 |
default:
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372 |
break;
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373 |
} |
374 |
} |
375 |
|
376 |
static uint32_t smb_ioport_readb(void *opaque, uint32_t addr) |
377 |
{ |
378 |
PIIX4PMState *s = opaque; |
379 |
uint32_t val; |
380 |
|
381 |
addr &= 0x3f;
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382 |
switch(addr) {
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383 |
case SMBHSTSTS:
|
384 |
val = s->smb_stat; |
385 |
break;
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386 |
case SMBHSTCNT:
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387 |
s->smb_index = 0;
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388 |
val = s->smb_ctl & 0x1f;
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389 |
break;
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390 |
case SMBHSTCMD:
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391 |
val = s->smb_cmd; |
392 |
break;
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393 |
case SMBHSTADD:
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394 |
val = s->smb_addr; |
395 |
break;
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396 |
case SMBHSTDAT0:
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397 |
val = s->smb_data0; |
398 |
break;
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399 |
case SMBHSTDAT1:
|
400 |
val = s->smb_data1; |
401 |
break;
|
402 |
case SMBBLKDAT:
|
403 |
val = s->smb_data[s->smb_index++]; |
404 |
if (s->smb_index > 31) |
405 |
s->smb_index = 0;
|
406 |
break;
|
407 |
default:
|
408 |
val = 0;
|
409 |
break;
|
410 |
} |
411 |
#ifdef DEBUG
|
412 |
printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
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413 |
#endif
|
414 |
return val;
|
415 |
} |
416 |
|
417 |
static void pm_io_space_update(PIIX4PMState *s) |
418 |
{ |
419 |
uint32_t pm_io_base; |
420 |
|
421 |
if (s->dev.config[0x80] & 1) { |
422 |
pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
|
423 |
pm_io_base &= 0xffc0;
|
424 |
|
425 |
/* XXX: need to improve memory and ioport allocation */
|
426 |
#if defined(DEBUG)
|
427 |
printf("PM: mapping to 0x%x\n", pm_io_base);
|
428 |
#endif
|
429 |
register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); |
430 |
register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); |
431 |
register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); |
432 |
register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); |
433 |
} |
434 |
} |
435 |
|
436 |
static void pm_write_config(PCIDevice *d, |
437 |
uint32_t address, uint32_t val, int len)
|
438 |
{ |
439 |
pci_default_write_config(d, address, val, len); |
440 |
if (address == 0x80) |
441 |
pm_io_space_update((PIIX4PMState *)d); |
442 |
} |
443 |
|
444 |
static void pm_save(QEMUFile* f,void *opaque) |
445 |
{ |
446 |
PIIX4PMState *s = opaque; |
447 |
|
448 |
pci_device_save(&s->dev, f); |
449 |
|
450 |
qemu_put_be16s(f, &s->pmsts); |
451 |
qemu_put_be16s(f, &s->pmen); |
452 |
qemu_put_be16s(f, &s->pmcntrl); |
453 |
qemu_put_8s(f, &s->apmc); |
454 |
qemu_put_8s(f, &s->apms); |
455 |
qemu_put_timer(f, s->tmr_timer); |
456 |
qemu_put_be64(f, s->tmr_overflow_time); |
457 |
} |
458 |
|
459 |
static int pm_load(QEMUFile* f,void* opaque,int version_id) |
460 |
{ |
461 |
PIIX4PMState *s = opaque; |
462 |
int ret;
|
463 |
|
464 |
if (version_id > 1) |
465 |
return -EINVAL;
|
466 |
|
467 |
ret = pci_device_load(&s->dev, f); |
468 |
if (ret < 0) |
469 |
return ret;
|
470 |
|
471 |
qemu_get_be16s(f, &s->pmsts); |
472 |
qemu_get_be16s(f, &s->pmen); |
473 |
qemu_get_be16s(f, &s->pmcntrl); |
474 |
qemu_get_8s(f, &s->apmc); |
475 |
qemu_get_8s(f, &s->apms); |
476 |
qemu_get_timer(f, s->tmr_timer); |
477 |
s->tmr_overflow_time=qemu_get_be64(f); |
478 |
|
479 |
pm_io_space_update(s); |
480 |
|
481 |
return 0; |
482 |
} |
483 |
|
484 |
static void piix4_reset(void *opaque) |
485 |
{ |
486 |
PIIX4PMState *s = opaque; |
487 |
uint8_t *pci_conf = s->dev.config; |
488 |
|
489 |
pci_conf[0x58] = 0; |
490 |
pci_conf[0x59] = 0; |
491 |
pci_conf[0x5a] = 0; |
492 |
pci_conf[0x5b] = 0; |
493 |
} |
494 |
|
495 |
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
496 |
qemu_irq sci_irq) |
497 |
{ |
498 |
PIIX4PMState *s; |
499 |
uint8_t *pci_conf; |
500 |
|
501 |
s = (PIIX4PMState *)pci_register_device(bus, |
502 |
"PM", sizeof(PIIX4PMState), |
503 |
devfn, NULL, pm_write_config);
|
504 |
pm_state = s; |
505 |
pci_conf = s->dev.config; |
506 |
pci_conf[0x00] = 0x86; |
507 |
pci_conf[0x01] = 0x80; |
508 |
pci_conf[0x02] = 0x13; |
509 |
pci_conf[0x03] = 0x71; |
510 |
pci_conf[0x06] = 0x80; |
511 |
pci_conf[0x07] = 0x02; |
512 |
pci_conf[0x08] = 0x03; // revision number |
513 |
pci_conf[0x09] = 0x00; |
514 |
pci_conf[0x0a] = 0x80; // other bridge device |
515 |
pci_conf[0x0b] = 0x06; // bridge device |
516 |
pci_conf[0x0e] = 0x00; // header_type |
517 |
pci_conf[0x3d] = 0x01; // interrupt pin 1 |
518 |
|
519 |
pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
520 |
|
521 |
register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s); |
522 |
register_ioport_read(0xb2, 2, 1, pm_smi_readb, s); |
523 |
|
524 |
register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); |
525 |
|
526 |
if (kvm_enabled()) {
|
527 |
/* Mark SMM as already inited to prevent SMM from running. KVM does not
|
528 |
* support SMM mode. */
|
529 |
pci_conf[0x5B] = 0x02; |
530 |
} |
531 |
|
532 |
/* XXX: which specification is used ? The i82731AB has different
|
533 |
mappings */
|
534 |
pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10; |
535 |
pci_conf[0x63] = 0x60; |
536 |
pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) | |
537 |
(serial_hds[1] != NULL ? 0x90 : 0); |
538 |
|
539 |
pci_conf[0x90] = smb_io_base | 1; |
540 |
pci_conf[0x91] = smb_io_base >> 8; |
541 |
pci_conf[0xd2] = 0x09; |
542 |
register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s); |
543 |
register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s); |
544 |
|
545 |
s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s); |
546 |
|
547 |
register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s); |
548 |
|
549 |
s->smbus = i2c_init_bus(); |
550 |
s->irq = sci_irq; |
551 |
qemu_register_reset(piix4_reset, s); |
552 |
|
553 |
return s->smbus;
|
554 |
} |
555 |
|
556 |
#if defined(TARGET_I386)
|
557 |
void qemu_system_powerdown(void) |
558 |
{ |
559 |
if (!pm_state) {
|
560 |
qemu_system_shutdown_request(); |
561 |
} else if (pm_state->pmen & PWRBTN_EN) { |
562 |
pm_state->pmsts |= PWRBTN_EN; |
563 |
pm_update_sci(pm_state); |
564 |
} |
565 |
} |
566 |
#endif
|