root / target-sh4 / op_helper.c @ fad6cb1a
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/*
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* SH4 emulation
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*
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* Copyright (c) 2005 Samuel Tardieu
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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*/
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#include <assert.h> |
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#include "exec.h" |
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#include "helper.h" |
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#ifndef CONFIG_USER_ONLY
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#define MMUSUFFIX _mmu
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#define SHIFT 0 |
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#include "softmmu_template.h" |
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#define SHIFT 1 |
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#include "softmmu_template.h" |
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#define SHIFT 2 |
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#include "softmmu_template.h" |
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#define SHIFT 3 |
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#include "softmmu_template.h" |
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void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
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{ |
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TranslationBlock *tb; |
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CPUState *saved_env; |
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unsigned long pc; |
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int ret;
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/* XXX: hack to restore env in all cases, even if not called from
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generated code */
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saved_env = env; |
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env = cpu_single_env; |
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ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
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if (ret) {
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if (retaddr) {
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/* now we have a real cpu fault */
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pc = (unsigned long) retaddr; |
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tb = tb_find_pc(pc); |
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if (tb) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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cpu_restore_state(tb, env, pc, NULL);
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} |
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} |
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cpu_loop_exit(); |
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} |
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env = saved_env; |
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} |
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#endif
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void helper_ldtlb(void) |
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{ |
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#ifdef CONFIG_USER_ONLY
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/* XXXXX */
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assert(0);
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#else
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cpu_load_tlb(env); |
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#endif
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} |
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void helper_raise_illegal_instruction(void) |
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{ |
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env->exception_index = 0x180;
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cpu_loop_exit(); |
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} |
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void helper_raise_slot_illegal_instruction(void) |
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{ |
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env->exception_index = 0x1a0;
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cpu_loop_exit(); |
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} |
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void helper_raise_fpu_disable(void) |
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{ |
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env->exception_index = 0x800;
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cpu_loop_exit(); |
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} |
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void helper_raise_slot_fpu_disable(void) |
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{ |
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env->exception_index = 0x820;
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cpu_loop_exit(); |
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} |
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void helper_debug(void) |
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{ |
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env->exception_index = EXCP_DEBUG; |
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cpu_loop_exit(); |
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} |
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void helper_sleep(uint32_t next_pc)
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{ |
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env->halted = 1;
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env->exception_index = EXCP_HLT; |
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env->pc = next_pc; |
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cpu_loop_exit(); |
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} |
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void helper_trapa(uint32_t tra)
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{ |
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env->tra = tra << 2;
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env->exception_index = 0x160;
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cpu_loop_exit(); |
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} |
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uint32_t helper_addc(uint32_t arg0, uint32_t arg1) |
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{ |
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uint32_t tmp0, tmp1; |
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tmp1 = arg0 + arg1; |
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tmp0 = arg1; |
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arg1 = tmp1 + (env->sr & 1);
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if (tmp0 > tmp1)
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env->sr |= SR_T; |
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else
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env->sr &= ~SR_T; |
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if (tmp1 > arg1)
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env->sr |= SR_T; |
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return arg1;
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} |
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uint32_t helper_addv(uint32_t arg0, uint32_t arg1) |
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{ |
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uint32_t dest, src, ans; |
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if ((int32_t) arg1 >= 0) |
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dest = 0;
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else
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dest = 1;
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if ((int32_t) arg0 >= 0) |
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src = 0;
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else
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src = 1;
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src += dest; |
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arg1 += arg0; |
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if ((int32_t) arg1 >= 0) |
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ans = 0;
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else
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ans = 1;
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ans += dest; |
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if (src == 0 || src == 2) { |
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if (ans == 1) |
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env->sr |= SR_T; |
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else
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env->sr &= ~SR_T; |
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} else
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env->sr &= ~SR_T; |
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return arg1;
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} |
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#define T (env->sr & SR_T)
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#define Q (env->sr & SR_Q ? 1 : 0) |
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#define M (env->sr & SR_M ? 1 : 0) |
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#define SETT env->sr |= SR_T
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#define CLRT env->sr &= ~SR_T
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#define SETQ env->sr |= SR_Q
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#define CLRQ env->sr &= ~SR_Q
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#define SETM env->sr |= SR_M
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#define CLRM env->sr &= ~SR_M
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uint32_t helper_div1(uint32_t arg0, uint32_t arg1) |
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{ |
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uint32_t tmp0, tmp2; |
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uint8_t old_q, tmp1 = 0xff;
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//printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
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old_q = Q; |
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if ((0x80000000 & arg1) != 0) |
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SETQ; |
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else
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CLRQ; |
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tmp2 = arg0; |
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arg1 <<= 1;
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arg1 |= T; |
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switch (old_q) {
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case 0: |
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switch (M) {
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case 0: |
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tmp0 = arg1; |
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arg1 -= tmp2; |
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tmp1 = arg1 > tmp0; |
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switch (Q) {
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case 0: |
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if (tmp1)
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SETQ; |
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else
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CLRQ; |
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break;
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case 1: |
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if (tmp1 == 0) |
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SETQ; |
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else
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CLRQ; |
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break;
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} |
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break;
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case 1: |
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tmp0 = arg1; |
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arg1 += tmp2; |
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tmp1 = arg1 < tmp0; |
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switch (Q) {
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case 0: |
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if (tmp1 == 0) |
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SETQ; |
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else
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CLRQ; |
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break;
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case 1: |
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if (tmp1)
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SETQ; |
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else
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CLRQ; |
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break;
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} |
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break;
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} |
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break;
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case 1: |
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switch (M) {
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case 0: |
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tmp0 = arg1; |
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arg1 += tmp2; |
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tmp1 = arg1 < tmp0; |
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switch (Q) {
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case 0: |
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if (tmp1)
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SETQ; |
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else
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CLRQ; |
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break;
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case 1: |
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if (tmp1 == 0) |
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SETQ; |
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else
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CLRQ; |
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break;
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} |
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break;
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case 1: |
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tmp0 = arg1; |
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arg1 -= tmp2; |
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tmp1 = arg1 > tmp0; |
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switch (Q) {
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case 0: |
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if (tmp1 == 0) |
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SETQ; |
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else
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CLRQ; |
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break;
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case 1: |
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if (tmp1)
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SETQ; |
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else
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CLRQ; |
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break;
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} |
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break;
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} |
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break;
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} |
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if (Q == M)
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SETT; |
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else
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CLRT; |
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//printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
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return arg1;
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} |
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void helper_macl(uint32_t arg0, uint32_t arg1)
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{ |
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int64_t res; |
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res = ((uint64_t) env->mach << 32) | env->macl;
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res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1; |
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env->mach = (res >> 32) & 0xffffffff; |
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env->macl = res & 0xffffffff;
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if (env->sr & SR_S) {
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if (res < 0) |
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env->mach |= 0xffff0000;
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else
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env->mach &= 0x00007fff;
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} |
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} |
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void helper_macw(uint32_t arg0, uint32_t arg1)
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{ |
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int64_t res; |
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res = ((uint64_t) env->mach << 32) | env->macl;
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res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1; |
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env->mach = (res >> 32) & 0xffffffff; |
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env->macl = res & 0xffffffff;
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if (env->sr & SR_S) {
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if (res < -0x80000000) { |
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env->mach = 1;
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env->macl = 0x80000000;
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} else if (res > 0x000000007fffffff) { |
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env->mach = 1;
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env->macl = 0x7fffffff;
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} |
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} |
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} |
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uint32_t helper_negc(uint32_t arg) |
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{ |
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uint32_t temp; |
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temp = -arg; |
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arg = temp - (env->sr & SR_T); |
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if (0 < temp) |
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env->sr |= SR_T; |
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else
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env->sr &= ~SR_T; |
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if (temp < arg)
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env->sr |= SR_T; |
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return arg;
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} |
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uint32_t helper_subc(uint32_t arg0, uint32_t arg1) |
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{ |
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uint32_t tmp0, tmp1; |
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tmp1 = arg1 - arg0; |
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tmp0 = arg1; |
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arg1 = tmp1 - (env->sr & SR_T); |
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if (tmp0 < tmp1)
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env->sr |= SR_T; |
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else
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env->sr &= ~SR_T; |
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if (tmp1 < arg1)
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env->sr |= SR_T; |
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return arg1;
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} |
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uint32_t helper_subv(uint32_t arg0, uint32_t arg1) |
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{ |
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int32_t dest, src, ans; |
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if ((int32_t) arg1 >= 0) |
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dest = 0;
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else
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dest = 1;
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if ((int32_t) arg0 >= 0) |
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src = 0;
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else
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src = 1;
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src += dest; |
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arg1 -= arg0; |
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if ((int32_t) arg1 >= 0) |
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ans = 0;
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else
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ans = 1;
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ans += dest; |
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if (src == 1) { |
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if (ans == 1) |
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env->sr |= SR_T; |
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else
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env->sr &= ~SR_T; |
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} else
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env->sr &= ~SR_T; |
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return arg1;
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} |
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static inline void set_t(void) |
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{ |
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env->sr |= SR_T; |
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} |
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static inline void clr_t(void) |
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{ |
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env->sr &= ~SR_T; |
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} |
392 |
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void helper_ld_fpscr(uint32_t val)
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{ |
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env->fpscr = val & 0x003fffff;
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if (val & 0x01) |
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set_float_rounding_mode(float_round_to_zero, &env->fp_status); |
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else
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set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
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} |
401 |
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uint32_t helper_fabs_FT(uint32_t t0) |
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{ |
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CPU_FloatU f; |
405 |
f.l = t0; |
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f.f = float32_abs(f.f); |
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return f.l;
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} |
409 |
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uint64_t helper_fabs_DT(uint64_t t0) |
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{ |
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CPU_DoubleU d; |
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d.ll = t0; |
414 |
d.d = float64_abs(d.d); |
415 |
return d.ll;
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} |
417 |
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418 |
uint32_t helper_fadd_FT(uint32_t t0, uint32_t t1) |
419 |
{ |
420 |
CPU_FloatU f0, f1; |
421 |
f0.l = t0; |
422 |
f1.l = t1; |
423 |
f0.f = float32_add(f0.f, f1.f, &env->fp_status); |
424 |
return f0.l;
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425 |
} |
426 |
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427 |
uint64_t helper_fadd_DT(uint64_t t0, uint64_t t1) |
428 |
{ |
429 |
CPU_DoubleU d0, d1; |
430 |
d0.ll = t0; |
431 |
d1.ll = t1; |
432 |
d0.d = float64_add(d0.d, d1.d, &env->fp_status); |
433 |
return d0.ll;
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434 |
} |
435 |
|
436 |
void helper_fcmp_eq_FT(uint32_t t0, uint32_t t1)
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437 |
{ |
438 |
CPU_FloatU f0, f1; |
439 |
f0.l = t0; |
440 |
f1.l = t1; |
441 |
|
442 |
if (float32_compare(f0.f, f1.f, &env->fp_status) == 0) |
443 |
set_t(); |
444 |
else
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445 |
clr_t(); |
446 |
} |
447 |
|
448 |
void helper_fcmp_eq_DT(uint64_t t0, uint64_t t1)
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449 |
{ |
450 |
CPU_DoubleU d0, d1; |
451 |
d0.ll = t0; |
452 |
d1.ll = t1; |
453 |
|
454 |
if (float64_compare(d0.d, d1.d, &env->fp_status) == 0) |
455 |
set_t(); |
456 |
else
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457 |
clr_t(); |
458 |
} |
459 |
|
460 |
void helper_fcmp_gt_FT(uint32_t t0, uint32_t t1)
|
461 |
{ |
462 |
CPU_FloatU f0, f1; |
463 |
f0.l = t0; |
464 |
f1.l = t1; |
465 |
|
466 |
if (float32_compare(f0.f, f1.f, &env->fp_status) == 1) |
467 |
set_t(); |
468 |
else
|
469 |
clr_t(); |
470 |
} |
471 |
|
472 |
void helper_fcmp_gt_DT(uint64_t t0, uint64_t t1)
|
473 |
{ |
474 |
CPU_DoubleU d0, d1; |
475 |
d0.ll = t0; |
476 |
d1.ll = t1; |
477 |
|
478 |
if (float64_compare(d0.d, d1.d, &env->fp_status) == 1) |
479 |
set_t(); |
480 |
else
|
481 |
clr_t(); |
482 |
} |
483 |
|
484 |
uint64_t helper_fcnvsd_FT_DT(uint32_t t0) |
485 |
{ |
486 |
CPU_DoubleU d; |
487 |
CPU_FloatU f; |
488 |
f.l = t0; |
489 |
d.d = float32_to_float64(f.f, &env->fp_status); |
490 |
return d.ll;
|
491 |
} |
492 |
|
493 |
uint32_t helper_fcnvds_DT_FT(uint64_t t0) |
494 |
{ |
495 |
CPU_DoubleU d; |
496 |
CPU_FloatU f; |
497 |
d.ll = t0; |
498 |
f.f = float64_to_float32(d.d, &env->fp_status); |
499 |
return f.l;
|
500 |
} |
501 |
|
502 |
uint32_t helper_fdiv_FT(uint32_t t0, uint32_t t1) |
503 |
{ |
504 |
CPU_FloatU f0, f1; |
505 |
f0.l = t0; |
506 |
f1.l = t1; |
507 |
f0.f = float32_div(f0.f, f1.f, &env->fp_status); |
508 |
return f0.l;
|
509 |
} |
510 |
|
511 |
uint64_t helper_fdiv_DT(uint64_t t0, uint64_t t1) |
512 |
{ |
513 |
CPU_DoubleU d0, d1; |
514 |
d0.ll = t0; |
515 |
d1.ll = t1; |
516 |
d0.d = float64_div(d0.d, d1.d, &env->fp_status); |
517 |
return d0.ll;
|
518 |
} |
519 |
|
520 |
uint32_t helper_float_FT(uint32_t t0) |
521 |
{ |
522 |
CPU_FloatU f; |
523 |
f.f = int32_to_float32(t0, &env->fp_status); |
524 |
return f.l;
|
525 |
} |
526 |
|
527 |
uint64_t helper_float_DT(uint32_t t0) |
528 |
{ |
529 |
CPU_DoubleU d; |
530 |
d.d = int32_to_float64(t0, &env->fp_status); |
531 |
return d.ll;
|
532 |
} |
533 |
|
534 |
uint32_t helper_fmul_FT(uint32_t t0, uint32_t t1) |
535 |
{ |
536 |
CPU_FloatU f0, f1; |
537 |
f0.l = t0; |
538 |
f1.l = t1; |
539 |
f0.f = float32_mul(f0.f, f1.f, &env->fp_status); |
540 |
return f0.l;
|
541 |
} |
542 |
|
543 |
uint64_t helper_fmul_DT(uint64_t t0, uint64_t t1) |
544 |
{ |
545 |
CPU_DoubleU d0, d1; |
546 |
d0.ll = t0; |
547 |
d1.ll = t1; |
548 |
d0.d = float64_mul(d0.d, d1.d, &env->fp_status); |
549 |
return d0.ll;
|
550 |
} |
551 |
|
552 |
uint32_t helper_fneg_T(uint32_t t0) |
553 |
{ |
554 |
CPU_FloatU f; |
555 |
f.l = t0; |
556 |
f.f = float32_chs(f.f); |
557 |
return f.l;
|
558 |
} |
559 |
|
560 |
uint32_t helper_fsqrt_FT(uint32_t t0) |
561 |
{ |
562 |
CPU_FloatU f; |
563 |
f.l = t0; |
564 |
f.f = float32_sqrt(f.f, &env->fp_status); |
565 |
return f.l;
|
566 |
} |
567 |
|
568 |
uint64_t helper_fsqrt_DT(uint64_t t0) |
569 |
{ |
570 |
CPU_DoubleU d; |
571 |
d.ll = t0; |
572 |
d.d = float64_sqrt(d.d, &env->fp_status); |
573 |
return d.ll;
|
574 |
} |
575 |
|
576 |
uint32_t helper_fsub_FT(uint32_t t0, uint32_t t1) |
577 |
{ |
578 |
CPU_FloatU f0, f1; |
579 |
f0.l = t0; |
580 |
f1.l = t1; |
581 |
f0.f = float32_sub(f0.f, f1.f, &env->fp_status); |
582 |
return f0.l;
|
583 |
} |
584 |
|
585 |
uint64_t helper_fsub_DT(uint64_t t0, uint64_t t1) |
586 |
{ |
587 |
CPU_DoubleU d0, d1; |
588 |
d0.ll = t0; |
589 |
d1.ll = t1; |
590 |
d0.d = float64_sub(d0.d, d1.d, &env->fp_status); |
591 |
return d0.ll;
|
592 |
} |
593 |
|
594 |
uint32_t helper_ftrc_FT(uint32_t t0) |
595 |
{ |
596 |
CPU_FloatU f; |
597 |
f.l = t0; |
598 |
return float32_to_int32_round_to_zero(f.f, &env->fp_status);
|
599 |
} |
600 |
|
601 |
uint32_t helper_ftrc_DT(uint64_t t0) |
602 |
{ |
603 |
CPU_DoubleU d; |
604 |
d.ll = t0; |
605 |
return float64_to_int32_round_to_zero(d.d, &env->fp_status);
|
606 |
} |