Revision fafc0b6a

b/target-ppc/kvm.c
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static int cap_interrupt_unset = false;
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static int cap_interrupt_level = false;
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static int cap_segstate;
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#ifdef KVM_CAP_PPC_BOOKE_SREGS
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static int cap_booke_sregs;
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#endif
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/* XXX We have a race condition where we actually have a level triggered
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 *     interrupt, but the infrastructure can't expose that yet, so the guest
......
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    for (i = 0;i < 32; i++)
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        env->gpr[i] = regs.gpr[i];
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#ifdef KVM_CAP_PPC_BOOKE_SREGS
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    if (cap_booke_sregs) {
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        ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
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        if (ret < 0) {
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            return ret;
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        }
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#ifdef KVM_CAP_PPC_BOOKE_SREGS
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        if (sregs.u.e.features & KVM_SREGS_E_BASE) {
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            env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
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            env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
......
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                env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
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            }
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        }
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    }
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#endif
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    }
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#ifdef KVM_CAP_PPC_SEGSTATE
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    if (cap_segstate) {
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        ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
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        if (ret < 0) {
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            return ret;
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        }
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#ifdef KVM_CAP_PPC_SEGSTATE
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        ppc_store_sdr1(env, sregs.u.s.sdr1);
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        /* Sync SLB */
......
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            env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
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            env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
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        }
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    }
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#endif
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    }
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    return 0;
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}

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