Revision fafc0b6a
b/target-ppc/kvm.c | ||
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45 | 45 |
static int cap_interrupt_unset = false; |
46 | 46 |
static int cap_interrupt_level = false; |
47 | 47 |
static int cap_segstate; |
48 |
#ifdef KVM_CAP_PPC_BOOKE_SREGS |
|
49 | 48 |
static int cap_booke_sregs; |
50 |
#endif |
|
51 | 49 |
|
52 | 50 |
/* XXX We have a race condition where we actually have a level triggered |
53 | 51 |
* interrupt, but the infrastructure can't expose that yet, so the guest |
... | ... | |
222 | 220 |
for (i = 0;i < 32; i++) |
223 | 221 |
env->gpr[i] = regs.gpr[i]; |
224 | 222 |
|
225 |
#ifdef KVM_CAP_PPC_BOOKE_SREGS |
|
226 | 223 |
if (cap_booke_sregs) { |
227 | 224 |
ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); |
228 | 225 |
if (ret < 0) { |
229 | 226 |
return ret; |
230 | 227 |
} |
231 | 228 |
|
229 |
#ifdef KVM_CAP_PPC_BOOKE_SREGS |
|
232 | 230 |
if (sregs.u.e.features & KVM_SREGS_E_BASE) { |
233 | 231 |
env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; |
234 | 232 |
env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; |
... | ... | |
325 | 323 |
env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; |
326 | 324 |
} |
327 | 325 |
} |
328 |
} |
|
329 | 326 |
#endif |
327 |
} |
|
330 | 328 |
|
331 |
#ifdef KVM_CAP_PPC_SEGSTATE |
|
332 | 329 |
if (cap_segstate) { |
333 | 330 |
ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); |
334 | 331 |
if (ret < 0) { |
335 | 332 |
return ret; |
336 | 333 |
} |
337 | 334 |
|
335 |
#ifdef KVM_CAP_PPC_SEGSTATE |
|
338 | 336 |
ppc_store_sdr1(env, sregs.u.s.sdr1); |
339 | 337 |
|
340 | 338 |
/* Sync SLB */ |
... | ... | |
357 | 355 |
env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; |
358 | 356 |
env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; |
359 | 357 |
} |
360 |
} |
|
361 | 358 |
#endif |
359 |
} |
|
362 | 360 |
|
363 | 361 |
return 0; |
364 | 362 |
} |
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